1 /******************************************************************************* 2 Copyright (c) 2016 NVIDIA Corporation 3 4 Permission is hereby granted, free of charge, to any person obtaining a copy 5 of this software and associated documentation files (the "Software"), to 6 deal in the Software without restriction, including without limitation the 7 rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 8 sell copies of the Software, and to permit persons to whom the Software is 9 furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be 12 included in all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 DEALINGS IN THE SOFTWARE. 21 22 *******************************************************************************/ 23 24 /* AUTO GENERATED FILE -- DO NOT EDIT */ 25 26 #ifndef __CLA1C0QMD_H__ 27 #define __CLA1C0QMD_H__ 28 29 /* 30 ** Queue Meta Data, Version 00_06 31 */ 32 33 // The below C preprocessor definitions describe "multi-word" structures, where 34 // fields may have bit numbers beyond 32. For example, MW(127:96) means 35 // the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" 36 // syntax is to distinguish from similar "X:Y" single-word definitions: the 37 // macros historically used for single-word definitions would fail with 38 // multi-word definitions. 39 // 40 // See nvmisc.h:DRF_VAL_MW() in the source code of the kernel 41 // interface layer of nvidia.ko for an example of how to manipulate 42 // these MW(X:Y) definitions. 43 44 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) 45 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) 46 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) 47 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) 48 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) 49 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) 50 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) 51 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) 52 #define NVA1C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) 53 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) 54 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) 55 #define NVA1C0_QMDV00_06_QMD_RESERVED_A MW(199:197) 56 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) 57 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 58 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 59 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) 60 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 61 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 62 #define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) 63 #define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 64 #define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 65 #define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) 66 #define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 67 #define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 68 #define NVA1C0_QMDV00_06_QMD_RESERVED_B MW(207:204) 69 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) 70 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) 71 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 72 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 73 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) 74 #define NVA1C0_QMDV00_06_QMD_RESERVED_C MW(249:249) 75 #define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) 76 #define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 77 #define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 78 #define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) 79 #define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 80 #define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 81 #define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) 82 #define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 83 #define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 84 #define NVA1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) 85 #define NVA1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 86 #define NVA1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 87 #define NVA1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) 88 #define NVA1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 89 #define NVA1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 90 #define NVA1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) 91 #define NVA1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 92 #define NVA1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 93 #define NVA1C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) 94 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) 95 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) 96 #define NVA1C0_QMDV00_06_QMD_RESERVED_D MW(335:328) 97 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) 98 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) 99 #define NVA1C0_QMDV00_06_QMD_RESERVED_E MW(365:358) 100 #define NVA1C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) 101 #define NVA1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 102 #define NVA1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 103 #define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) 104 #define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 105 #define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 106 #define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 107 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) 108 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 109 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 110 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) 111 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 112 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 113 #define NVA1C0_QMDV00_06_THROTTLED MW(372:372) 114 #define NVA1C0_QMDV00_06_THROTTLED_FALSE 0x00000000 115 #define NVA1C0_QMDV00_06_THROTTLED_TRUE 0x00000001 116 #define NVA1C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) 117 #define NVA1C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) 118 #define NVA1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) 119 #define NVA1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 120 #define NVA1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 121 #define NVA1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) 122 #define NVA1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 123 #define NVA1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 124 #define NVA1C0_QMDV00_06_SAMPLER_INDEX MW(382:382) 125 #define NVA1C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 126 #define NVA1C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 127 #define NVA1C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) 128 #define NVA1C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) 129 #define NVA1C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) 130 #define NVA1C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) 131 #define NVA1C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) 132 #define NVA1C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) 133 #define NVA1C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) 134 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) 135 #define NVA1C0_QMDV00_06_QMD_RESERVED_F MW(542:536) 136 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) 137 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 138 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 139 #define NVA1C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) 140 #define NVA1C0_QMDV00_06_QMD_RESERVED_G MW(575:562) 141 #define NVA1C0_QMDV00_06_QMD_VERSION MW(579:576) 142 #define NVA1C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) 143 #define NVA1C0_QMDV00_06_QMD_RESERVED_H MW(591:584) 144 #define NVA1C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) 145 #define NVA1C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) 146 #define NVA1C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) 147 #define NVA1C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) 148 #define NVA1C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 149 #define NVA1C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 150 #define NVA1C0_QMDV00_06_QMD_RESERVED_I MW(668:648) 151 #define NVA1C0_QMDV00_06_L1_CONFIGURATION MW(671:669) 152 #define NVA1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 153 #define NVA1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 154 #define NVA1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 155 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) 156 #define NVA1C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) 157 #define NVA1C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) 158 #define NVA1C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) 159 #define NVA1C0_QMDV00_06_QMD_RESERVED_J MW(783:776) 160 #define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) 161 #define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 162 #define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 163 #define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 164 #define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 165 #define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 166 #define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 167 #define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 168 #define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 169 #define NVA1C0_QMDV00_06_QMD_RESERVED_K MW(791:791) 170 #define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) 171 #define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 172 #define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 173 #define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) 174 #define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 175 #define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 176 #define NVA1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) 177 #define NVA1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 178 #define NVA1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 179 #define NVA1C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) 180 #define NVA1C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) 181 #define NVA1C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) 182 #define NVA1C0_QMDV00_06_QMD_RESERVED_L MW(879:872) 183 #define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) 184 #define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 185 #define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 186 #define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 187 #define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 188 #define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 189 #define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 190 #define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 191 #define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 192 #define NVA1C0_QMDV00_06_QMD_RESERVED_M MW(887:887) 193 #define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) 194 #define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 195 #define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 196 #define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) 197 #define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 198 #define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 199 #define NVA1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) 200 #define NVA1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 201 #define NVA1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 202 #define NVA1C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) 203 #define NVA1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) 204 #define NVA1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) 205 #define NVA1C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) 206 #define NVA1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) 207 #define NVA1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 208 #define NVA1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 209 #define NVA1C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) 210 #define NVA1C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) 211 #define NVA1C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) 212 #define NVA1C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) 213 #define NVA1C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) 214 #define NVA1C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) 215 #define NVA1C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) 216 #define NVA1C0_QMDV00_06_SASS_VERSION MW(1535:1528) 217 #define NVA1C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) 218 #define NVA1C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) 219 #define NVA1C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) 220 #define NVA1C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) 221 #define NVA1C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) 222 #define NVA1C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) 223 #define NVA1C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) 224 #define NVA1C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) 225 #define NVA1C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) 226 #define NVA1C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) 227 #define NVA1C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) 228 #define NVA1C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) 229 #define NVA1C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) 230 #define NVA1C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) 231 #define NVA1C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) 232 #define NVA1C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) 233 234 235 /* 236 ** Queue Meta Data, Version 01_07 237 */ 238 239 #define NVA1C0_QMDV01_07_OUTER_PUT MW(30:0) 240 #define NVA1C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) 241 #define NVA1C0_QMDV01_07_OUTER_GET MW(62:32) 242 #define NVA1C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) 243 #define NVA1C0_QMDV01_07_INNER_GET MW(94:64) 244 #define NVA1C0_QMDV01_07_INNER_OVERFLOW MW(95:95) 245 #define NVA1C0_QMDV01_07_INNER_PUT MW(126:96) 246 #define NVA1C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) 247 #define NVA1C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) 248 #define NVA1C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) 249 #define NVA1C0_QMDV01_07_QMD_GROUP_ID MW(197:192) 250 #define NVA1C0_QMDV01_07_QMD_RESERVED_A MW(199:198) 251 #define NVA1C0_QMDV01_07_IS_QUEUE MW(200:200) 252 #define NVA1C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 253 #define NVA1C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 254 #define NVA1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) 255 #define NVA1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 256 #define NVA1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 257 #define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) 258 #define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 259 #define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 260 #define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) 261 #define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 262 #define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 263 #define NVA1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) 264 #define NVA1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 265 #define NVA1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 266 #define NVA1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) 267 #define NVA1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 268 #define NVA1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 269 #define NVA1C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) 270 #define NVA1C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 271 #define NVA1C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 272 #define NVA1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) 273 #define NVA1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 274 #define NVA1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 275 #define NVA1C0_QMDV01_07_QMD_RESERVED_B MW(223:208) 276 #define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) 277 #define NVA1C0_QMDV01_07_QMD_RESERVED_C MW(249:249) 278 #define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) 279 #define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 280 #define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 281 #define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) 282 #define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 283 #define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 284 #define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) 285 #define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 286 #define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 287 #define NVA1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) 288 #define NVA1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 289 #define NVA1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 290 #define NVA1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) 291 #define NVA1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 292 #define NVA1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 293 #define NVA1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) 294 #define NVA1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 295 #define NVA1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 296 #define NVA1C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) 297 #define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) 298 #define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) 299 #define NVA1C0_QMDV01_07_QMD_RESERVED_D MW(335:328) 300 #define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) 301 #define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) 302 #define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) 303 #define NVA1C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) 304 #define NVA1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 305 #define NVA1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 306 #define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) 307 #define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 308 #define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 309 #define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) 310 #define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 311 #define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 312 #define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 313 #define NVA1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) 314 #define NVA1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 315 #define NVA1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 316 #define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) 317 #define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 318 #define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 319 #define NVA1C0_QMDV01_07_THROTTLED MW(372:372) 320 #define NVA1C0_QMDV01_07_THROTTLED_FALSE 0x00000000 321 #define NVA1C0_QMDV01_07_THROTTLED_TRUE 0x00000001 322 #define NVA1C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) 323 #define NVA1C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 324 #define NVA1C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 325 #define NVA1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) 326 #define NVA1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 327 #define NVA1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 328 #define NVA1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) 329 #define NVA1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 330 #define NVA1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 331 #define NVA1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) 332 #define NVA1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 333 #define NVA1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 334 #define NVA1C0_QMDV01_07_SAMPLER_INDEX MW(382:382) 335 #define NVA1C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 336 #define NVA1C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 337 #define NVA1C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) 338 #define NVA1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 339 #define NVA1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 340 #define NVA1C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) 341 #define NVA1C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) 342 #define NVA1C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) 343 #define NVA1C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) 344 #define NVA1C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) 345 #define NVA1C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) 346 #define NVA1C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) 347 #define NVA1C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) 348 #define NVA1C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) 349 #define NVA1C0_QMDV01_07_QMD_RESERVED_G MW(575:562) 350 #define NVA1C0_QMDV01_07_QMD_VERSION MW(579:576) 351 #define NVA1C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) 352 #define NVA1C0_QMDV01_07_QMD_RESERVED_H MW(591:584) 353 #define NVA1C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) 354 #define NVA1C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) 355 #define NVA1C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) 356 #define NVA1C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) 357 #define NVA1C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 358 #define NVA1C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 359 #define NVA1C0_QMDV01_07_QMD_RESERVED_I MW(668:648) 360 #define NVA1C0_QMDV01_07_L1_CONFIGURATION MW(671:669) 361 #define NVA1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 362 #define NVA1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 363 #define NVA1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 364 #define NVA1C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) 365 #define NVA1C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) 366 #define NVA1C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) 367 #define NVA1C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) 368 #define NVA1C0_QMDV01_07_QMD_RESERVED_J MW(783:776) 369 #define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) 370 #define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 371 #define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 372 #define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 373 #define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 374 #define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 375 #define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 376 #define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 377 #define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 378 #define NVA1C0_QMDV01_07_QMD_RESERVED_K MW(791:791) 379 #define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) 380 #define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 381 #define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 382 #define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) 383 #define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 384 #define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 385 #define NVA1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) 386 #define NVA1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 387 #define NVA1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 388 #define NVA1C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) 389 #define NVA1C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) 390 #define NVA1C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) 391 #define NVA1C0_QMDV01_07_QMD_RESERVED_L MW(879:872) 392 #define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) 393 #define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 394 #define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 395 #define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 396 #define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 397 #define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 398 #define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 399 #define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 400 #define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 401 #define NVA1C0_QMDV01_07_QMD_RESERVED_M MW(887:887) 402 #define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) 403 #define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 404 #define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 405 #define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) 406 #define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 407 #define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 408 #define NVA1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) 409 #define NVA1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 410 #define NVA1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 411 #define NVA1C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) 412 #define NVA1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) 413 #define NVA1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) 414 #define NVA1C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) 415 #define NVA1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) 416 #define NVA1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 417 #define NVA1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 418 #define NVA1C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) 419 #define NVA1C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) 420 #define NVA1C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) 421 #define NVA1C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) 422 #define NVA1C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) 423 #define NVA1C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) 424 #define NVA1C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) 425 #define NVA1C0_QMDV01_07_SASS_VERSION MW(1535:1528) 426 #define NVA1C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) 427 #define NVA1C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) 428 #define NVA1C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) 429 #define NVA1C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) 430 #define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) 431 #define NVA1C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) 432 #define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) 433 #define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 434 #define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 435 #define NVA1C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) 436 #define NVA1C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) 437 #define NVA1C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) 438 #define NVA1C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) 439 #define NVA1C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) 440 #define NVA1C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) 441 #define NVA1C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) 442 #define NVA1C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) 443 #define NVA1C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) 444 #define NVA1C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) 445 #define NVA1C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) 446 #define NVA1C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) 447 #define NVA1C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) 448 449 450 451 #endif // #ifndef __CLA1C0QMD_H__ 452