1 /******************************************************************************* 2 Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files (the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and/or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be included in 12 all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 DEALINGS IN THE SOFTWARE. 21 22 *******************************************************************************/ 23 #ifndef _cla26f_h_ 24 #define _cla26f_h_ 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 #include "nvtypes.h" 31 32 /* class KEPLER_CHANNEL_GPFIFO */ 33 /* 34 * Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref, 35 * chapter "User Control Registers". It is documented as device NV_UDMA. 36 * The GPFIFO format itself is also documented in dev_pbdma.ref, 37 * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, 38 * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. 39 * 40 */ 41 #define KEPLER_CHANNEL_GPFIFO_C (0x0000A26F) 42 43 /* pio method data structure */ 44 typedef volatile struct _cla26f_tag0 { 45 NvV32 Reserved00[0x7c0]; 46 } NvA26FTypedef, KEPLER_ChannelGPFifoC; 47 #define NVA26F_TYPEDEF KEPLER_CHANNELChannelGPFifo 48 /* dma flow control data structure */ 49 typedef volatile struct _cla26f_tag1 { 50 NvU32 Ignored00[0x010]; /* 0000-003f*/ 51 NvU32 Put; /* put offset, read/write 0040-0043*/ 52 NvU32 Get; /* get offset, read only 0044-0047*/ 53 NvU32 Reference; /* reference value, read only 0048-004b*/ 54 NvU32 PutHi; /* high order put offset bits 004c-004f*/ 55 NvU32 Ignored01[0x002]; /* 0050-0057*/ 56 NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ 57 NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ 58 NvU32 GetHi; /* high order get offset bits 0060-0063*/ 59 NvU32 Ignored02[0x007]; /* 0064-007f*/ 60 NvU32 Ignored03; /* used to be engine yield 0080-0083*/ 61 NvU32 Ignored04[0x001]; /* 0084-0087*/ 62 NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ 63 NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ 64 NvU32 Ignored05[0x5c]; 65 } NvA26FControl, KeplerCControlGPFifo; 66 /* fields and values */ 67 #define NVA26F_NUMBER_OF_SUBCHANNELS (8) 68 #define NVA26F_SET_OBJECT (0x00000000) 69 #define NVA26F_SET_OBJECT_NVCLASS 15:0 70 #define NVA26F_SET_OBJECT_ENGINE 20:16 71 #define NVA26F_SET_OBJECT_ENGINE_SW 0x0000001f 72 #define NVA26F_ILLEGAL (0x00000004) 73 #define NVA26F_ILLEGAL_HANDLE 31:0 74 #define NVA26F_NOP (0x00000008) 75 #define NVA26F_NOP_HANDLE 31:0 76 #define NVA26F_SEMAPHOREA (0x00000010) 77 #define NVA26F_SEMAPHOREA_OFFSET_UPPER 7:0 78 #define NVA26F_SEMAPHOREB (0x00000014) 79 #define NVA26F_SEMAPHOREB_OFFSET_LOWER 31:2 80 #define NVA26F_SEMAPHOREC (0x00000018) 81 #define NVA26F_SEMAPHOREC_PAYLOAD 31:0 82 #define NVA26F_SEMAPHORED (0x0000001C) 83 #define NVA26F_SEMAPHORED_OPERATION 3:0 84 #define NVA26F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 85 #define NVA26F_SEMAPHORED_OPERATION_RELEASE 0x00000002 86 #define NVA26F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 87 #define NVA26F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 88 #define NVA26F_SEMAPHORED_ACQUIRE_SWITCH 12:12 89 #define NVA26F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 90 #define NVA26F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 91 #define NVA26F_SEMAPHORED_RELEASE_WFI 20:20 92 #define NVA26F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 93 #define NVA26F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 94 #define NVA26F_SEMAPHORED_RELEASE_SIZE 24:24 95 #define NVA26F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 96 #define NVA26F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 97 #define NVA26F_NON_STALL_INTERRUPT (0x00000020) 98 #define NVA26F_NON_STALL_INTERRUPT_HANDLE 31:0 99 #define NVA26F_FB_FLUSH (0x00000024) 100 #define NVA26F_FB_FLUSH_HANDLE 31:0 101 #define NVA26F_MEM_OP_A (0x00000028) 102 #define NVA26F_MEM_OP_A_OPERAND_LOW 31:2 103 #define NVA26F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2 104 #define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30 105 #define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 106 #define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 107 #define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 108 #define NVA26F_MEM_OP_B (0x0000002c) 109 #define NVA26F_MEM_OP_B_OPERAND_HIGH 7:0 110 #define NVA26F_MEM_OP_B_OPERATION 31:27 111 #define NVA26F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005 112 #define NVA26F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009 113 #define NVA26F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e 114 #define NVA26F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f 115 #define NVA26F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010 116 #define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0 117 #define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000 118 #define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001 119 #define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1 120 #define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000 121 #define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001 122 #define NVA26F_SET_REFERENCE (0x00000050) 123 #define NVA26F_SET_REFERENCE_COUNT 31:0 124 #define NVA26F_SYNCPOINTA (0x00000070) 125 #define NVA26F_SYNCPOINTA_PAYLOAD 31:0 126 #define NVA26F_SYNCPOINTB (0x00000074) 127 #define NVA26F_SYNCPOINTB_OPERATION 1:0 128 #define NVA26F_SYNCPOINTB_OPERATION_WAIT 0x00000000 129 #define NVA26F_SYNCPOINTB_OPERATION_INCR 0x00000001 130 #define NVA26F_SYNCPOINTB_OPERATION_BASE_ADD 0x00000002 131 #define NVA26F_SYNCPOINTB_OPERATION_BASE_WRITE 0x00000003 132 #define NVA26F_SYNCPOINTB_WAIT_SWITCH 4:4 133 #define NVA26F_SYNCPOINTB_WAIT_SWITCH_DIS 0x00000000 134 #define NVA26F_SYNCPOINTB_WAIT_SWITCH_EN 0x00000001 135 #define NVA26F_SYNCPOINTB_BASE 5:5 136 #define NVA26F_SYNCPOINTB_BASE_DIS 0x00000000 137 #define NVA26F_SYNCPOINTB_BASE_EN 0x00000001 138 #define NVA26F_SYNCPOINTB_SYNCPT_INDEX 15:8 139 #define NVA26F_SYNCPOINTB_BASE_INDEX 25:20 140 #define NVA26F_WFI (0x00000078) 141 #define NVA26F_WFI_HANDLE 31:0 142 #define NVA26F_CRC_CHECK (0x0000007c) 143 #define NVA26F_CRC_CHECK_VALUE 31:0 144 #define NVA26F_YIELD (0x00000080) 145 #define NVA26F_YIELD_OP 1:0 146 #define NVA26F_YIELD_OP_NOP 0x00000000 147 148 149 /* GPFIFO entry format */ 150 #define NVA26F_GP_ENTRY__SIZE 8 151 #define NVA26F_GP_ENTRY0_FETCH 0:0 152 #define NVA26F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 153 #define NVA26F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 154 #define NVA26F_GP_ENTRY0_GET 31:2 155 #define NVA26F_GP_ENTRY0_OPERAND 31:0 156 #define NVA26F_GP_ENTRY1_GET_HI 7:0 157 #define NVA26F_GP_ENTRY1_PRIV 8:8 158 #define NVA26F_GP_ENTRY1_PRIV_USER 0x00000000 159 #define NVA26F_GP_ENTRY1_PRIV_KERNEL 0x00000001 160 #define NVA26F_GP_ENTRY1_LEVEL 9:9 161 #define NVA26F_GP_ENTRY1_LEVEL_MAIN 0x00000000 162 #define NVA26F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 163 #define NVA26F_GP_ENTRY1_LENGTH 30:10 164 #define NVA26F_GP_ENTRY1_SYNC 31:31 165 #define NVA26F_GP_ENTRY1_SYNC_PROCEED 0x00000000 166 #define NVA26F_GP_ENTRY1_SYNC_WAIT 0x00000001 167 #define NVA26F_GP_ENTRY1_OPCODE 7:0 168 #define NVA26F_GP_ENTRY1_OPCODE_NOP 0x00000000 169 #define NVA26F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 170 #define NVA26F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 171 #define NVA26F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 172 173 /* dma method formats */ 174 #define NVA26F_DMA_METHOD_ADDRESS_OLD 12:2 175 #define NVA26F_DMA_METHOD_ADDRESS 11:0 176 #define NVA26F_DMA_SUBDEVICE_MASK 15:4 177 #define NVA26F_DMA_METHOD_SUBCHANNEL 15:13 178 #define NVA26F_DMA_TERT_OP 17:16 179 #define NVA26F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) 180 #define NVA26F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) 181 #define NVA26F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) 182 #define NVA26F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) 183 #define NVA26F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) 184 #define NVA26F_DMA_METHOD_COUNT_OLD 28:18 185 #define NVA26F_DMA_METHOD_COUNT 28:16 186 #define NVA26F_DMA_IMMD_DATA 28:16 187 #define NVA26F_DMA_SEC_OP 31:29 188 #define NVA26F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) 189 #define NVA26F_DMA_SEC_OP_INC_METHOD (0x00000001) 190 #define NVA26F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) 191 #define NVA26F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) 192 #define NVA26F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) 193 #define NVA26F_DMA_SEC_OP_ONE_INC (0x00000005) 194 #define NVA26F_DMA_SEC_OP_RESERVED6 (0x00000006) 195 #define NVA26F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) 196 /* dma incrementing method format */ 197 #define NVA26F_DMA_INCR_ADDRESS 11:0 198 #define NVA26F_DMA_INCR_SUBCHANNEL 15:13 199 #define NVA26F_DMA_INCR_COUNT 28:16 200 #define NVA26F_DMA_INCR_OPCODE 31:29 201 #define NVA26F_DMA_INCR_OPCODE_VALUE (0x00000001) 202 #define NVA26F_DMA_INCR_DATA 31:0 203 /* dma non-incrementing method format */ 204 #define NVA26F_DMA_NONINCR_ADDRESS 11:0 205 #define NVA26F_DMA_NONINCR_SUBCHANNEL 15:13 206 #define NVA26F_DMA_NONINCR_COUNT 28:16 207 #define NVA26F_DMA_NONINCR_OPCODE 31:29 208 #define NVA26F_DMA_NONINCR_OPCODE_VALUE (0x00000003) 209 #define NVA26F_DMA_NONINCR_DATA 31:0 210 /* dma increment-once method format */ 211 #define NVA26F_DMA_ONEINCR_ADDRESS 11:0 212 #define NVA26F_DMA_ONEINCR_SUBCHANNEL 15:13 213 #define NVA26F_DMA_ONEINCR_COUNT 28:16 214 #define NVA26F_DMA_ONEINCR_OPCODE 31:29 215 #define NVA26F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) 216 #define NVA26F_DMA_ONEINCR_DATA 31:0 217 /* dma no-operation format */ 218 #define NVA26F_DMA_NOP (0x00000000) 219 /* dma immediate-data format */ 220 #define NVA26F_DMA_IMMD_ADDRESS 11:0 221 #define NVA26F_DMA_IMMD_SUBCHANNEL 15:13 222 #define NVA26F_DMA_IMMD_DATA 28:16 223 #define NVA26F_DMA_IMMD_OPCODE 31:29 224 #define NVA26F_DMA_IMMD_OPCODE_VALUE (0x00000004) 225 /* dma set sub-device mask format */ 226 #define NVA26F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 227 #define NVA26F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 228 #define NVA26F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) 229 /* dma store sub-device mask format */ 230 #define NVA26F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 231 #define NVA26F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 232 #define NVA26F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) 233 /* dma use sub-device mask format */ 234 #define NVA26F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 235 #define NVA26F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) 236 /* dma end-segment format */ 237 #define NVA26F_DMA_ENDSEG_OPCODE 31:29 238 #define NVA26F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) 239 /* dma legacy incrementing/non-incrementing formats */ 240 #define NVA26F_DMA_ADDRESS 12:2 241 #define NVA26F_DMA_SUBCH 15:13 242 #define NVA26F_DMA_OPCODE3 17:16 243 #define NVA26F_DMA_OPCODE3_NONE (0x00000000) 244 #define NVA26F_DMA_COUNT 28:18 245 #define NVA26F_DMA_OPCODE 31:29 246 #define NVA26F_DMA_OPCODE_METHOD (0x00000000) 247 #define NVA26F_DMA_OPCODE_NONINC_METHOD (0x00000002) 248 #define NVA26F_DMA_DATA 31:0 249 250 #ifdef __cplusplus 251 }; /* extern "C" */ 252 #endif 253 254 #endif /* _cla26f_h_ */ 255