1 /******************************************************************************* 2 Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files (the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and/or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be included in 12 all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 DEALINGS IN THE SOFTWARE. 21 22 *******************************************************************************/ 23 #ifndef _clb06f_h_ 24 #define _clb06f_h_ 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 #include "nvtypes.h" 31 32 /* class MAXWELL_CHANNEL_GPFIFO */ 33 /* 34 * Documentation for MAXWELL_CHANNEL_GPFIFO can be found in dev_pbdma.ref, 35 * chapter "User Control Registers". It is documented as device NV_UDMA. 36 * The GPFIFO format itself is also documented in dev_pbdma.ref, 37 * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, 38 * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. 39 * 40 */ 41 #define MAXWELL_CHANNEL_GPFIFO_A (0x0000B06F) 42 43 #define NVB06F_TYPEDEF MAXWELL_CHANNELChannelGPFifoA 44 45 /* dma flow control data structure */ 46 typedef volatile struct _clb06f_tag0 { 47 NvU32 Ignored00[0x010]; /* 0000-003f*/ 48 NvU32 Put; /* put offset, read/write 0040-0043*/ 49 NvU32 Get; /* get offset, read only 0044-0047*/ 50 NvU32 Reference; /* reference value, read only 0048-004b*/ 51 NvU32 PutHi; /* high order put offset bits 004c-004f*/ 52 NvU32 Ignored01[0x002]; /* 0050-0057*/ 53 NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ 54 NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ 55 NvU32 GetHi; /* high order get offset bits 0060-0063*/ 56 NvU32 Ignored02[0x007]; /* 0064-007f*/ 57 NvU32 Ignored03; /* used to be engine yield 0080-0083*/ 58 NvU32 Ignored04[0x001]; /* 0084-0087*/ 59 NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ 60 NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ 61 NvU32 Ignored05[0x5c]; 62 } Nvb06FControl, MaxwellAControlGPFifo; 63 64 /* fields and values */ 65 #define NVB06F_NUMBER_OF_SUBCHANNELS (8) 66 #define NVB06F_SET_OBJECT (0x00000000) 67 #define NVB06F_SET_OBJECT_NVCLASS 15:0 68 #define NVB06F_SET_OBJECT_ENGINE 20:16 69 #define NVB06F_SET_OBJECT_ENGINE_SW 0x0000001f 70 #define NVB06F_ILLEGAL (0x00000004) 71 #define NVB06F_ILLEGAL_HANDLE 31:0 72 #define NVB06F_NOP (0x00000008) 73 #define NVB06F_NOP_HANDLE 31:0 74 #define NVB06F_SEMAPHOREA (0x00000010) 75 #define NVB06F_SEMAPHOREA_OFFSET_UPPER 7:0 76 #define NVB06F_SEMAPHOREB (0x00000014) 77 #define NVB06F_SEMAPHOREB_OFFSET_LOWER 31:2 78 #define NVB06F_SEMAPHOREC (0x00000018) 79 #define NVB06F_SEMAPHOREC_PAYLOAD 31:0 80 #define NVB06F_SEMAPHORED (0x0000001C) 81 #define NVB06F_SEMAPHORED_OPERATION 4:0 82 #define NVB06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 83 #define NVB06F_SEMAPHORED_OPERATION_RELEASE 0x00000002 84 #define NVB06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 85 #define NVB06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 86 #define NVB06F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 87 #define NVB06F_SEMAPHORED_ACQUIRE_SWITCH 12:12 88 #define NVB06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 89 #define NVB06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 90 #define NVB06F_SEMAPHORED_RELEASE_WFI 20:20 91 #define NVB06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 92 #define NVB06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 93 #define NVB06F_SEMAPHORED_RELEASE_SIZE 24:24 94 #define NVB06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 95 #define NVB06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 96 #define NVB06F_SEMAPHORED_REDUCTION 30:27 97 #define NVB06F_SEMAPHORED_REDUCTION_MIN 0x00000000 98 #define NVB06F_SEMAPHORED_REDUCTION_MAX 0x00000001 99 #define NVB06F_SEMAPHORED_REDUCTION_XOR 0x00000002 100 #define NVB06F_SEMAPHORED_REDUCTION_AND 0x00000003 101 #define NVB06F_SEMAPHORED_REDUCTION_OR 0x00000004 102 #define NVB06F_SEMAPHORED_REDUCTION_ADD 0x00000005 103 #define NVB06F_SEMAPHORED_REDUCTION_INC 0x00000006 104 #define NVB06F_SEMAPHORED_REDUCTION_DEC 0x00000007 105 #define NVB06F_SEMAPHORED_FORMAT 31:31 106 #define NVB06F_SEMAPHORED_FORMAT_SIGNED 0x00000000 107 #define NVB06F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 108 #define NVB06F_NON_STALL_INTERRUPT (0x00000020) 109 #define NVB06F_NON_STALL_INTERRUPT_HANDLE 31:0 110 #define NVB06F_FB_FLUSH (0x00000024) 111 #define NVB06F_FB_FLUSH_HANDLE 31:0 112 // NOTE - MEM_OP_A and MEM_OP_B have been removed for gm20x to make room for 113 // possible future MEM_OP features. MEM_OP_C/D have identical functionality 114 // to the previous MEM_OP_A/B methods. 115 #define NVB06F_MEM_OP_C (0x00000030) 116 #define NVB06F_MEM_OP_C_OPERAND_LOW 31:2 117 #define NVB06F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 118 #define NVB06F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 119 #define NVB06F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 120 #define NVB06F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 121 #define NVB06F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 122 #define NVB06F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 123 #define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET 11:10 124 #define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 125 #define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 126 #define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 127 #define NVB06F_MEM_OP_C_TLB_INVALIDATE_ADDR_LO 31:12 128 #define NVB06F_MEM_OP_D (0x00000034) 129 #define NVB06F_MEM_OP_D_OPERAND_HIGH 7:0 130 #define NVB06F_MEM_OP_D_OPERATION 31:27 131 #define NVB06F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 132 #define NVB06F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 133 #define NVB06F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d 134 #define NVB06F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e 135 #define NVB06F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f 136 #define NVB06F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 137 #define NVB06F_MEM_OP_D_TLB_INVALIDATE_ADDR_HI 7:0 138 #define NVB06F_SET_REFERENCE (0x00000050) 139 #define NVB06F_SET_REFERENCE_COUNT 31:0 140 #define NVB06F_WFI (0x00000078) 141 #define NVB06F_WFI_SCOPE 0:0 142 #define NVB06F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 143 #define NVB06F_WFI_SCOPE_ALL 0x00000001 144 #define NVB06F_CRC_CHECK (0x0000007c) 145 #define NVB06F_CRC_CHECK_VALUE 31:0 146 #define NVB06F_YIELD (0x00000080) 147 #define NVB06F_YIELD_OP 1:0 148 #define NVB06F_YIELD_OP_NOP 0x00000000 149 #define NVB06F_YIELD_OP_PBDMA_TIMESLICE 0x00000001 150 #define NVB06F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 151 #define NVB06F_YIELD_OP_TSG 0x00000003 152 153 154 /* GPFIFO entry format */ 155 #define NVB06F_GP_ENTRY__SIZE 8 156 #define NVB06F_GP_ENTRY0_FETCH 0:0 157 #define NVB06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 158 #define NVB06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 159 #define NVB06F_GP_ENTRY0_GET 31:2 160 #define NVB06F_GP_ENTRY0_OPERAND 31:0 161 #define NVB06F_GP_ENTRY1_GET_HI 7:0 162 #define NVB06F_GP_ENTRY1_PRIV 8:8 163 #define NVB06F_GP_ENTRY1_PRIV_USER 0x00000000 164 #define NVB06F_GP_ENTRY1_PRIV_KERNEL 0x00000001 165 #define NVB06F_GP_ENTRY1_LEVEL 9:9 166 #define NVB06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 167 #define NVB06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 168 #define NVB06F_GP_ENTRY1_LENGTH 30:10 169 #define NVB06F_GP_ENTRY1_SYNC 31:31 170 #define NVB06F_GP_ENTRY1_SYNC_PROCEED 0x00000000 171 #define NVB06F_GP_ENTRY1_SYNC_WAIT 0x00000001 172 #define NVB06F_GP_ENTRY1_OPCODE 7:0 173 #define NVB06F_GP_ENTRY1_OPCODE_NOP 0x00000000 174 #define NVB06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 175 #define NVB06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 176 #define NVB06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 177 178 /* dma method formats */ 179 #define NVB06F_DMA_METHOD_ADDRESS_OLD 12:2 180 #define NVB06F_DMA_METHOD_ADDRESS 11:0 181 #define NVB06F_DMA_SUBDEVICE_MASK 15:4 182 #define NVB06F_DMA_METHOD_SUBCHANNEL 15:13 183 #define NVB06F_DMA_TERT_OP 17:16 184 #define NVB06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) 185 #define NVB06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) 186 #define NVB06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) 187 #define NVB06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) 188 #define NVB06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) 189 #define NVB06F_DMA_METHOD_COUNT_OLD 28:18 190 #define NVB06F_DMA_METHOD_COUNT 28:16 191 #define NVB06F_DMA_IMMD_DATA 28:16 192 #define NVB06F_DMA_SEC_OP 31:29 193 #define NVB06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) 194 #define NVB06F_DMA_SEC_OP_INC_METHOD (0x00000001) 195 #define NVB06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) 196 #define NVB06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) 197 #define NVB06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) 198 #define NVB06F_DMA_SEC_OP_ONE_INC (0x00000005) 199 #define NVB06F_DMA_SEC_OP_RESERVED6 (0x00000006) 200 #define NVB06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) 201 /* dma incrementing method format */ 202 #define NVB06F_DMA_INCR_ADDRESS 11:0 203 #define NVB06F_DMA_INCR_SUBCHANNEL 15:13 204 #define NVB06F_DMA_INCR_COUNT 28:16 205 #define NVB06F_DMA_INCR_OPCODE 31:29 206 #define NVB06F_DMA_INCR_OPCODE_VALUE (0x00000001) 207 #define NVB06F_DMA_INCR_DATA 31:0 208 /* dma non-incrementing method format */ 209 #define NVB06F_DMA_NONINCR_ADDRESS 11:0 210 #define NVB06F_DMA_NONINCR_SUBCHANNEL 15:13 211 #define NVB06F_DMA_NONINCR_COUNT 28:16 212 #define NVB06F_DMA_NONINCR_OPCODE 31:29 213 #define NVB06F_DMA_NONINCR_OPCODE_VALUE (0x00000003) 214 #define NVB06F_DMA_NONINCR_DATA 31:0 215 /* dma increment-once method format */ 216 #define NVB06F_DMA_ONEINCR_ADDRESS 11:0 217 #define NVB06F_DMA_ONEINCR_SUBCHANNEL 15:13 218 #define NVB06F_DMA_ONEINCR_COUNT 28:16 219 #define NVB06F_DMA_ONEINCR_OPCODE 31:29 220 #define NVB06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) 221 #define NVB06F_DMA_ONEINCR_DATA 31:0 222 /* dma no-operation format */ 223 #define NVB06F_DMA_NOP (0x00000000) 224 /* dma immediate-data format */ 225 #define NVB06F_DMA_IMMD_ADDRESS 11:0 226 #define NVB06F_DMA_IMMD_SUBCHANNEL 15:13 227 #define NVB06F_DMA_IMMD_DATA 28:16 228 #define NVB06F_DMA_IMMD_OPCODE 31:29 229 #define NVB06F_DMA_IMMD_OPCODE_VALUE (0x00000004) 230 /* dma set sub-device mask format */ 231 #define NVB06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 232 #define NVB06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 233 #define NVB06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) 234 /* dma store sub-device mask format */ 235 #define NVB06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 236 #define NVB06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 237 #define NVB06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) 238 /* dma use sub-device mask format */ 239 #define NVB06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 240 #define NVB06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) 241 /* dma end-segment format */ 242 #define NVB06F_DMA_ENDSEG_OPCODE 31:29 243 #define NVB06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) 244 /* dma legacy incrementing/non-incrementing formats */ 245 #define NVB06F_DMA_ADDRESS 12:2 246 #define NVB06F_DMA_SUBCH 15:13 247 #define NVB06F_DMA_OPCODE3 17:16 248 #define NVB06F_DMA_OPCODE3_NONE (0x00000000) 249 #define NVB06F_DMA_COUNT 28:18 250 #define NVB06F_DMA_OPCODE 31:29 251 #define NVB06F_DMA_OPCODE_METHOD (0x00000000) 252 #define NVB06F_DMA_OPCODE_NONINC_METHOD (0x00000002) 253 #define NVB06F_DMA_DATA 31:0 254 255 #ifdef __cplusplus 256 }; /* extern "C" */ 257 #endif 258 259 #endif /* _clb06f_h_ */ 260