1 /******************************************************************************* 2 Copyright (c) 2016 NVIDIA Corporation 3 4 Permission is hereby granted, free of charge, to any person obtaining a copy 5 of this software and associated documentation files (the "Software"), to 6 deal in the Software without restriction, including without limitation the 7 rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 8 sell copies of the Software, and to permit persons to whom the Software is 9 furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be 12 included in all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 DEALINGS IN THE SOFTWARE. 21 22 *******************************************************************************/ 23 24 /* AUTO GENERATED FILE -- DO NOT EDIT */ 25 26 #ifndef __CLB1C0QMD_H__ 27 #define __CLB1C0QMD_H__ 28 29 /* 30 ** Queue Meta Data, Version 00_06 31 */ 32 33 // The below C preprocessor definitions describe "multi-word" structures, where 34 // fields may have bit numbers beyond 32. For example, MW(127:96) means 35 // the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" 36 // syntax is to distinguish from similar "X:Y" single-word definitions: the 37 // macros historically used for single-word definitions would fail with 38 // multi-word definitions. 39 // 40 // See nvmisc.h:DRF_VAL_MW() in the source code of the kernel 41 // interface layer of nvidia.ko for an example of how to manipulate 42 // these MW(X:Y) definitions. 43 44 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) 45 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) 46 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) 47 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) 48 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) 49 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) 50 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) 51 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) 52 #define NVB1C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) 53 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) 54 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) 55 #define NVB1C0_QMDV00_06_QMD_RESERVED_A MW(199:197) 56 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) 57 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 58 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 59 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) 60 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 61 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 62 #define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) 63 #define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 64 #define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 65 #define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) 66 #define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 67 #define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 68 #define NVB1C0_QMDV00_06_QMD_RESERVED_B MW(207:204) 69 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) 70 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) 71 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 72 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 73 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) 74 #define NVB1C0_QMDV00_06_QMD_RESERVED_C MW(249:249) 75 #define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) 76 #define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 77 #define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 78 #define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) 79 #define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 80 #define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 81 #define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) 82 #define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 83 #define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 84 #define NVB1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) 85 #define NVB1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 86 #define NVB1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 87 #define NVB1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) 88 #define NVB1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 89 #define NVB1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 90 #define NVB1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) 91 #define NVB1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 92 #define NVB1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 93 #define NVB1C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) 94 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) 95 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) 96 #define NVB1C0_QMDV00_06_QMD_RESERVED_D MW(335:328) 97 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) 98 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) 99 #define NVB1C0_QMDV00_06_QMD_RESERVED_E MW(365:358) 100 #define NVB1C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) 101 #define NVB1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 102 #define NVB1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 103 #define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) 104 #define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 105 #define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 106 #define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 107 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) 108 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 109 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 110 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) 111 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 112 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 113 #define NVB1C0_QMDV00_06_THROTTLED MW(372:372) 114 #define NVB1C0_QMDV00_06_THROTTLED_FALSE 0x00000000 115 #define NVB1C0_QMDV00_06_THROTTLED_TRUE 0x00000001 116 #define NVB1C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) 117 #define NVB1C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) 118 #define NVB1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) 119 #define NVB1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 120 #define NVB1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 121 #define NVB1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) 122 #define NVB1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 123 #define NVB1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 124 #define NVB1C0_QMDV00_06_SAMPLER_INDEX MW(382:382) 125 #define NVB1C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 126 #define NVB1C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 127 #define NVB1C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) 128 #define NVB1C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) 129 #define NVB1C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) 130 #define NVB1C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) 131 #define NVB1C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) 132 #define NVB1C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) 133 #define NVB1C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) 134 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) 135 #define NVB1C0_QMDV00_06_QMD_RESERVED_F MW(542:536) 136 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) 137 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 138 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 139 #define NVB1C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) 140 #define NVB1C0_QMDV00_06_QMD_RESERVED_G MW(575:562) 141 #define NVB1C0_QMDV00_06_QMD_VERSION MW(579:576) 142 #define NVB1C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) 143 #define NVB1C0_QMDV00_06_QMD_RESERVED_H MW(591:584) 144 #define NVB1C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) 145 #define NVB1C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) 146 #define NVB1C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) 147 #define NVB1C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) 148 #define NVB1C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 149 #define NVB1C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 150 #define NVB1C0_QMDV00_06_QMD_RESERVED_I MW(668:648) 151 #define NVB1C0_QMDV00_06_L1_CONFIGURATION MW(671:669) 152 #define NVB1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 153 #define NVB1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 154 #define NVB1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 155 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) 156 #define NVB1C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) 157 #define NVB1C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) 158 #define NVB1C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) 159 #define NVB1C0_QMDV00_06_QMD_RESERVED_J MW(783:776) 160 #define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) 161 #define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 162 #define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 163 #define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 164 #define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 165 #define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 166 #define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 167 #define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 168 #define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 169 #define NVB1C0_QMDV00_06_QMD_RESERVED_K MW(791:791) 170 #define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) 171 #define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 172 #define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 173 #define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) 174 #define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 175 #define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 176 #define NVB1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) 177 #define NVB1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 178 #define NVB1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 179 #define NVB1C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) 180 #define NVB1C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) 181 #define NVB1C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) 182 #define NVB1C0_QMDV00_06_QMD_RESERVED_L MW(879:872) 183 #define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) 184 #define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 185 #define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 186 #define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 187 #define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 188 #define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 189 #define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 190 #define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 191 #define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 192 #define NVB1C0_QMDV00_06_QMD_RESERVED_M MW(887:887) 193 #define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) 194 #define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 195 #define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 196 #define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) 197 #define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 198 #define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 199 #define NVB1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) 200 #define NVB1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 201 #define NVB1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 202 #define NVB1C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) 203 #define NVB1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) 204 #define NVB1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) 205 #define NVB1C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) 206 #define NVB1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) 207 #define NVB1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 208 #define NVB1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 209 #define NVB1C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) 210 #define NVB1C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) 211 #define NVB1C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) 212 #define NVB1C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) 213 #define NVB1C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) 214 #define NVB1C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) 215 #define NVB1C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) 216 #define NVB1C0_QMDV00_06_SASS_VERSION MW(1535:1528) 217 #define NVB1C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) 218 #define NVB1C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) 219 #define NVB1C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) 220 #define NVB1C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) 221 #define NVB1C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) 222 #define NVB1C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) 223 #define NVB1C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) 224 #define NVB1C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) 225 #define NVB1C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) 226 #define NVB1C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) 227 #define NVB1C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) 228 #define NVB1C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) 229 #define NVB1C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) 230 #define NVB1C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) 231 #define NVB1C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) 232 #define NVB1C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) 233 234 235 /* 236 ** Queue Meta Data, Version 01_07 237 */ 238 239 #define NVB1C0_QMDV01_07_OUTER_PUT MW(30:0) 240 #define NVB1C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) 241 #define NVB1C0_QMDV01_07_OUTER_GET MW(62:32) 242 #define NVB1C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) 243 #define NVB1C0_QMDV01_07_INNER_GET MW(94:64) 244 #define NVB1C0_QMDV01_07_INNER_OVERFLOW MW(95:95) 245 #define NVB1C0_QMDV01_07_INNER_PUT MW(126:96) 246 #define NVB1C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) 247 #define NVB1C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) 248 #define NVB1C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) 249 #define NVB1C0_QMDV01_07_QMD_GROUP_ID MW(197:192) 250 #define NVB1C0_QMDV01_07_SM_GLOBAL_CACHING_ENABLE MW(198:198) 251 #define NVB1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) 252 #define NVB1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 253 #define NVB1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 254 #define NVB1C0_QMDV01_07_IS_QUEUE MW(200:200) 255 #define NVB1C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 256 #define NVB1C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 257 #define NVB1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) 258 #define NVB1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 259 #define NVB1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 260 #define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) 261 #define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 262 #define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 263 #define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) 264 #define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 265 #define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 266 #define NVB1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) 267 #define NVB1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 268 #define NVB1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 269 #define NVB1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) 270 #define NVB1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 271 #define NVB1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 272 #define NVB1C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) 273 #define NVB1C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 274 #define NVB1C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 275 #define NVB1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) 276 #define NVB1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 277 #define NVB1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 278 #define NVB1C0_QMDV01_07_QMD_RESERVED_B MW(223:208) 279 #define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) 280 #define NVB1C0_QMDV01_07_QMD_RESERVED_C MW(249:249) 281 #define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) 282 #define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 283 #define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 284 #define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) 285 #define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 286 #define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 287 #define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) 288 #define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 289 #define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 290 #define NVB1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) 291 #define NVB1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 292 #define NVB1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 293 #define NVB1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) 294 #define NVB1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 295 #define NVB1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 296 #define NVB1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) 297 #define NVB1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 298 #define NVB1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 299 #define NVB1C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) 300 #define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) 301 #define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) 302 #define NVB1C0_QMDV01_07_QMD_RESERVED_D MW(335:328) 303 #define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) 304 #define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) 305 #define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) 306 #define NVB1C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) 307 #define NVB1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 308 #define NVB1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 309 #define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) 310 #define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 311 #define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 312 #define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) 313 #define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 314 #define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 315 #define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 316 #define NVB1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) 317 #define NVB1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 318 #define NVB1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 319 #define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) 320 #define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 321 #define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 322 #define NVB1C0_QMDV01_07_THROTTLED MW(372:372) 323 #define NVB1C0_QMDV01_07_THROTTLED_FALSE 0x00000000 324 #define NVB1C0_QMDV01_07_THROTTLED_TRUE 0x00000001 325 #define NVB1C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) 326 #define NVB1C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 327 #define NVB1C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 328 #define NVB1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) 329 #define NVB1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 330 #define NVB1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 331 #define NVB1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) 332 #define NVB1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 333 #define NVB1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 334 #define NVB1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) 335 #define NVB1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 336 #define NVB1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 337 #define NVB1C0_QMDV01_07_SAMPLER_INDEX MW(382:382) 338 #define NVB1C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 339 #define NVB1C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 340 #define NVB1C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) 341 #define NVB1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 342 #define NVB1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 343 #define NVB1C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) 344 #define NVB1C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) 345 #define NVB1C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) 346 #define NVB1C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) 347 #define NVB1C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) 348 #define NVB1C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) 349 #define NVB1C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) 350 #define NVB1C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) 351 #define NVB1C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) 352 #define NVB1C0_QMDV01_07_QMD_RESERVED_G MW(575:562) 353 #define NVB1C0_QMDV01_07_QMD_VERSION MW(579:576) 354 #define NVB1C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) 355 #define NVB1C0_QMDV01_07_QMD_RESERVED_H MW(591:584) 356 #define NVB1C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) 357 #define NVB1C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) 358 #define NVB1C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) 359 #define NVB1C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) 360 #define NVB1C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 361 #define NVB1C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 362 #define NVB1C0_QMDV01_07_QMD_RESERVED_I MW(668:648) 363 #define NVB1C0_QMDV01_07_L1_CONFIGURATION MW(671:669) 364 #define NVB1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 365 #define NVB1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 366 #define NVB1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 367 #define NVB1C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) 368 #define NVB1C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) 369 #define NVB1C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) 370 #define NVB1C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) 371 #define NVB1C0_QMDV01_07_QMD_RESERVED_J MW(783:776) 372 #define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) 373 #define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 374 #define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 375 #define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 376 #define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 377 #define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 378 #define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 379 #define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 380 #define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 381 #define NVB1C0_QMDV01_07_QMD_RESERVED_K MW(791:791) 382 #define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) 383 #define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 384 #define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 385 #define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) 386 #define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 387 #define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 388 #define NVB1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) 389 #define NVB1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 390 #define NVB1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 391 #define NVB1C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) 392 #define NVB1C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) 393 #define NVB1C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) 394 #define NVB1C0_QMDV01_07_QMD_RESERVED_L MW(879:872) 395 #define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) 396 #define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 397 #define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 398 #define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 399 #define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 400 #define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 401 #define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 402 #define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 403 #define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 404 #define NVB1C0_QMDV01_07_QMD_RESERVED_M MW(887:887) 405 #define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) 406 #define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 407 #define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 408 #define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) 409 #define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 410 #define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 411 #define NVB1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) 412 #define NVB1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 413 #define NVB1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 414 #define NVB1C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) 415 #define NVB1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) 416 #define NVB1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) 417 #define NVB1C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) 418 #define NVB1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) 419 #define NVB1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 420 #define NVB1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 421 #define NVB1C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) 422 #define NVB1C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) 423 #define NVB1C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) 424 #define NVB1C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) 425 #define NVB1C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) 426 #define NVB1C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) 427 #define NVB1C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) 428 #define NVB1C0_QMDV01_07_SASS_VERSION MW(1535:1528) 429 #define NVB1C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) 430 #define NVB1C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) 431 #define NVB1C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) 432 #define NVB1C0_QMDV01_07_HW_ONLY_SCG_TYPE MW(1599:1599) 433 #define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) 434 #define NVB1C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) 435 #define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) 436 #define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 437 #define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 438 #define NVB1C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) 439 #define NVB1C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) 440 #define NVB1C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) 441 #define NVB1C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) 442 #define NVB1C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) 443 #define NVB1C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) 444 #define NVB1C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) 445 #define NVB1C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) 446 #define NVB1C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) 447 #define NVB1C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) 448 #define NVB1C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) 449 #define NVB1C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) 450 #define NVB1C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) 451 452 453 454 #endif // #ifndef __CLB1C0QMD_H__ 455