1 /******************************************************************************* 2 Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files (the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and/or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be included in 12 all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 DEALINGS IN THE SOFTWARE. 21 22 *******************************************************************************/ 23 #ifndef _clc46f_h_ 24 #define _clc46f_h_ 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 #include "nvtypes.h" 31 32 /* class TURING_CHANNEL_GPFIFO */ 33 /* 34 * Documentation for TURING_CHANNEL_GPFIFO can be found in dev_pbdma.ref, 35 * chapter "User Control Registers". It is documented as device NV_UDMA. 36 * The GPFIFO format itself is also documented in dev_pbdma.ref, 37 * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, 38 * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. 39 * 40 * Note there is no .mfs file for this class. 41 */ 42 #define TURING_CHANNEL_GPFIFO_A (0x0000C46F) 43 44 #define NVC46F_TYPEDEF TURING_CHANNELChannelGPFifoA 45 46 /* dma flow control data structure */ 47 typedef volatile struct Nvc46fControl_struct { 48 NvU32 Ignored00[0x010]; /* 0000-003f*/ 49 NvU32 Put; /* put offset, read/write 0040-0043*/ 50 NvU32 Get; /* get offset, read only 0044-0047*/ 51 NvU32 Reference; /* reference value, read only 0048-004b*/ 52 NvU32 PutHi; /* high order put offset bits 004c-004f*/ 53 NvU32 Ignored01[0x002]; /* 0050-0057*/ 54 NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ 55 NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ 56 NvU32 GetHi; /* high order get offset bits 0060-0063*/ 57 NvU32 Ignored02[0x007]; /* 0064-007f*/ 58 NvU32 Ignored03; /* used to be engine yield 0080-0083*/ 59 NvU32 Ignored04[0x001]; /* 0084-0087*/ 60 NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ 61 NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ 62 NvU32 Ignored05[0x5c]; 63 } Nvc46fControl, TuringAControlGPFifo; 64 65 /* fields and values */ 66 #define NVC46F_NUMBER_OF_SUBCHANNELS (8) 67 #define NVC46F_SET_OBJECT (0x00000000) 68 #define NVC46F_SET_OBJECT_NVCLASS 15:0 69 #define NVC46F_SET_OBJECT_ENGINE 20:16 70 #define NVC46F_SET_OBJECT_ENGINE_SW 0x0000001f 71 #define NVC46F_ILLEGAL (0x00000004) 72 #define NVC46F_ILLEGAL_HANDLE 31:0 73 #define NVC46F_NOP (0x00000008) 74 #define NVC46F_NOP_HANDLE 31:0 75 #define NVC46F_SEMAPHOREA (0x00000010) 76 #define NVC46F_SEMAPHOREA_OFFSET_UPPER 7:0 77 #define NVC46F_SEMAPHOREB (0x00000014) 78 #define NVC46F_SEMAPHOREB_OFFSET_LOWER 31:2 79 #define NVC46F_SEMAPHOREC (0x00000018) 80 #define NVC46F_SEMAPHOREC_PAYLOAD 31:0 81 #define NVC46F_SEMAPHORED (0x0000001C) 82 #define NVC46F_SEMAPHORED_OPERATION 4:0 83 #define NVC46F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 84 #define NVC46F_SEMAPHORED_OPERATION_RELEASE 0x00000002 85 #define NVC46F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 86 #define NVC46F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 87 #define NVC46F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 88 #define NVC46F_SEMAPHORED_ACQUIRE_SWITCH 12:12 89 #define NVC46F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 90 #define NVC46F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 91 #define NVC46F_SEMAPHORED_RELEASE_WFI 20:20 92 #define NVC46F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 93 #define NVC46F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 94 #define NVC46F_SEMAPHORED_RELEASE_SIZE 24:24 95 #define NVC46F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 96 #define NVC46F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 97 #define NVC46F_SEMAPHORED_REDUCTION 30:27 98 #define NVC46F_SEMAPHORED_REDUCTION_MIN 0x00000000 99 #define NVC46F_SEMAPHORED_REDUCTION_MAX 0x00000001 100 #define NVC46F_SEMAPHORED_REDUCTION_XOR 0x00000002 101 #define NVC46F_SEMAPHORED_REDUCTION_AND 0x00000003 102 #define NVC46F_SEMAPHORED_REDUCTION_OR 0x00000004 103 #define NVC46F_SEMAPHORED_REDUCTION_ADD 0x00000005 104 #define NVC46F_SEMAPHORED_REDUCTION_INC 0x00000006 105 #define NVC46F_SEMAPHORED_REDUCTION_DEC 0x00000007 106 #define NVC46F_SEMAPHORED_FORMAT 31:31 107 #define NVC46F_SEMAPHORED_FORMAT_SIGNED 0x00000000 108 #define NVC46F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 109 #define NVC46F_NON_STALL_INTERRUPT (0x00000020) 110 #define NVC46F_NON_STALL_INTERRUPT_HANDLE 31:0 111 #define NVC46F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR 112 #define NVC46F_FB_FLUSH_HANDLE 31:0 113 // NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for 114 // specifying the page address for a targeted TLB invalidate and the uTLB for 115 // a targeted REPLAY_CANCEL for UVM. 116 // The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly 117 // rearranged fields. 118 #define NVC46F_MEM_OP_A (0x00000028) 119 #define NVC46F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED 120 #define NVC46F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type 121 #define NVC46F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED 122 #define NVC46F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL 123 #define NVC46F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 124 #define NVC46F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 125 #define NVC46F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 126 #define NVC46F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 127 #define NVC46F_MEM_OP_B (0x0000002c) 128 #define NVC46F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 129 #define NVC46F_MEM_OP_C (0x00000030) 130 #define NVC46F_MEM_OP_C_MEMBAR_TYPE 2:0 131 #define NVC46F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 132 #define NVC46F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 133 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 134 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 135 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED 136 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 137 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 138 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 139 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE 140 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 141 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 142 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 143 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 144 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 145 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 146 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE 147 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 148 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 149 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 150 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL 151 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0 152 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1 153 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2 154 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3 155 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4 156 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5 157 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6 158 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7 159 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below 160 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table 161 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 162 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 163 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 164 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 165 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 166 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 167 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 168 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE 169 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 170 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 171 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 172 #define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE 173 #define NVC46F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0 174 // MEM_OP_D MUST be preceded by MEM_OPs A-C. 175 #define NVC46F_MEM_OP_D (0x00000034) 176 #define NVC46F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE 177 #define NVC46F_MEM_OP_D_OPERATION 31:27 178 #define NVC46F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 179 #define NVC46F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 180 #define NVC46F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a 181 #define NVC46F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d 182 #define NVC46F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e 183 // CLEAN_LINES is an alias for Tegra/GPU IP usage 184 #define NVC46F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e 185 #define NVC46F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f 186 #define NVC46F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 187 #define NVC46F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 188 #define NVC46F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016 189 #define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0 190 #define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000 191 #define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001 192 #define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002 193 #define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003 194 #define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2 195 #define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000 196 #define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001 197 #define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3 198 #define NVC46F_SET_REFERENCE (0x00000050) 199 #define NVC46F_SET_REFERENCE_COUNT 31:0 200 #define NVC46F_SEM_ADDR_LO (0x0000005c) 201 #define NVC46F_SEM_ADDR_LO_OFFSET 31:2 202 #define NVC46F_SEM_ADDR_HI (0x00000060) 203 #define NVC46F_SEM_ADDR_HI_OFFSET 7:0 204 #define NVC46F_SEM_PAYLOAD_LO (0x00000064) 205 #define NVC46F_SEM_PAYLOAD_LO_PAYLOAD 31:0 206 #define NVC46F_SEM_PAYLOAD_HI (0x00000068) 207 #define NVC46F_SEM_PAYLOAD_HI_PAYLOAD 31:0 208 #define NVC46F_SEM_EXECUTE (0x0000006c) 209 #define NVC46F_SEM_EXECUTE_OPERATION 2:0 210 #define NVC46F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 211 #define NVC46F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 212 #define NVC46F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002 213 #define NVC46F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 214 #define NVC46F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004 215 #define NVC46F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005 216 #define NVC46F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006 217 #define NVC46F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 218 #define NVC46F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000 219 #define NVC46F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 220 #define NVC46F_SEM_EXECUTE_RELEASE_WFI 20:20 221 #define NVC46F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 222 #define NVC46F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001 223 #define NVC46F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 224 #define NVC46F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 225 #define NVC46F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001 226 #define NVC46F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 227 #define NVC46F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 228 #define NVC46F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 229 #define NVC46F_SEM_EXECUTE_REDUCTION 30:27 230 #define NVC46F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000 231 #define NVC46F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001 232 #define NVC46F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002 233 #define NVC46F_SEM_EXECUTE_REDUCTION_IAND 0x00000003 234 #define NVC46F_SEM_EXECUTE_REDUCTION_IOR 0x00000004 235 #define NVC46F_SEM_EXECUTE_REDUCTION_IADD 0x00000005 236 #define NVC46F_SEM_EXECUTE_REDUCTION_INC 0x00000006 237 #define NVC46F_SEM_EXECUTE_REDUCTION_DEC 0x00000007 238 #define NVC46F_SEM_EXECUTE_REDUCTION_FORMAT 31:31 239 #define NVC46F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000 240 #define NVC46F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001 241 #define NVC46F_WFI (0x00000078) 242 #define NVC46F_WFI_SCOPE 0:0 243 #define NVC46F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 244 #define NVC46F_WFI_SCOPE_CURRENT_VEID 0x00000000 245 #define NVC46F_WFI_SCOPE_ALL 0x00000001 246 #define NVC46F_CRC_CHECK (0x0000007c) 247 #define NVC46F_CRC_CHECK_VALUE 31:0 248 #define NVC46F_YIELD (0x00000080) 249 #define NVC46F_YIELD_OP 1:0 250 #define NVC46F_YIELD_OP_NOP 0x00000000 251 #define NVC46F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 252 #define NVC46F_YIELD_OP_TSG 0x00000003 253 #define NVC46F_CLEAR_FAULTED (0x00000084) 254 // Note: RM provides the HANDLE as an opaque value; the internal detail fields 255 // are intentionally not exposed to the driver through these defines. 256 #define NVC46F_CLEAR_FAULTED_HANDLE 30:0 257 #define NVC46F_CLEAR_FAULTED_TYPE 31:31 258 #define NVC46F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000 259 #define NVC46F_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001 260 261 262 /* GPFIFO entry format */ 263 #define NVC46F_GP_ENTRY__SIZE 8 264 #define NVC46F_GP_ENTRY0_FETCH 0:0 265 #define NVC46F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 266 #define NVC46F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 267 #define NVC46F_GP_ENTRY0_GET 31:2 268 #define NVC46F_GP_ENTRY0_OPERAND 31:0 269 #define NVC46F_GP_ENTRY1_GET_HI 7:0 270 #define NVC46F_GP_ENTRY1_LEVEL 9:9 271 #define NVC46F_GP_ENTRY1_LEVEL_MAIN 0x00000000 272 #define NVC46F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 273 #define NVC46F_GP_ENTRY1_LENGTH 30:10 274 #define NVC46F_GP_ENTRY1_SYNC 31:31 275 #define NVC46F_GP_ENTRY1_SYNC_PROCEED 0x00000000 276 #define NVC46F_GP_ENTRY1_SYNC_WAIT 0x00000001 277 #define NVC46F_GP_ENTRY1_OPCODE 7:0 278 #define NVC46F_GP_ENTRY1_OPCODE_NOP 0x00000000 279 #define NVC46F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 280 #define NVC46F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 281 #define NVC46F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 282 283 /* dma method formats */ 284 #define NVC46F_DMA_METHOD_ADDRESS_OLD 12:2 285 #define NVC46F_DMA_METHOD_ADDRESS 11:0 286 #define NVC46F_DMA_SUBDEVICE_MASK 15:4 287 #define NVC46F_DMA_METHOD_SUBCHANNEL 15:13 288 #define NVC46F_DMA_TERT_OP 17:16 289 #define NVC46F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) 290 #define NVC46F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) 291 #define NVC46F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) 292 #define NVC46F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) 293 #define NVC46F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) 294 #define NVC46F_DMA_METHOD_COUNT_OLD 28:18 295 #define NVC46F_DMA_METHOD_COUNT 28:16 296 #define NVC46F_DMA_IMMD_DATA 28:16 297 #define NVC46F_DMA_SEC_OP 31:29 298 #define NVC46F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) 299 #define NVC46F_DMA_SEC_OP_INC_METHOD (0x00000001) 300 #define NVC46F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) 301 #define NVC46F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) 302 #define NVC46F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) 303 #define NVC46F_DMA_SEC_OP_ONE_INC (0x00000005) 304 #define NVC46F_DMA_SEC_OP_RESERVED6 (0x00000006) 305 #define NVC46F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) 306 /* dma incrementing method format */ 307 #define NVC46F_DMA_INCR_ADDRESS 11:0 308 #define NVC46F_DMA_INCR_SUBCHANNEL 15:13 309 #define NVC46F_DMA_INCR_COUNT 28:16 310 #define NVC46F_DMA_INCR_OPCODE 31:29 311 #define NVC46F_DMA_INCR_OPCODE_VALUE (0x00000001) 312 #define NVC46F_DMA_INCR_DATA 31:0 313 /* dma non-incrementing method format */ 314 #define NVC46F_DMA_NONINCR_ADDRESS 11:0 315 #define NVC46F_DMA_NONINCR_SUBCHANNEL 15:13 316 #define NVC46F_DMA_NONINCR_COUNT 28:16 317 #define NVC46F_DMA_NONINCR_OPCODE 31:29 318 #define NVC46F_DMA_NONINCR_OPCODE_VALUE (0x00000003) 319 #define NVC46F_DMA_NONINCR_DATA 31:0 320 /* dma increment-once method format */ 321 #define NVC46F_DMA_ONEINCR_ADDRESS 11:0 322 #define NVC46F_DMA_ONEINCR_SUBCHANNEL 15:13 323 #define NVC46F_DMA_ONEINCR_COUNT 28:16 324 #define NVC46F_DMA_ONEINCR_OPCODE 31:29 325 #define NVC46F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) 326 #define NVC46F_DMA_ONEINCR_DATA 31:0 327 /* dma no-operation format */ 328 #define NVC46F_DMA_NOP (0x00000000) 329 /* dma immediate-data format */ 330 #define NVC46F_DMA_IMMD_ADDRESS 11:0 331 #define NVC46F_DMA_IMMD_SUBCHANNEL 15:13 332 #define NVC46F_DMA_IMMD_DATA 28:16 333 #define NVC46F_DMA_IMMD_OPCODE 31:29 334 #define NVC46F_DMA_IMMD_OPCODE_VALUE (0x00000004) 335 /* dma set sub-device mask format */ 336 #define NVC46F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 337 #define NVC46F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 338 #define NVC46F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) 339 /* dma store sub-device mask format */ 340 #define NVC46F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 341 #define NVC46F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 342 #define NVC46F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) 343 /* dma use sub-device mask format */ 344 #define NVC46F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 345 #define NVC46F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) 346 /* dma end-segment format */ 347 #define NVC46F_DMA_ENDSEG_OPCODE 31:29 348 #define NVC46F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) 349 /* dma legacy incrementing/non-incrementing formats */ 350 #define NVC46F_DMA_ADDRESS 12:2 351 #define NVC46F_DMA_SUBCH 15:13 352 #define NVC46F_DMA_OPCODE3 17:16 353 #define NVC46F_DMA_OPCODE3_NONE (0x00000000) 354 #define NVC46F_DMA_COUNT 28:18 355 #define NVC46F_DMA_OPCODE 31:29 356 #define NVC46F_DMA_OPCODE_METHOD (0x00000000) 357 #define NVC46F_DMA_OPCODE_NONINC_METHOD (0x00000002) 358 #define NVC46F_DMA_DATA 31:0 359 360 #ifdef __cplusplus 361 }; /* extern "C" */ 362 #endif 363 364 #endif /* _clc46f_h_ */ 365