1 /*
2 * The PCI Utilities -- Show Capabilities
3 *
4 * Copyright (c) 1997--2018 Martin Mares <[email protected]>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL v2+.
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11 #include <stdio.h>
12 #include <string.h>
13 #include <stdlib.h>
14
15 #include "lspci.h"
16
17 static void
cap_pm(struct device * d,int where,int cap)18 cap_pm(struct device *d, int where, int cap)
19 {
20 int t, b;
21 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
22
23 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
24 if (verbose < 2)
25 return;
26 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
27 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
28 FLAG(cap, PCI_PM_CAP_DSI),
29 FLAG(cap, PCI_PM_CAP_D1),
30 FLAG(cap, PCI_PM_CAP_D2),
31 pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6],
32 FLAG(cap, PCI_PM_CAP_PME_D0),
33 FLAG(cap, PCI_PM_CAP_PME_D1),
34 FLAG(cap, PCI_PM_CAP_PME_D2),
35 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
36 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
37 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
38 return;
39 t = get_conf_word(d, where + PCI_PM_CTRL);
40 printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n",
41 t & PCI_PM_CTRL_STATE_MASK,
42 FLAG(t, PCI_PM_CTRL_NO_SOFT_RST),
43 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
44 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
45 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
46 FLAG(t, PCI_PM_CTRL_PME_STATUS));
47 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
48 if (b)
49 printf("\t\tBridge: PM%c B3%c\n",
50 FLAG(b, PCI_PM_BPCC_ENABLE),
51 FLAG(~b, PCI_PM_PPB_B2_B3));
52 }
53
54 static void
format_agp_rate(int rate,char * buf,int agp3)55 format_agp_rate(int rate, char *buf, int agp3)
56 {
57 char *c = buf;
58 int i;
59
60 for (i=0; i<=2; i++)
61 if (rate & (1 << i))
62 {
63 if (c != buf)
64 *c++ = ',';
65 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
66 }
67 if (c != buf)
68 *c = 0;
69 else
70 strcpy(buf, "<none>");
71 }
72
73 static void
cap_agp(struct device * d,int where,int cap)74 cap_agp(struct device *d, int where, int cap)
75 {
76 u32 t;
77 char rate[16];
78 int ver, rev;
79 int agp3 = 0;
80
81 ver = (cap >> 4) & 0x0f;
82 rev = cap & 0x0f;
83 printf("AGP version %x.%x\n", ver, rev);
84 if (verbose < 2)
85 return;
86 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
87 return;
88 t = get_conf_long(d, where + PCI_AGP_STATUS);
89 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
90 agp3 = 1;
91 format_agp_rate(t & 7, rate, agp3);
92 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
93 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
94 FLAG(t, PCI_AGP_STATUS_ISOCH),
95 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
96 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
97 FLAG(t, PCI_AGP_STATUS_SBA),
98 FLAG(t, PCI_AGP_STATUS_ITA_COH),
99 FLAG(t, PCI_AGP_STATUS_GART64),
100 FLAG(t, PCI_AGP_STATUS_HTRANS),
101 FLAG(t, PCI_AGP_STATUS_64BIT),
102 FLAG(t, PCI_AGP_STATUS_FW),
103 FLAG(t, PCI_AGP_STATUS_AGP3),
104 rate);
105 t = get_conf_long(d, where + PCI_AGP_COMMAND);
106 format_agp_rate(t & 7, rate, agp3);
107 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
108 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
109 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
110 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
111 FLAG(t, PCI_AGP_COMMAND_SBA),
112 FLAG(t, PCI_AGP_COMMAND_AGP),
113 FLAG(t, PCI_AGP_COMMAND_GART64),
114 FLAG(t, PCI_AGP_COMMAND_64BIT),
115 FLAG(t, PCI_AGP_COMMAND_FW),
116 rate);
117 }
118
119 static void
cap_pcix_nobridge(struct device * d,int where)120 cap_pcix_nobridge(struct device *d, int where)
121 {
122 u16 command;
123 u32 status;
124 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
125
126 printf("PCI-X non-bridge device\n");
127
128 if (verbose < 2)
129 return;
130
131 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
132 return;
133
134 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
135 status = get_conf_long(d, where + PCI_PCIX_STATUS);
136 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
137 FLAG(command, PCI_PCIX_COMMAND_DPERE),
138 FLAG(command, PCI_PCIX_COMMAND_ERO),
139 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
140 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
141 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
142 (status & PCI_PCIX_STATUS_BUS) >> 8,
143 (status & PCI_PCIX_STATUS_DEVICE) >> 3,
144 (status & PCI_PCIX_STATUS_FUNCTION),
145 FLAG(status, PCI_PCIX_STATUS_64BIT),
146 FLAG(status, PCI_PCIX_STATUS_133MHZ),
147 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
148 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
149 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
150 1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)),
151 max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23],
152 1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)),
153 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
154 FLAG(status, PCI_PCIX_STATUS_266MHZ),
155 FLAG(status, PCI_PCIX_STATUS_533MHZ));
156 }
157
158 static void
cap_pcix_bridge(struct device * d,int where)159 cap_pcix_bridge(struct device *d, int where)
160 {
161 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
162 u16 secstatus;
163 u32 status, upstcr, downstcr;
164
165 printf("PCI-X bridge device\n");
166
167 if (verbose < 2)
168 return;
169
170 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
171 return;
172
173 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
174 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
175 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
176 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
177 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
178 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
179 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
180 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
181 sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]);
182 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
183 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
184 (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8,
185 (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3,
186 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
187 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
188 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
189 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
190 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
191 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
192 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
193 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
194 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
195 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
196 (upstcr >> 16) & 0xffff);
197 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
198 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
199 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
200 (downstcr >> 16) & 0xffff);
201 }
202
203 static void
cap_pcix(struct device * d,int where)204 cap_pcix(struct device *d, int where)
205 {
206 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
207 {
208 case PCI_HEADER_TYPE_NORMAL:
209 cap_pcix_nobridge(d, where);
210 break;
211 case PCI_HEADER_TYPE_BRIDGE:
212 cap_pcix_bridge(d, where);
213 break;
214 }
215 }
216
217 static inline char *
ht_link_width(unsigned width)218 ht_link_width(unsigned width)
219 {
220 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
221 return widths[width];
222 }
223
224 static inline char *
ht_link_freq(unsigned freq)225 ht_link_freq(unsigned freq)
226 {
227 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
228 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
229 return freqs[freq];
230 }
231
232 static void
cap_ht_pri(struct device * d,int where,int cmd)233 cap_ht_pri(struct device *d, int where, int cmd)
234 {
235 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
236 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
237
238 printf("HyperTransport: Slave or Primary Interface\n");
239 if (verbose < 2)
240 return;
241
242 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
243 return;
244 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
245 if (rid < 0x22 && rid > 0x11)
246 printf("\t\t!!! Possibly incomplete decoding\n");
247
248 printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c",
249 (cmd & PCI_HT_PRI_CMD_BUID),
250 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
251 FLAG(cmd, PCI_HT_PRI_CMD_MH),
252 FLAG(cmd, PCI_HT_PRI_CMD_DD));
253 if (rid >= 0x22)
254 printf(" DUL%c", FLAG(cmd, PCI_HT_PRI_CMD_DUL));
255 printf("\n");
256
257 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
258 printf("\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
259 FLAG(lctr0, PCI_HT_LCTR_CFLE),
260 FLAG(lctr0, PCI_HT_LCTR_CST),
261 FLAG(lctr0, PCI_HT_LCTR_CFE),
262 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
263 FLAG(lctr0, PCI_HT_LCTR_INIT),
264 FLAG(lctr0, PCI_HT_LCTR_EOC),
265 FLAG(lctr0, PCI_HT_LCTR_TXO),
266 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8);
267 if (rid >= 0x22)
268 printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
269 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
270 FLAG(lctr0, PCI_HT_LCTR_LSEN),
271 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
272 FLAG(lctr0, PCI_HT_LCTR_64B));
273 printf("\n");
274
275 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
276 if (rid < 0x22)
277 printf("\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
278 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
279 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
280 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
281 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12));
282 else
283 printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
284 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
285 FLAG(lcnf0, PCI_HT_LCNF_DFI),
286 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
287 FLAG(lcnf0, PCI_HT_LCNF_DFO),
288 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
289 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
290 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
291 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
292
293 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
294 printf("\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
295 FLAG(lctr1, PCI_HT_LCTR_CFLE),
296 FLAG(lctr1, PCI_HT_LCTR_CST),
297 FLAG(lctr1, PCI_HT_LCTR_CFE),
298 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
299 FLAG(lctr1, PCI_HT_LCTR_INIT),
300 FLAG(lctr1, PCI_HT_LCTR_EOC),
301 FLAG(lctr1, PCI_HT_LCTR_TXO),
302 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8);
303 if (rid >= 0x22)
304 printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
305 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
306 FLAG(lctr1, PCI_HT_LCTR_LSEN),
307 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
308 FLAG(lctr1, PCI_HT_LCTR_64B));
309 printf("\n");
310
311 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
312 if (rid < 0x22)
313 printf("\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
314 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
315 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
316 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
317 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12));
318 else
319 printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
320 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
321 FLAG(lcnf1, PCI_HT_LCNF_DFI),
322 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
323 FLAG(lcnf1, PCI_HT_LCNF_DFO),
324 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
325 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
326 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
327 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
328
329 printf("\t\tRevision ID: %u.%02u\n",
330 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
331 if (rid < 0x22)
332 return;
333
334 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
335 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
336 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
337 FLAG(lfrer0, PCI_HT_LFRER_PROT),
338 FLAG(lfrer0, PCI_HT_LFRER_OV),
339 FLAG(lfrer0, PCI_HT_LFRER_EOC),
340 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
341
342 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
343 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
344 FLAG(lfcap0, PCI_HT_LFCAP_200),
345 FLAG(lfcap0, PCI_HT_LFCAP_300),
346 FLAG(lfcap0, PCI_HT_LFCAP_400),
347 FLAG(lfcap0, PCI_HT_LFCAP_500),
348 FLAG(lfcap0, PCI_HT_LFCAP_600),
349 FLAG(lfcap0, PCI_HT_LFCAP_800),
350 FLAG(lfcap0, PCI_HT_LFCAP_1000),
351 FLAG(lfcap0, PCI_HT_LFCAP_1200),
352 FLAG(lfcap0, PCI_HT_LFCAP_1400),
353 FLAG(lfcap0, PCI_HT_LFCAP_1600),
354 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
355
356 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
357 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
358 FLAG(ftr, PCI_HT_FTR_ISOCFC),
359 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
360 FLAG(ftr, PCI_HT_FTR_CRCTM),
361 FLAG(ftr, PCI_HT_FTR_ECTLT),
362 FLAG(ftr, PCI_HT_FTR_64BA),
363 FLAG(ftr, PCI_HT_FTR_UIDRD));
364
365 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
366 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
367 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
368 FLAG(lfrer1, PCI_HT_LFRER_PROT),
369 FLAG(lfrer1, PCI_HT_LFRER_OV),
370 FLAG(lfrer1, PCI_HT_LFRER_EOC),
371 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
372
373 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
374 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
375 FLAG(lfcap1, PCI_HT_LFCAP_200),
376 FLAG(lfcap1, PCI_HT_LFCAP_300),
377 FLAG(lfcap1, PCI_HT_LFCAP_400),
378 FLAG(lfcap1, PCI_HT_LFCAP_500),
379 FLAG(lfcap1, PCI_HT_LFCAP_600),
380 FLAG(lfcap1, PCI_HT_LFCAP_800),
381 FLAG(lfcap1, PCI_HT_LFCAP_1000),
382 FLAG(lfcap1, PCI_HT_LFCAP_1200),
383 FLAG(lfcap1, PCI_HT_LFCAP_1400),
384 FLAG(lfcap1, PCI_HT_LFCAP_1600),
385 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
386
387 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
388 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
389 FLAG(eh, PCI_HT_EH_PFLE),
390 FLAG(eh, PCI_HT_EH_OFLE),
391 FLAG(eh, PCI_HT_EH_PFE),
392 FLAG(eh, PCI_HT_EH_OFE),
393 FLAG(eh, PCI_HT_EH_EOCFE),
394 FLAG(eh, PCI_HT_EH_RFE),
395 FLAG(eh, PCI_HT_EH_CRCFE),
396 FLAG(eh, PCI_HT_EH_SERRFE),
397 FLAG(eh, PCI_HT_EH_CF),
398 FLAG(eh, PCI_HT_EH_RE),
399 FLAG(eh, PCI_HT_EH_PNFE),
400 FLAG(eh, PCI_HT_EH_ONFE),
401 FLAG(eh, PCI_HT_EH_EOCNFE),
402 FLAG(eh, PCI_HT_EH_RNFE),
403 FLAG(eh, PCI_HT_EH_CRCNFE),
404 FLAG(eh, PCI_HT_EH_SERRNFE));
405
406 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
407 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
408 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
409
410 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
411 printf("\t\tBus Number: %02x\n", bn);
412 }
413
414 static void
cap_ht_sec(struct device * d,int where,int cmd)415 cap_ht_sec(struct device *d, int where, int cmd)
416 {
417 u16 lctr, lcnf, ftr, eh;
418 u8 rid, lfrer, lfcap, mbu, mlu;
419 char *fmt;
420
421 printf("HyperTransport: Host or Secondary Interface\n");
422 if (verbose < 2)
423 return;
424
425 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
426 return;
427 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
428 if (rid < 0x22 && rid > 0x11)
429 printf("\t\t!!! Possibly incomplete decoding\n");
430
431 if (rid >= 0x22)
432 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
433 else
434 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
435 printf(fmt,
436 FLAG(cmd, PCI_HT_SEC_CMD_WR),
437 FLAG(cmd, PCI_HT_SEC_CMD_DE),
438 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
439 FLAG(cmd, PCI_HT_SEC_CMD_CS),
440 FLAG(cmd, PCI_HT_SEC_CMD_HH),
441 FLAG(cmd, PCI_HT_SEC_CMD_AS),
442 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
443 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
444 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
445 if (rid >= 0x22)
446 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
447 else
448 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
449 printf(fmt,
450 FLAG(lctr, PCI_HT_LCTR_CFLE),
451 FLAG(lctr, PCI_HT_LCTR_CST),
452 FLAG(lctr, PCI_HT_LCTR_CFE),
453 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
454 FLAG(lctr, PCI_HT_LCTR_INIT),
455 FLAG(lctr, PCI_HT_LCTR_EOC),
456 FLAG(lctr, PCI_HT_LCTR_TXO),
457 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
458 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
459 FLAG(lctr, PCI_HT_LCTR_LSEN),
460 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
461 FLAG(lctr, PCI_HT_LCTR_64B));
462 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
463 if (rid >= 0x22)
464 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
465 else
466 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
467 printf(fmt,
468 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
469 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
470 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
471 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
472 FLAG(lcnf, PCI_HT_LCNF_DFI),
473 FLAG(lcnf, PCI_HT_LCNF_DFO),
474 FLAG(lcnf, PCI_HT_LCNF_DFIE),
475 FLAG(lcnf, PCI_HT_LCNF_DFOE));
476 printf("\t\tRevision ID: %u.%02u\n",
477 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
478 if (rid < 0x22)
479 return;
480 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
481 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
482 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
483 FLAG(lfrer, PCI_HT_LFRER_PROT),
484 FLAG(lfrer, PCI_HT_LFRER_OV),
485 FLAG(lfrer, PCI_HT_LFRER_EOC),
486 FLAG(lfrer, PCI_HT_LFRER_CTLT));
487 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
488 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
489 FLAG(lfcap, PCI_HT_LFCAP_200),
490 FLAG(lfcap, PCI_HT_LFCAP_300),
491 FLAG(lfcap, PCI_HT_LFCAP_400),
492 FLAG(lfcap, PCI_HT_LFCAP_500),
493 FLAG(lfcap, PCI_HT_LFCAP_600),
494 FLAG(lfcap, PCI_HT_LFCAP_800),
495 FLAG(lfcap, PCI_HT_LFCAP_1000),
496 FLAG(lfcap, PCI_HT_LFCAP_1200),
497 FLAG(lfcap, PCI_HT_LFCAP_1400),
498 FLAG(lfcap, PCI_HT_LFCAP_1600),
499 FLAG(lfcap, PCI_HT_LFCAP_VEND));
500 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
501 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
502 FLAG(ftr, PCI_HT_FTR_ISOCFC),
503 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
504 FLAG(ftr, PCI_HT_FTR_CRCTM),
505 FLAG(ftr, PCI_HT_FTR_ECTLT),
506 FLAG(ftr, PCI_HT_FTR_64BA),
507 FLAG(ftr, PCI_HT_FTR_UIDRD),
508 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
509 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
510 if (ftr & PCI_HT_SEC_FTR_EXTRS)
511 {
512 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
513 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
514 FLAG(eh, PCI_HT_EH_PFLE),
515 FLAG(eh, PCI_HT_EH_OFLE),
516 FLAG(eh, PCI_HT_EH_PFE),
517 FLAG(eh, PCI_HT_EH_OFE),
518 FLAG(eh, PCI_HT_EH_EOCFE),
519 FLAG(eh, PCI_HT_EH_RFE),
520 FLAG(eh, PCI_HT_EH_CRCFE),
521 FLAG(eh, PCI_HT_EH_SERRFE),
522 FLAG(eh, PCI_HT_EH_CF),
523 FLAG(eh, PCI_HT_EH_RE),
524 FLAG(eh, PCI_HT_EH_PNFE),
525 FLAG(eh, PCI_HT_EH_ONFE),
526 FLAG(eh, PCI_HT_EH_EOCNFE),
527 FLAG(eh, PCI_HT_EH_RNFE),
528 FLAG(eh, PCI_HT_EH_CRCNFE),
529 FLAG(eh, PCI_HT_EH_SERRNFE));
530 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
531 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
532 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
533 }
534 }
535
536 static void
cap_ht(struct device * d,int where,int cmd)537 cap_ht(struct device *d, int where, int cmd)
538 {
539 int type;
540
541 switch (cmd & PCI_HT_CMD_TYP_HI)
542 {
543 case PCI_HT_CMD_TYP_HI_PRI:
544 cap_ht_pri(d, where, cmd);
545 return;
546 case PCI_HT_CMD_TYP_HI_SEC:
547 cap_ht_sec(d, where, cmd);
548 return;
549 }
550
551 type = cmd & PCI_HT_CMD_TYP;
552 switch (type)
553 {
554 case PCI_HT_CMD_TYP_SW:
555 printf("HyperTransport: Switch\n");
556 break;
557 case PCI_HT_CMD_TYP_IDC:
558 printf("HyperTransport: Interrupt Discovery and Configuration\n");
559 break;
560 case PCI_HT_CMD_TYP_RID:
561 printf("HyperTransport: Revision ID: %u.%02u\n",
562 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
563 break;
564 case PCI_HT_CMD_TYP_UIDC:
565 printf("HyperTransport: UnitID Clumping\n");
566 break;
567 case PCI_HT_CMD_TYP_ECSA:
568 printf("HyperTransport: Extended Configuration Space Access\n");
569 break;
570 case PCI_HT_CMD_TYP_AM:
571 printf("HyperTransport: Address Mapping\n");
572 break;
573 case PCI_HT_CMD_TYP_MSIM:
574 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
575 FLAG(cmd, PCI_HT_MSIM_CMD_EN),
576 FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
577 if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
578 {
579 u32 offl, offh;
580 if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
581 break;
582 offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
583 offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
584 printf("\t\tMapping Address Base: %016" PCI_U64_FMT_X "\n", ((u64)offh << 32) | (offl & ~0xfffff));
585 }
586 break;
587 case PCI_HT_CMD_TYP_DR:
588 printf("HyperTransport: DirectRoute\n");
589 break;
590 case PCI_HT_CMD_TYP_VCS:
591 printf("HyperTransport: VCSet\n");
592 break;
593 case PCI_HT_CMD_TYP_RM:
594 printf("HyperTransport: Retry Mode\n");
595 break;
596 case PCI_HT_CMD_TYP_X86:
597 printf("HyperTransport: X86 (reserved)\n");
598 break;
599 default:
600 printf("HyperTransport: #%02x\n", type >> 11);
601 }
602 }
603
604 static void
cap_msi(struct device * d,int where,int cap)605 cap_msi(struct device *d, int where, int cap)
606 {
607 int is64;
608 u32 t;
609 u16 w;
610
611 printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n",
612 FLAG(cap, PCI_MSI_FLAGS_ENABLE),
613 1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
614 1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
615 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
616 FLAG(cap, PCI_MSI_FLAGS_64BIT));
617 if (verbose < 2)
618 return;
619 is64 = cap & PCI_MSI_FLAGS_64BIT;
620 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
621 return;
622 printf("\t\tAddress: ");
623 if (is64)
624 {
625 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
626 w = get_conf_word(d, where + PCI_MSI_DATA_64);
627 printf("%08x", t);
628 }
629 else
630 w = get_conf_word(d, where + PCI_MSI_DATA_32);
631 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
632 printf("%08x Data: %04x\n", t, w);
633 if (cap & PCI_MSI_FLAGS_MASK_BIT)
634 {
635 u32 mask, pending;
636
637 if (is64)
638 {
639 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
640 return;
641 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
642 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
643 }
644 else
645 {
646 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
647 return;
648 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
649 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
650 }
651 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
652 }
653 }
654
exp_downstream_port(int type)655 static int exp_downstream_port(int type)
656 {
657 return type == PCI_EXP_TYPE_ROOT_PORT ||
658 type == PCI_EXP_TYPE_DOWNSTREAM ||
659 type == PCI_EXP_TYPE_PCIE_BRIDGE; /* PCI/PCI-X to PCIe Bridge */
660 }
661
show_power_limit(int value,int scale)662 static void show_power_limit(int value, int scale)
663 {
664 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
665
666 if (scale == 0 && value == 0xFF)
667 {
668 printf(">600W");
669 return;
670 }
671
672 if (scale == 0 && value >= 0xF0 && value <= 0xFE)
673 value = 250 + 25 * (value - 0xF0);
674
675 printf("%gW", value * scales[scale]);
676 }
677
latency_l0s(int value)678 static const char *latency_l0s(int value)
679 {
680 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
681 return latencies[value];
682 }
683
latency_l1(int value)684 static const char *latency_l1(int value)
685 {
686 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
687 return latencies[value];
688 }
689
cap_express_dev(struct device * d,int where,int type)690 static void cap_express_dev(struct device *d, int where, int type)
691 {
692 u32 t;
693 u16 w;
694
695 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
696 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d",
697 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
698 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1);
699 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
700 printf(", Latency L0s %s, L1 %s",
701 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
702 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
703 printf("\n");
704 printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
705 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
706 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
707 printf(" AttnBtn%c AttnInd%c PwrInd%c",
708 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
709 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
710 printf(" RBE%c",
711 FLAG(t, PCI_EXP_DEVCAP_RBE));
712 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP))
713 printf(" FLReset%c",
714 FLAG(t, PCI_EXP_DEVCAP_FLRESET));
715 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) ||
716 (type == PCI_EXP_TYPE_PCI_BRIDGE))
717 {
718 printf(" SlotPowerLimit ");
719 show_power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26);
720 }
721 printf(" TEE-IO%c", FLAG(t, PCI_EXP_DEVCAP_TEE_IO));
722 printf("\n");
723
724 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
725 printf("\t\tDevCtl:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c\n",
726 FLAG(w, PCI_EXP_DEVCTL_CERE),
727 FLAG(w, PCI_EXP_DEVCTL_NFERE),
728 FLAG(w, PCI_EXP_DEVCTL_FERE),
729 FLAG(w, PCI_EXP_DEVCTL_URRE));
730 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
731 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
732 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
733 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
734 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
735 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
736 if (type == PCI_EXP_TYPE_PCI_BRIDGE)
737 printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
738 if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP)) &&
739 (t & PCI_EXP_DEVCAP_FLRESET))
740 printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
741 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
742 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
743 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
744
745 w = get_conf_word(d, where + PCI_EXP_DEVSTA);
746 printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n",
747 FLAG(w, PCI_EXP_DEVSTA_CED),
748 FLAG(w, PCI_EXP_DEVSTA_NFED),
749 FLAG(w, PCI_EXP_DEVSTA_FED),
750 FLAG(w, PCI_EXP_DEVSTA_URD),
751 FLAG(w, PCI_EXP_DEVSTA_AUXPD),
752 FLAG(w, PCI_EXP_DEVSTA_TRPND));
753 }
754
link_speed(int speed)755 static char *link_speed(int speed)
756 {
757 switch (speed)
758 {
759 case 1:
760 return "2.5GT/s";
761 case 2:
762 return "5GT/s";
763 case 3:
764 return "8GT/s";
765 case 4:
766 return "16GT/s";
767 case 5:
768 return "32GT/s";
769 case 6:
770 return "64GT/s";
771 default:
772 return "unknown";
773 }
774 }
775
link_compare(int type,int sta,int cap)776 static char *link_compare(int type, int sta, int cap)
777 {
778 if (sta > cap)
779 return " (overdriven)";
780 if (sta == cap)
781 return "";
782 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_DOWNSTREAM) ||
783 (type == PCI_EXP_TYPE_PCIE_BRIDGE))
784 return "";
785 return " (downgraded)";
786 }
787
aspm_support(int code)788 static char *aspm_support(int code)
789 {
790 switch (code)
791 {
792 case 0:
793 return "not supported";
794 case 1:
795 return "L0s";
796 case 2:
797 return "L1";
798 case 3:
799 return "L0s L1";
800 default:
801 return "unknown";
802 }
803 }
804
aspm_enabled(int code)805 static const char *aspm_enabled(int code)
806 {
807 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
808 return desc[code];
809 }
810
cap_express_link(struct device * d,int where,int type)811 static void cap_express_link(struct device *d, int where, int type)
812 {
813 u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width;
814 u16 w;
815
816 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
817 aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
818 cap_speed = t & PCI_EXP_LNKCAP_SPEED;
819 cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4;
820 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
821 t >> 24,
822 link_speed(cap_speed), cap_width,
823 aspm_support(aspm));
824 if (aspm)
825 {
826 printf(", Exit Latency ");
827 if (aspm & 1)
828 printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12));
829 if (aspm & 2)
830 printf("%sL1 %s", (aspm & 1) ? ", " : "",
831 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
832 }
833 printf("\n");
834 printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
835 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
836 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
837 FLAG(t, PCI_EXP_LNKCAP_DLLA),
838 FLAG(t, PCI_EXP_LNKCAP_LBNC),
839 FLAG(t, PCI_EXP_LNKCAP_AOC));
840
841 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
842 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
843 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
844 (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
845 printf(" RCB %d bytes,", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
846 printf(" LnkDisable%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
847 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
848 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
849 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
850 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
851 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
852 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
853 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
854
855 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
856 sta_speed = w & PCI_EXP_LNKSTA_SPEED;
857 sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4;
858 printf("\t\tLnkSta:\tSpeed %s%s, Width x%d%s\n",
859 link_speed(sta_speed),
860 link_compare(type, sta_speed, cap_speed),
861 sta_width,
862 link_compare(type, sta_width, cap_width));
863 printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
864 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
865 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
866 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
867 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
868 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
869 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
870 }
871
indicator(int code)872 static const char *indicator(int code)
873 {
874 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
875 return names[code];
876 }
877
cap_express_slot(struct device * d,int where)878 static void cap_express_slot(struct device *d, int where)
879 {
880 u32 t;
881 u16 w;
882
883 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
884 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
885 FLAG(t, PCI_EXP_SLTCAP_ATNB),
886 FLAG(t, PCI_EXP_SLTCAP_PWRC),
887 FLAG(t, PCI_EXP_SLTCAP_MRL),
888 FLAG(t, PCI_EXP_SLTCAP_ATNI),
889 FLAG(t, PCI_EXP_SLTCAP_PWRI),
890 FLAG(t, PCI_EXP_SLTCAP_HPC),
891 FLAG(t, PCI_EXP_SLTCAP_HPS));
892 printf("\t\t\tSlot #%d, PowerLimit ",
893 (t & PCI_EXP_SLTCAP_PSN) >> 19);
894 show_power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15);
895 printf("; Interlock%c NoCompl%c\n",
896 FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
897 FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
898
899 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
900 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
901 FLAG(w, PCI_EXP_SLTCTL_ATNB),
902 FLAG(w, PCI_EXP_SLTCTL_PWRF),
903 FLAG(w, PCI_EXP_SLTCTL_MRLS),
904 FLAG(w, PCI_EXP_SLTCTL_PRSD),
905 FLAG(w, PCI_EXP_SLTCTL_CMDC),
906 FLAG(w, PCI_EXP_SLTCTL_HPIE),
907 FLAG(w, PCI_EXP_SLTCTL_LLCHG));
908 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
909 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
910 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
911 FLAG(w, PCI_EXP_SLTCTL_PWRC),
912 FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
913
914 w = get_conf_word(d, where + PCI_EXP_SLTSTA);
915 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
916 FLAG(w, PCI_EXP_SLTSTA_ATNB),
917 FLAG(w, PCI_EXP_SLTSTA_PWRF),
918 FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
919 FLAG(w, PCI_EXP_SLTSTA_CMDC),
920 FLAG(w, PCI_EXP_SLTSTA_PRES),
921 FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
922 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
923 FLAG(w, PCI_EXP_SLTSTA_MRLS),
924 FLAG(w, PCI_EXP_SLTSTA_PRSD),
925 FLAG(w, PCI_EXP_SLTSTA_LLCHG));
926 }
927
cap_express_root(struct device * d,int where)928 static void cap_express_root(struct device *d, int where)
929 {
930 u32 w;
931
932 w = get_conf_word(d, where + PCI_EXP_RTCAP);
933 printf("\t\tRootCap: CRSVisible%c\n",
934 FLAG(w, PCI_EXP_RTCAP_CRSVIS));
935
936 w = get_conf_word(d, where + PCI_EXP_RTCTL);
937 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
938 FLAG(w, PCI_EXP_RTCTL_SECEE),
939 FLAG(w, PCI_EXP_RTCTL_SENFEE),
940 FLAG(w, PCI_EXP_RTCTL_SEFEE),
941 FLAG(w, PCI_EXP_RTCTL_PMEIE),
942 FLAG(w, PCI_EXP_RTCTL_CRSVIS));
943
944 w = get_conf_long(d, where + PCI_EXP_RTSTA);
945 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
946 w & PCI_EXP_RTSTA_PME_REQID,
947 FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
948 FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
949 }
950
cap_express_dev2_timeout_range(int type)951 static const char *cap_express_dev2_timeout_range(int type)
952 {
953 /* Decode Completion Timeout Ranges. */
954 switch (type)
955 {
956 case 0:
957 return "Not Supported";
958 case 1:
959 return "Range A";
960 case 2:
961 return "Range B";
962 case 3:
963 return "Range AB";
964 case 6:
965 return "Range BC";
966 case 7:
967 return "Range ABC";
968 case 14:
969 return "Range BCD";
970 case 15:
971 return "Range ABCD";
972 default:
973 return "Unknown";
974 }
975 }
976
cap_express_dev2_timeout_value(int type)977 static const char *cap_express_dev2_timeout_value(int type)
978 {
979 /* Decode Completion Timeout Value. */
980 switch (type)
981 {
982 case 0:
983 return "50us to 50ms";
984 case 1:
985 return "50us to 100us";
986 case 2:
987 return "1ms to 10ms";
988 case 5:
989 return "16ms to 55ms";
990 case 6:
991 return "65ms to 210ms";
992 case 9:
993 return "260ms to 900ms";
994 case 10:
995 return "1s to 3.5s";
996 case 13:
997 return "4s to 13s";
998 case 14:
999 return "17s to 64s";
1000 default:
1001 return "Unknown";
1002 }
1003 }
1004
cap_express_devcap2_obff(int obff)1005 static const char *cap_express_devcap2_obff(int obff)
1006 {
1007 switch (obff)
1008 {
1009 case 1:
1010 return "Via message";
1011 case 2:
1012 return "Via WAKE#";
1013 case 3:
1014 return "Via message/WAKE#";
1015 default:
1016 return "Not Supported";
1017 }
1018 }
1019
cap_express_devcap2_epr(int epr)1020 static const char *cap_express_devcap2_epr(int epr)
1021 {
1022 switch (epr)
1023 {
1024 case 1:
1025 return "Dev Specific";
1026 case 2:
1027 return "Form Factor Dev Specific";
1028 case 3:
1029 return "Reserved";
1030 default:
1031 return "Not Supported";
1032 }
1033 }
1034
cap_express_devcap2_lncls(int lncls)1035 static const char *cap_express_devcap2_lncls(int lncls)
1036 {
1037 switch (lncls)
1038 {
1039 case 1:
1040 return "64byte cachelines";
1041 case 2:
1042 return "128byte cachelines";
1043 case 3:
1044 return "Reserved";
1045 default:
1046 return "Not Supported";
1047 }
1048 }
1049
cap_express_devcap2_tphcomp(int tph)1050 static const char *cap_express_devcap2_tphcomp(int tph)
1051 {
1052 switch (tph)
1053 {
1054 case 1:
1055 return "TPHComp+ ExtTPHComp-";
1056 case 2:
1057 /* Reserved; intentionally left blank */
1058 return "";
1059 case 3:
1060 return "TPHComp+ ExtTPHComp+";
1061 default:
1062 return "TPHComp- ExtTPHComp-";
1063 }
1064 }
1065
cap_express_devctl2_obff(int obff)1066 static const char *cap_express_devctl2_obff(int obff)
1067 {
1068 switch (obff)
1069 {
1070 case 0:
1071 return "Disabled";
1072 case 1:
1073 return "Via message A";
1074 case 2:
1075 return "Via message B";
1076 case 3:
1077 return "Via WAKE#";
1078 default:
1079 return "Unknown";
1080 }
1081 }
1082
1083 static int
device_has_memory_space_bar(struct device * d)1084 device_has_memory_space_bar(struct device *d)
1085 {
1086 struct pci_dev *p = d->dev;
1087 int i, found = 0;
1088
1089 for (i=0; i<6; i++)
1090 if (p->base_addr[i] || p->size[i])
1091 {
1092 if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO))
1093 {
1094 found = 1;
1095 break;
1096 }
1097 }
1098 return found;
1099 }
1100
cap_express_dev2(struct device * d,int where,int type)1101 static void cap_express_dev2(struct device *d, int where, int type)
1102 {
1103 u32 l;
1104 u16 w;
1105 int has_mem_bar = device_has_memory_space_bar(d);
1106
1107 l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
1108 printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c NROPrPrP%c LTR%c",
1109 cap_express_dev2_timeout_range(PCI_EXP_DEVCAP2_TIMEOUT_RANGE(l)),
1110 FLAG(l, PCI_EXP_DEVCAP2_TIMEOUT_DIS),
1111 FLAG(l, PCI_EXP_DEVCAP2_NROPRPRP),
1112 FLAG(l, PCI_EXP_DEVCAP2_LTR));
1113 printf("\n\t\t\t 10BitTagComp%c 10BitTagReq%c OBFF %s, ExtFmt%c EETLPPrefix%c",
1114 FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_COMP),
1115 FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_REQ),
1116 cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)),
1117 FLAG(l, PCI_EXP_DEVCAP2_EXTFMT),
1118 FLAG(l, PCI_EXP_DEVCAP2_EE_TLP));
1119
1120 if (PCI_EXP_DEVCAP2_EE_TLP == (l & PCI_EXP_DEVCAP2_EE_TLP))
1121 {
1122 printf(", MaxEETLPPrefixes %d",
1123 PCI_EXP_DEVCAP2_MEE_TLP(l) ? PCI_EXP_DEVCAP2_MEE_TLP(l) : 4);
1124 }
1125
1126 printf("\n\t\t\t EmergencyPowerReduction %s, EmergencyPowerReductionInit%c",
1127 cap_express_devcap2_epr(PCI_EXP_DEVCAP2_EPR(l)),
1128 FLAG(l, PCI_EXP_DEVCAP2_EPR_INIT));
1129 printf("\n\t\t\t FRS%c", FLAG(l, PCI_EXP_DEVCAP2_FRS));
1130
1131 if (type == PCI_EXP_TYPE_ROOT_PORT)
1132 printf(" LN System CLS %s,",
1133 cap_express_devcap2_lncls(PCI_EXP_DEVCAP2_LN_CLS(l)));
1134
1135 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT)
1136 printf(" %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l)));
1137
1138 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1139 printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEVCAP2_ARI));
1140 else
1141 printf("\n");
1142 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1143 type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar)
1144 {
1145 printf("\t\t\t AtomicOpsCap:");
1146 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1147 type == PCI_EXP_TYPE_DOWNSTREAM)
1148 printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING));
1149 if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar)
1150 printf(" 32bit%c 64bit%c 128bitCAS%c",
1151 FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP),
1152 FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP),
1153 FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP));
1154 printf("\n");
1155 }
1156
1157 w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
1158 printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c",
1159 cap_express_dev2_timeout_value(PCI_EXP_DEVCTL2_TIMEOUT_VALUE(w)),
1160 FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS));
1161 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1162 printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEVCTL2_ARI));
1163 else
1164 printf("\n");
1165 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1166 type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT ||
1167 type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1168 {
1169 printf("\t\t\t AtomicOpsCtl:");
1170 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
1171 type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1172 printf(" ReqEn%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN));
1173 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1174 type == PCI_EXP_TYPE_DOWNSTREAM)
1175 printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK));
1176 printf("\n");
1177 }
1178 printf("\t\t\t IDOReq%c IDOCompl%c LTR%c EmergencyPowerReductionReq%c\n",
1179 FLAG(w, PCI_EXP_DEVCTL2_IDO_REQ_EN),
1180 FLAG(w, PCI_EXP_DEVCTL2_IDO_CMP_EN),
1181 FLAG(w, PCI_EXP_DEVCTL2_LTR),
1182 FLAG(w, PCI_EXP_DEVCTL2_EPR_REQ));
1183 printf("\t\t\t 10BitTagReq%c OBFF %s, EETLPPrefixBlk%c\n",
1184 FLAG(w, PCI_EXP_DEVCTL2_10BIT_TAG_REQ),
1185 cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)),
1186 FLAG(w, PCI_EXP_DEVCTL2_EE_TLP_BLK));
1187 }
1188
cap_express_link2_speed_cap(int vector)1189 static const char *cap_express_link2_speed_cap(int vector)
1190 {
1191 /*
1192 * Per PCIe r5.0, sec 8.2.1, a device must support 2.5GT/s and is not
1193 * permitted to skip support for any data rates between 2.5GT/s and the
1194 * highest supported rate.
1195 */
1196 if (vector & 0x40)
1197 return "RsvdP";
1198 if (vector & 0x20)
1199 return "2.5-64GT/s";
1200 if (vector & 0x10)
1201 return "2.5-32GT/s";
1202 if (vector & 0x08)
1203 return "2.5-16GT/s";
1204 if (vector & 0x04)
1205 return "2.5-8GT/s";
1206 if (vector & 0x02)
1207 return "2.5-5GT/s";
1208 if (vector & 0x01)
1209 return "2.5GT/s";
1210
1211 return "Unknown";
1212 }
1213
cap_express_link2_speed(int type)1214 static const char *cap_express_link2_speed(int type)
1215 {
1216 switch (type)
1217 {
1218 case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1219 case 1:
1220 return "2.5GT/s";
1221 case 2:
1222 return "5GT/s";
1223 case 3:
1224 return "8GT/s";
1225 case 4:
1226 return "16GT/s";
1227 case 5:
1228 return "32GT/s";
1229 case 6:
1230 return "64GT/s";
1231 default:
1232 return "Unknown";
1233 }
1234 }
1235
cap_express_link2_deemphasis(int type)1236 static const char *cap_express_link2_deemphasis(int type)
1237 {
1238 switch (type)
1239 {
1240 case 0:
1241 return "-6dB";
1242 case 1:
1243 return "-3.5dB";
1244 default:
1245 return "Unknown";
1246 }
1247 }
1248
cap_express_link2_compliance_preset(int type)1249 static const char *cap_express_link2_compliance_preset(int type)
1250 {
1251 switch (type)
1252 {
1253 case 0:
1254 return "-6dB de-emphasis, 0dB preshoot";
1255 case 1:
1256 return "-3.5dB de-emphasis, 0dB preshoot";
1257 case 2:
1258 return "-4.4dB de-emphasis, 0dB preshoot";
1259 case 3:
1260 return "-2.5dB de-emphasis, 0dB preshoot";
1261 case 4:
1262 return "0dB de-emphasis, 0dB preshoot";
1263 case 5:
1264 return "0dB de-emphasis, 1.9dB preshoot";
1265 case 6:
1266 return "0dB de-emphasis, 2.5dB preshoot";
1267 case 7:
1268 return "-6.0dB de-emphasis, 3.5dB preshoot";
1269 case 8:
1270 return "-3.5dB de-emphasis, 3.5dB preshoot";
1271 case 9:
1272 return "0dB de-emphasis, 3.5dB preshoot";
1273 default:
1274 return "Unknown";
1275 }
1276 }
1277
cap_express_link2_transmargin(int type)1278 static const char *cap_express_link2_transmargin(int type)
1279 {
1280 switch (type)
1281 {
1282 case 0:
1283 return "Normal Operating Range";
1284 case 1:
1285 return "800-1200mV(full-swing)/400-700mV(half-swing)";
1286 case 2:
1287 case 3:
1288 case 4:
1289 case 5:
1290 return "200-400mV(full-swing)/100-200mV(half-swing)";
1291 default:
1292 return "Unknown";
1293 }
1294 }
1295
cap_express_link2_crosslink_res(int crosslink)1296 static const char *cap_express_link2_crosslink_res(int crosslink)
1297 {
1298 switch (crosslink)
1299 {
1300 case 0:
1301 return "unsupported";
1302 case 1:
1303 return "Upstream Port";
1304 case 2:
1305 return "Downstream Port";
1306 default:
1307 return "incomplete";
1308 }
1309 }
1310
cap_express_link2_component(int presence)1311 static const char *cap_express_link2_component(int presence)
1312 {
1313 switch (presence)
1314 {
1315 case 0:
1316 return "Link Down - Not Determined";
1317 case 1:
1318 return "Link Down - Not Present";
1319 case 2:
1320 return "Link Down - Present";
1321 case 4:
1322 return "Link Up - Present";
1323 case 5:
1324 return "Link Up - Present and DRS Received";
1325 default:
1326 return "Reserved";
1327 }
1328 }
1329
cap_express_link2(struct device * d,int where,int type)1330 static void cap_express_link2(struct device *d, int where, int type)
1331 {
1332 u32 l = 0;
1333 u16 w;
1334
1335 if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) &&
1336 (d->dev->dev != 0 || d->dev->func != 0))) {
1337 /* Link Capabilities 2 was reserved before PCIe r3.0 */
1338 l = get_conf_long(d, where + PCI_EXP_LNKCAP2);
1339 if (l) {
1340 printf("\t\tLnkCap2: Supported Link Speeds: %s, Crosslink%c "
1341 "Retimer%c 2Retimers%c DRS%c\n",
1342 cap_express_link2_speed_cap(PCI_EXP_LNKCAP2_SPEED(l)),
1343 FLAG(l, PCI_EXP_LNKCAP2_CROSSLINK),
1344 FLAG(l, PCI_EXP_LNKCAP2_RETIMER),
1345 FLAG(l, PCI_EXP_LNKCAP2_2RETIMERS),
1346 FLAG(l, PCI_EXP_LNKCAP2_DRS));
1347 }
1348
1349 w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
1350 printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
1351 cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
1352 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
1353 FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS));
1354 if (type == PCI_EXP_TYPE_DOWNSTREAM)
1355 printf(", Selectable De-emphasis: %s",
1356 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)));
1357 printf("\n"
1358 "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
1359 "\t\t\t Compliance Preset/De-emphasis: %s\n",
1360 cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
1361 FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
1362 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
1363 cap_express_link2_compliance_preset(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
1364 }
1365
1366 w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
1367 printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c EqualizationPhase1%c\n"
1368 "\t\t\t EqualizationPhase2%c EqualizationPhase3%c LinkEqualizationRequest%c\n"
1369 "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s",
1370 cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)),
1371 FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP),
1372 FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1),
1373 FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2),
1374 FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3),
1375 FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ),
1376 FLAG(w, PCI_EXP_LINKSTA2_RETIMER),
1377 FLAG(w, PCI_EXP_LINKSTA2_2RETIMERS),
1378 cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w)));
1379
1380 if (exp_downstream_port(type) && (l & PCI_EXP_LNKCAP2_DRS)) {
1381 printf(", DRS%c\n"
1382 "\t\t\t DownstreamComp: %s\n",
1383 FLAG(w, PCI_EXP_LINKSTA2_DRS_RCVD),
1384 cap_express_link2_component(PCI_EXP_LINKSTA2_COMPONENT(w)));
1385 } else
1386 printf("\n");
1387 }
1388
cap_express_slot2(struct device * d UNUSED,int where UNUSED)1389 static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
1390 {
1391 /* No capabilities that require this field in PCIe rev2.0 spec. */
1392 }
1393
cap_express_link_rcd(struct device * d)1394 static void cap_express_link_rcd(struct device *d)
1395 {
1396 u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width;
1397 u16 w;
1398 struct pci_dev *pdev = d->dev;
1399
1400 if (!pdev->rcd_link_cap)
1401 return;
1402
1403 t = pdev->rcd_link_cap;
1404 aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
1405 cap_speed = t & PCI_EXP_LNKCAP_SPEED;
1406 cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4;
1407 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
1408 t >> 24,
1409 link_speed(cap_speed), cap_width,
1410 aspm_support(aspm));
1411 if (aspm)
1412 {
1413 printf(", Exit Latency ");
1414 if (aspm & 1)
1415 printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12));
1416 if (aspm & 2)
1417 printf("%sL1 %s", (aspm & 1) ? ", " : "",
1418 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1419 }
1420 printf("\n");
1421 printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
1422 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
1423 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
1424 FLAG(t, PCI_EXP_LNKCAP_DLLA),
1425 FLAG(t, PCI_EXP_LNKCAP_LBNC),
1426 FLAG(t, PCI_EXP_LNKCAP_AOC));
1427
1428 w = pdev->rcd_link_ctrl;
1429 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1430 printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
1431 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
1432 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1433 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
1434 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
1435 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
1436 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
1437 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
1438
1439 w = pdev->rcd_link_status;
1440 sta_speed = w & PCI_EXP_LNKSTA_SPEED;
1441 sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4;
1442 printf("\t\tLnkSta:\tSpeed %s%s, Width x%d%s\n",
1443 link_speed(sta_speed),
1444 link_compare(PCI_EXP_TYPE_ROOT_INT_EP, sta_speed, cap_speed),
1445 sta_width,
1446 link_compare(PCI_EXP_TYPE_ROOT_INT_EP, sta_width, cap_width));
1447 printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
1448 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
1449 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
1450 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
1451 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
1452 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
1453 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
1454 }
1455
1456 static int
cap_express(struct device * d,int where,int cap)1457 cap_express(struct device *d, int where, int cap)
1458 {
1459 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1460 int size;
1461 int slot = 0;
1462 int link = 1;
1463
1464 printf("Express ");
1465 if (verbose >= 2)
1466 printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1467 switch (type)
1468 {
1469 case PCI_EXP_TYPE_ENDPOINT:
1470 printf("Endpoint");
1471 break;
1472 case PCI_EXP_TYPE_LEG_END:
1473 printf("Legacy Endpoint");
1474 break;
1475 case PCI_EXP_TYPE_ROOT_PORT:
1476 slot = cap & PCI_EXP_FLAGS_SLOT;
1477 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1478 break;
1479 case PCI_EXP_TYPE_UPSTREAM:
1480 printf("Upstream Port");
1481 break;
1482 case PCI_EXP_TYPE_DOWNSTREAM:
1483 slot = cap & PCI_EXP_FLAGS_SLOT;
1484 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1485 break;
1486 case PCI_EXP_TYPE_PCI_BRIDGE:
1487 printf("PCI-Express to PCI/PCI-X Bridge");
1488 break;
1489 case PCI_EXP_TYPE_PCIE_BRIDGE:
1490 slot = cap & PCI_EXP_FLAGS_SLOT;
1491 printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)",
1492 FLAG(cap, PCI_EXP_FLAGS_SLOT));
1493 break;
1494 case PCI_EXP_TYPE_ROOT_INT_EP:
1495 link = 0;
1496 printf("Root Complex Integrated Endpoint");
1497 break;
1498 case PCI_EXP_TYPE_ROOT_EC:
1499 link = 0;
1500 printf("Root Complex Event Collector");
1501 break;
1502 default:
1503 printf("Unknown type %d", type);
1504 }
1505 printf(", IntMsgNum %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1506 if (verbose < 2)
1507 return type;
1508
1509 size = 16;
1510 if (slot)
1511 size = 24;
1512 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
1513 size = 32;
1514 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1515 return type;
1516
1517 cap_express_dev(d, where, type);
1518 if (link)
1519 cap_express_link(d, where, type);
1520 else if (d->dev->rcd_link_cap)
1521 cap_express_link_rcd(d);
1522
1523 if (slot)
1524 cap_express_slot(d, where);
1525 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
1526 cap_express_root(d, where);
1527
1528 if ((cap & PCI_EXP_FLAGS_VERS) < 2)
1529 return type;
1530
1531 size = 16;
1532 if (slot)
1533 size = 24;
1534 if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
1535 return type;
1536
1537 cap_express_dev2(d, where, type);
1538 if (link)
1539 cap_express_link2(d, where, type);
1540 if (slot)
1541 cap_express_slot2(d, where);
1542 return type;
1543 }
1544
1545 static void
cap_msix(struct device * d,int where,int cap)1546 cap_msix(struct device *d, int where, int cap)
1547 {
1548 u32 off;
1549
1550 printf("MSI-X: Enable%c Count=%d Masked%c\n",
1551 FLAG(cap, PCI_MSIX_ENABLE),
1552 (cap & PCI_MSIX_TABSIZE) + 1,
1553 FLAG(cap, PCI_MSIX_MASK));
1554 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1555 return;
1556
1557 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1558 printf("\t\tVector table: BAR=%d offset=%08x\n",
1559 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1560 off = get_conf_long(d, where + PCI_MSIX_PBA);
1561 printf("\t\tPBA: BAR=%d offset=%08x\n",
1562 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1563 }
1564
1565 static void
cap_slotid(int cap)1566 cap_slotid(int cap)
1567 {
1568 int esr = cap & 0xff;
1569 int chs = cap >> 8;
1570
1571 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1572 esr & PCI_SID_ESR_NSLOTS,
1573 FLAG(esr, PCI_SID_ESR_FIC),
1574 chs);
1575 }
1576
1577 static void
cap_ssvid(struct device * d,int where)1578 cap_ssvid(struct device *d, int where)
1579 {
1580 u16 subsys_v, subsys_d;
1581 char ssnamebuf[256];
1582
1583 if (!config_fetch(d, where, 8))
1584 return;
1585 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1586 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1587 printf("Subsystem: %s\n",
1588 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1589 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1590 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1591 }
1592
1593 static void
cap_debug_port(int cap)1594 cap_debug_port(int cap)
1595 {
1596 int bar = cap >> 13;
1597 int pos = cap & 0x1fff;
1598 printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1599 }
1600
1601 static void
cap_af(struct device * d,int where)1602 cap_af(struct device *d, int where)
1603 {
1604 u8 reg;
1605
1606 printf("PCI Advanced Features\n");
1607 if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3))
1608 return;
1609
1610 reg = get_conf_byte(d, where + PCI_AF_CAP);
1611 printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP),
1612 FLAG(reg, PCI_AF_CAP_FLR));
1613 reg = get_conf_byte(d, where + PCI_AF_CTRL);
1614 printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR));
1615 reg = get_conf_byte(d, where + PCI_AF_STATUS);
1616 printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP));
1617 }
1618
1619 static void
cap_sata_hba(struct device * d,int where,int cap)1620 cap_sata_hba(struct device *d, int where, int cap)
1621 {
1622 u32 bars;
1623 int bar;
1624
1625 printf("SATA HBA v%d.%d", BITS(cap, 4, 4), BITS(cap, 0, 4));
1626 if (verbose < 2 || !config_fetch(d, where + PCI_SATA_HBA_BARS, 4))
1627 {
1628 printf("\n");
1629 return;
1630 }
1631
1632 bars = get_conf_long(d, where + PCI_SATA_HBA_BARS);
1633 bar = BITS(bars, 0, 4);
1634 if (bar >= 4 && bar <= 9)
1635 printf(" BAR%d Offset=%08x\n", bar - 4, BITS(bars, 4, 20));
1636 else if (bar == 15)
1637 printf(" InCfgSpace\n");
1638 else
1639 printf(" BAR??%d\n", bar);
1640 }
1641
cap_ea_property(int p,int is_secondary)1642 static const char *cap_ea_property(int p, int is_secondary)
1643 {
1644 switch (p) {
1645 case 0x00:
1646 return "memory space, non-prefetchable";
1647 case 0x01:
1648 return "memory space, prefetchable";
1649 case 0x02:
1650 return "I/O space";
1651 case 0x03:
1652 return "VF memory space, prefetchable";
1653 case 0x04:
1654 return "VF memory space, non-prefetchable";
1655 case 0x05:
1656 return "allocation behind bridge, non-prefetchable memory";
1657 case 0x06:
1658 return "allocation behind bridge, prefetchable memory";
1659 case 0x07:
1660 return "allocation behind bridge, I/O space";
1661 case 0xfd:
1662 return "memory space resource unavailable for use";
1663 case 0xfe:
1664 return "I/O space resource unavailable for use";
1665 case 0xff:
1666 if (is_secondary)
1667 return "entry unavailable for use, PrimaryProperties should be used";
1668 else
1669 return "entry unavailable for use";
1670 default:
1671 return NULL;
1672 }
1673 }
1674
cap_ea(struct device * d,int where,int cap)1675 static void cap_ea(struct device *d, int where, int cap)
1676 {
1677 int entry;
1678 int entry_base = where + 4;
1679 int num_entries = BITS(cap, 0, 6);
1680 u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1681
1682 printf("Enhanced Allocation (EA): NumEntries=%u", num_entries);
1683 if (htype == PCI_HEADER_TYPE_BRIDGE) {
1684 byte fixed_sub, fixed_sec;
1685
1686 entry_base += 4;
1687 if (!config_fetch(d, where + 4, 2)) {
1688 printf("\n");
1689 return;
1690 }
1691 fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY);
1692 fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE);
1693 printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub);
1694 }
1695 printf("\n");
1696 if (verbose < 2)
1697 return;
1698
1699 for (entry = 0; entry < num_entries; entry++) {
1700 int max_offset_high_pos, has_base_high, has_max_offset_high;
1701 u32 entry_header;
1702 u32 base, max_offset;
1703 int es, bei, pp, sp;
1704 const char *prop_text;
1705
1706 if (!config_fetch(d, entry_base, 4))
1707 return;
1708 entry_header = get_conf_long(d, entry_base);
1709 es = BITS(entry_header, 0, 3);
1710 bei = BITS(entry_header, 4, 4);
1711 pp = BITS(entry_header, 8, 8);
1712 sp = BITS(entry_header, 16, 8);
1713 if (!config_fetch(d, entry_base + 4, es * 4))
1714 return;
1715 printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry,
1716 FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE),
1717 FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es);
1718 printf("\t\t\t BAR Equivalent Indicator: ");
1719 switch (bei) {
1720 case 0:
1721 case 1:
1722 case 2:
1723 case 3:
1724 case 4:
1725 case 5:
1726 printf("BAR %u", bei);
1727 break;
1728 case 6:
1729 printf("resource behind function");
1730 break;
1731 case 7:
1732 printf("not indicated");
1733 break;
1734 case 8:
1735 printf("expansion ROM");
1736 break;
1737 case 9:
1738 case 10:
1739 case 11:
1740 case 12:
1741 case 13:
1742 case 14:
1743 printf("VF-BAR %u", bei - 9);
1744 break;
1745 default:
1746 printf("reserved");
1747 break;
1748 }
1749 printf("\n");
1750
1751 prop_text = cap_ea_property(pp, 0);
1752 printf("\t\t\t PrimaryProperties: ");
1753 if (prop_text)
1754 printf("%s\n", prop_text);
1755 else
1756 printf("[%02x]\n", pp);
1757
1758 prop_text = cap_ea_property(sp, 1);
1759 printf("\t\t\t SecondaryProperties: ");
1760 if (prop_text)
1761 printf("%s\n", prop_text);
1762 else
1763 printf("[%02x]\n", sp);
1764
1765 base = get_conf_long(d, entry_base + 4);
1766 has_base_high = ((base & 2) != 0);
1767 base &= ~3;
1768
1769 max_offset = get_conf_long(d, entry_base + 8);
1770 has_max_offset_high = ((max_offset & 2) != 0);
1771 max_offset |= 3;
1772 max_offset_high_pos = entry_base + 12;
1773
1774 printf("\t\t\t Base: ");
1775 if (has_base_high) {
1776 u32 base_high = get_conf_long(d, entry_base + 12);
1777
1778 printf("%x", base_high);
1779 max_offset_high_pos += 4;
1780 }
1781 printf("%08x\n", base);
1782
1783 printf("\t\t\t MaxOffset: ");
1784 if (has_max_offset_high) {
1785 u32 max_offset_high = get_conf_long(d, max_offset_high_pos);
1786
1787 printf("%x", max_offset_high);
1788 }
1789 printf("%08x\n", max_offset);
1790
1791 entry_base += 4 + 4 * es;
1792 }
1793 }
1794
1795 void
show_caps(struct device * d,int where)1796 show_caps(struct device *d, int where)
1797 {
1798 int can_have_ext_caps = 0;
1799 int type = -1;
1800
1801 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1802 {
1803 byte been_there[256];
1804 where = get_conf_byte(d, where) & ~3;
1805 memset(been_there, 0, 256);
1806 while (where)
1807 {
1808 int id, next, cap;
1809 printf("\tCapabilities: ");
1810 if (!config_fetch(d, where, 4))
1811 {
1812 puts("<access denied>");
1813 break;
1814 }
1815 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1816 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1817 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1818 printf("[%02x] ", where);
1819 if (been_there[where]++)
1820 {
1821 printf("<chain looped>\n");
1822 break;
1823 }
1824 if (id == 0xff)
1825 {
1826 printf("<chain broken>\n");
1827 break;
1828 }
1829 switch (id)
1830 {
1831 case PCI_CAP_ID_NULL:
1832 printf("Null\n");
1833 break;
1834 case PCI_CAP_ID_PM:
1835 cap_pm(d, where, cap);
1836 break;
1837 case PCI_CAP_ID_AGP:
1838 cap_agp(d, where, cap);
1839 break;
1840 case PCI_CAP_ID_VPD:
1841 cap_vpd(d);
1842 break;
1843 case PCI_CAP_ID_SLOTID:
1844 cap_slotid(cap);
1845 break;
1846 case PCI_CAP_ID_MSI:
1847 cap_msi(d, where, cap);
1848 break;
1849 case PCI_CAP_ID_CHSWP:
1850 printf("CompactPCI hot-swap <?>\n");
1851 break;
1852 case PCI_CAP_ID_PCIX:
1853 cap_pcix(d, where);
1854 can_have_ext_caps = 1;
1855 break;
1856 case PCI_CAP_ID_HT:
1857 cap_ht(d, where, cap);
1858 break;
1859 case PCI_CAP_ID_VNDR:
1860 show_vendor_caps(d, where, cap);
1861 break;
1862 case PCI_CAP_ID_DBG:
1863 cap_debug_port(cap);
1864 break;
1865 case PCI_CAP_ID_CCRC:
1866 printf("CompactPCI central resource control <?>\n");
1867 break;
1868 case PCI_CAP_ID_HOTPLUG:
1869 printf("Hot-plug capable\n");
1870 break;
1871 case PCI_CAP_ID_SSVID:
1872 cap_ssvid(d, where);
1873 break;
1874 case PCI_CAP_ID_AGP3:
1875 printf("AGP3 <?>\n");
1876 break;
1877 case PCI_CAP_ID_SECURE:
1878 printf("Secure device <?>\n");
1879 break;
1880 case PCI_CAP_ID_EXP:
1881 type = cap_express(d, where, cap);
1882 can_have_ext_caps = 1;
1883 break;
1884 case PCI_CAP_ID_MSIX:
1885 cap_msix(d, where, cap);
1886 break;
1887 case PCI_CAP_ID_SATA:
1888 cap_sata_hba(d, where, cap);
1889 break;
1890 case PCI_CAP_ID_AF:
1891 cap_af(d, where);
1892 break;
1893 case PCI_CAP_ID_EA:
1894 cap_ea(d, where, cap);
1895 break;
1896 default:
1897 printf("Capability ID %#02x [%04x]\n", id, cap);
1898 }
1899 where = next;
1900 }
1901 }
1902 if (can_have_ext_caps)
1903 show_ext_caps(d, type);
1904 }
1905