1.. _module-pw_cpu_exception_risc_v: 2 3======================= 4pw_cpu_exception_risc_v 5======================= 6This module lays the foundation for implementing a backend cpu exception 7for the RISCV architectures: 8 9For now, this contains the cpu state, protos, and tools needed for parsing 10and the snapshot. The entry for exception handling will still need to be 11implemented by the user. 12 13Python processor 14================ 15This module's included Python exception analyzer tooling provides snapshot 16integration via a ``process_snapshot()`` function that produces a multi-line 17dump from a serialized snapshot proto, for example: 18 19.. code-block:: 20 21 All registers: 22 mepc 0x20047144 example::Serivice::Crash(_example_service_CrashRequest const&, _pw_protobuf_Empty&) (src/example_service/service.cc:131) 23 mcause 0x00000003 24 mstatus 0x80007800 25 mtval 0x00000000 26 ra 0x2001e92c pw_log_tokenized_HandleLog (src/system/log.cc:124) 27 sp 0x00095660 28 t0 0x20047120 29 t1 0xfffffff0 30 t2 0x00000800 31 fp 0x00095760 32 s1 0x000956dc 33 a0 0x00000004 34 a1 0x000956dc 35 a2 0x00000000 36 a3 0x00000004 37 a4 0x00000007 38 a5 0x000814b0 39 a6 0x000955e6 40 a7 0x00000000 41 s2 0x00000004 42 s3 0x20059114 43 s4 0x00000000 44 s5 0x000aae98 45 s6 0x00084a8f 46 s7 0xb7002653 47 s8 0xd20200f3 48 s9 0x00000002 49 s10 0xa5a5a5a5 50 s11 0xa5a5a5a5 51 t3 0xfffffffd 52 t4 0x00000000 53 t5 0xa5a5a5a5 54 t6 0xa5a5a5a5 55 56Module Configuration Options 57============================ 58The following configurations can be adjusted via compile-time configuration of 59this module, see the 60:ref:`module documentation <module-structure-compile-time-configuration>` for 61more details. 62 63.. c:macro:: PW_CPU_EXCEPTION_RISCV_LOG_LEVEL 64 65 The log level to use for this module. Logs below this level are omitted. 66 67 This defaults to ``PW_LOG_LEVEL_DEBUG``. 68