1 /*
2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch.h>
12 #include <arch_features.h>
13 #include <arch_helpers.h>
14 #include <bl1/bl1.h>
15 #include <common/bl_common.h>
16 #include <common/build_message.h>
17 #include <common/debug.h>
18 #include <drivers/auth/auth_mod.h>
19 #include <drivers/auth/crypto_mod.h>
20 #include <drivers/console.h>
21 #include <lib/bootmarker_capture.h>
22 #include <lib/cpus/errata.h>
23 #include <lib/pmf/pmf.h>
24 #include <lib/utils.h>
25 #include <plat/common/platform.h>
26 #include <smccc_helpers.h>
27 #include <tools_share/uuid.h>
28
29 #include "bl1_private.h"
30
31 static void bl1_load_bl2(void);
32
33 #if ENABLE_PAUTH
34 uint64_t bl1_apiakey[2];
35 #endif
36
37 #if ENABLE_RUNTIME_INSTRUMENTATION
PMF_REGISTER_SERVICE(bl_svc,PMF_RT_INSTR_SVC_ID,BL_TOTAL_IDS,PMF_DUMP_ENABLE)38 PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID,
39 BL_TOTAL_IDS, PMF_DUMP_ENABLE)
40 #endif
41
42 /*******************************************************************************
43 * Setup function for BL1.
44 ******************************************************************************/
45 void bl1_setup(void)
46 {
47 /* Enable early console if EARLY_CONSOLE flag is enabled */
48 plat_setup_early_console();
49
50 /* Perform early platform-specific setup */
51 bl1_early_platform_setup();
52
53 /* Perform late platform-specific setup */
54 bl1_plat_arch_setup();
55
56 #if CTX_INCLUDE_PAUTH_REGS
57 /*
58 * Assert that the ARMv8.3-PAuth registers are present or an access
59 * fault will be triggered when they are being saved or restored.
60 */
61 assert(is_armv8_3_pauth_present());
62 #endif /* CTX_INCLUDE_PAUTH_REGS */
63 }
64
65 /*******************************************************************************
66 * Function to perform late architectural and platform specific initialization.
67 * It also queries the platform to load and run next BL image. Only called
68 * by the primary cpu after a cold boot.
69 ******************************************************************************/
bl1_main(void)70 void bl1_main(void)
71 {
72 unsigned int image_id;
73
74 #if ENABLE_RUNTIME_INSTRUMENTATION
75 PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_ENTRY, PMF_CACHE_MAINT);
76 #endif
77
78 /* Announce our arrival */
79 NOTICE(FIRMWARE_WELCOME_STR);
80 NOTICE("BL1: %s\n", build_version_string);
81 NOTICE("BL1: %s\n", build_message);
82
83 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT);
84
85 print_errata_status();
86
87 #if ENABLE_ASSERTIONS
88 u_register_t val;
89 /*
90 * Ensure that MMU/Caches and coherency are turned on
91 */
92 #ifdef __aarch64__
93 val = read_sctlr_el3();
94 #else
95 val = read_sctlr();
96 #endif
97 assert((val & SCTLR_M_BIT) != 0);
98 assert((val & SCTLR_C_BIT) != 0);
99 assert((val & SCTLR_I_BIT) != 0);
100 /*
101 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
102 * provided platform value
103 */
104 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
105 /*
106 * If CWG is zero, then no CWG information is available but we can
107 * at least check the platform value is less than the architectural
108 * maximum.
109 */
110 if (val != 0)
111 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
112 else
113 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
114 #endif /* ENABLE_ASSERTIONS */
115
116 /* Perform remaining generic architectural setup from EL3 */
117 bl1_arch_setup();
118
119 crypto_mod_init();
120
121 /* Initialize authentication module */
122 auth_mod_init();
123
124 /* Initialize the measured boot */
125 bl1_plat_mboot_init();
126
127 /* Perform platform setup in BL1. */
128 bl1_platform_setup();
129
130 #if ENABLE_PAUTH
131 /* Store APIAKey_EL1 key */
132 bl1_apiakey[0] = read_apiakeylo_el1();
133 bl1_apiakey[1] = read_apiakeyhi_el1();
134 #endif /* ENABLE_PAUTH */
135
136 /* Get the image id of next image to load and run. */
137 image_id = bl1_plat_get_next_image_id();
138
139 /*
140 * We currently interpret any image id other than
141 * BL2_IMAGE_ID as the start of firmware update.
142 */
143 if (image_id == BL2_IMAGE_ID)
144 bl1_load_bl2();
145 else
146 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
147
148 /* Teardown the measured boot driver */
149 bl1_plat_mboot_finish();
150
151 bl1_prepare_next_image(image_id);
152
153 #if ENABLE_RUNTIME_INSTRUMENTATION
154 PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_EXIT, PMF_CACHE_MAINT);
155 #endif
156
157 console_flush();
158 }
159
160 /*******************************************************************************
161 * This function locates and loads the BL2 raw binary image in the trusted SRAM.
162 * Called by the primary cpu after a cold boot.
163 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
164 * loader etc.
165 ******************************************************************************/
bl1_load_bl2(void)166 static void bl1_load_bl2(void)
167 {
168 image_desc_t *desc;
169 image_info_t *info;
170 int err;
171
172 /* Get the image descriptor */
173 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
174 assert(desc != NULL);
175
176 /* Get the image info */
177 info = &desc->image_info;
178 INFO("BL1: Loading BL2\n");
179
180 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID);
181 if (err != 0) {
182 ERROR("Failure in pre image load handling of BL2 (%d)\n", err);
183 plat_error_handler(err);
184 }
185
186 err = load_auth_image(BL2_IMAGE_ID, info);
187 if (err != 0) {
188 ERROR("Failed to load BL2 firmware.\n");
189 plat_error_handler(err);
190 }
191
192 /* Allow platform to handle image information. */
193 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID);
194 if (err != 0) {
195 ERROR("Failure in post image load handling of BL2 (%d)\n", err);
196 plat_error_handler(err);
197 }
198
199 NOTICE("BL1: Booting BL2\n");
200 }
201
202 /*******************************************************************************
203 * Function called just before handing over to the next BL to inform the user
204 * about the boot progress. In debug mode, also print details about the BL
205 * image's execution context.
206 ******************************************************************************/
bl1_print_next_bl_ep_info(const entry_point_info_t * bl_ep_info)207 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
208 {
209 #ifdef __aarch64__
210 NOTICE("BL1: Booting BL31\n");
211 #else
212 NOTICE("BL1: Booting BL32\n");
213 #endif /* __aarch64__ */
214 print_entry_point_info(bl_ep_info);
215 }
216
217 #if SPIN_ON_BL1_EXIT
print_debug_loop_message(void)218 void print_debug_loop_message(void)
219 {
220 NOTICE("BL1: Debug loop, spinning forever\n");
221 NOTICE("BL1: Please connect the debugger to continue\n");
222 }
223 #endif
224
225 /*******************************************************************************
226 * Top level handler for servicing BL1 SMCs.
227 ******************************************************************************/
bl1_smc_handler(unsigned int smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * cookie,void * handle,unsigned int flags)228 u_register_t bl1_smc_handler(unsigned int smc_fid,
229 u_register_t x1,
230 u_register_t x2,
231 u_register_t x3,
232 u_register_t x4,
233 void *cookie,
234 void *handle,
235 unsigned int flags)
236 {
237 /* BL1 Service UUID */
238 DEFINE_SVC_UUID2(bl1_svc_uid,
239 U(0xd46739fd), 0xcb72, 0x9a4d, 0xb5, 0x75,
240 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
241
242
243 #if TRUSTED_BOARD_BOOT
244 /*
245 * Dispatch FWU calls to FWU SMC handler and return its return
246 * value
247 */
248 if (is_fwu_fid(smc_fid)) {
249 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
250 handle, flags);
251 }
252 #endif
253
254 switch (smc_fid) {
255 case BL1_SMC_CALL_COUNT:
256 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
257
258 case BL1_SMC_UID:
259 SMC_UUID_RET(handle, bl1_svc_uid);
260
261 case BL1_SMC_VERSION:
262 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
263
264 default:
265 WARN("Unimplemented BL1 SMC Call: 0x%x\n", smc_fid);
266 SMC_RET1(handle, SMC_UNK);
267 }
268 }
269
270 /*******************************************************************************
271 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI
272 * compliance when invoking bl1_smc_handler.
273 ******************************************************************************/
bl1_smc_wrapper(uint32_t smc_fid,void * cookie,void * handle,unsigned int flags)274 u_register_t bl1_smc_wrapper(uint32_t smc_fid,
275 void *cookie,
276 void *handle,
277 unsigned int flags)
278 {
279 u_register_t x1, x2, x3, x4;
280
281 assert(handle != NULL);
282
283 get_smc_params_from_ctx(handle, x1, x2, x3, x4);
284 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
285 }
286