1 /*
2 * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_features.h>
8 #include <common/debug.h>
9 #include <common/feat_detect.h>
10
11 static bool tainted;
12
13 /*******************************************************************************
14 * This section lists the wrapper modules for each feature to evaluate the
15 * feature states (FEAT_STATE_ALWAYS and FEAT_STATE_CHECK) and perform
16 * necessary action as below:
17 *
18 * It verifies whether the FEAT_XXX (eg: FEAT_SB) is supported by the PE or not.
19 * Without this check an exception would occur during context save/restore
20 * routines, if the feature is enabled but not supported by PE.
21 ******************************************************************************/
22
23 #define feat_detect_panic(a, b) ((a) ? (void)0 : feature_panic(b))
24
25 /*******************************************************************************
26 * Function : feature_panic
27 * Customised panic function with error logging mechanism to list the feature
28 * not supported by the PE.
29 ******************************************************************************/
feature_panic(char * feat_name)30 static inline void feature_panic(char *feat_name)
31 {
32 ERROR("FEAT_%s not supported by the PE\n", feat_name);
33 panic();
34 }
35
36 /*******************************************************************************
37 * Function : check_feature
38 * Check for a valid combination of build time flags (ENABLE_FEAT_xxx) and
39 * feature availability on the hardware. <min> is the smallest feature
40 * ID field value that is required for that feature.
41 * Triggers a panic later if a feature is forcefully enabled, but not
42 * available on the PE. Also will panic if the hardware feature ID field
43 * is larger than the maximum known and supported number, specified by <max>.
44 *
45 * We force inlining here to let the compiler optimise away the whole check
46 * if the feature is disabled at build time (FEAT_STATE_DISABLED).
47 ******************************************************************************/
48 static inline void __attribute((__always_inline__))
check_feature(int state,unsigned long field,const char * feat_name,unsigned int min,unsigned int max)49 check_feature(int state, unsigned long field, const char *feat_name,
50 unsigned int min, unsigned int max)
51 {
52 if (state == FEAT_STATE_ALWAYS && field < min) {
53 ERROR("FEAT_%s not supported by the PE\n", feat_name);
54 tainted = true;
55 }
56 if (state >= FEAT_STATE_ALWAYS && field > max) {
57 ERROR("FEAT_%s is version %ld, but is only known up to version %d\n",
58 feat_name, field, max);
59 tainted = true;
60 }
61 }
62
63 /************************************************
64 * Feature : FEAT_PAUTH (Pointer Authentication)
65 ***********************************************/
read_feat_pauth(void)66 static void read_feat_pauth(void)
67 {
68 #if (ENABLE_PAUTH == FEAT_STATE_ALWAYS) || (CTX_INCLUDE_PAUTH_REGS == FEAT_STATE_ALWAYS)
69 feat_detect_panic(is_armv8_3_pauth_present(), "PAUTH");
70 #endif
71 }
72
read_feat_rng_trap_id_field(void)73 static unsigned int read_feat_rng_trap_id_field(void)
74 {
75 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT,
76 ID_AA64PFR1_EL1_RNDR_TRAP_MASK);
77 }
78
read_feat_bti_id_field(void)79 static unsigned int read_feat_bti_id_field(void)
80 {
81 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_BT_SHIFT,
82 ID_AA64PFR1_EL1_BT_MASK);
83 }
84
read_feat_sb_id_field(void)85 static unsigned int read_feat_sb_id_field(void)
86 {
87 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT,
88 ID_AA64ISAR1_SB_MASK);
89 }
90
read_feat_csv2_id_field(void)91 static unsigned int read_feat_csv2_id_field(void)
92 {
93 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2_SHIFT,
94 ID_AA64PFR0_CSV2_MASK);
95 }
96
read_feat_pmuv3_id_field(void)97 static unsigned int read_feat_pmuv3_id_field(void)
98 {
99 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT,
100 ID_AA64DFR0_PMUVER_MASK);
101 }
102
read_feat_vhe_id_field(void)103 static unsigned int read_feat_vhe_id_field(void)
104 {
105 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE_SHIFT,
106 ID_AA64MMFR1_EL1_VHE_MASK);
107 }
108
read_feat_sve_id_field(void)109 static unsigned int read_feat_sve_id_field(void)
110 {
111 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE_SHIFT,
112 ID_AA64PFR0_SVE_MASK);
113 }
114
read_feat_ras_id_field(void)115 static unsigned int read_feat_ras_id_field(void)
116 {
117 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS_SHIFT,
118 ID_AA64PFR0_RAS_MASK);
119 }
120
read_feat_dit_id_field(void)121 static unsigned int read_feat_dit_id_field(void)
122 {
123 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT_SHIFT,
124 ID_AA64PFR0_DIT_MASK);
125 }
126
read_feat_amu_id_field(void)127 static unsigned int read_feat_amu_id_field(void)
128 {
129 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU_SHIFT,
130 ID_AA64PFR0_AMU_MASK);
131 }
132
read_feat_mpam_version(void)133 static unsigned int read_feat_mpam_version(void)
134 {
135 return (unsigned int)((((read_id_aa64pfr0_el1() >>
136 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
137 ((read_id_aa64pfr1_el1() >>
138 ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
139 }
140
read_feat_nv_id_field(void)141 static unsigned int read_feat_nv_id_field(void)
142 {
143 return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV_SHIFT,
144 ID_AA64MMFR2_EL1_NV_MASK);
145 }
146
read_feat_sel2_id_field(void)147 static unsigned int read_feat_sel2_id_field(void)
148 {
149 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2_SHIFT,
150 ID_AA64PFR0_SEL2_MASK);
151 }
152
read_feat_trf_id_field(void)153 static unsigned int read_feat_trf_id_field(void)
154 {
155 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT_SHIFT,
156 ID_AA64DFR0_TRACEFILT_MASK);
157 }
get_armv8_5_mte_support(void)158 static unsigned int get_armv8_5_mte_support(void)
159 {
160 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_MTE_SHIFT,
161 ID_AA64PFR1_EL1_MTE_MASK);
162 }
read_feat_rng_id_field(void)163 static unsigned int read_feat_rng_id_field(void)
164 {
165 return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR_SHIFT,
166 ID_AA64ISAR0_RNDR_MASK);
167 }
read_feat_fgt_id_field(void)168 static unsigned int read_feat_fgt_id_field(void)
169 {
170 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT_SHIFT,
171 ID_AA64MMFR0_EL1_FGT_MASK);
172 }
read_feat_ecv_id_field(void)173 static unsigned int read_feat_ecv_id_field(void)
174 {
175 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV_SHIFT,
176 ID_AA64MMFR0_EL1_ECV_MASK);
177 }
read_feat_twed_id_field(void)178 static unsigned int read_feat_twed_id_field(void)
179 {
180 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED_SHIFT,
181 ID_AA64MMFR1_EL1_TWED_MASK);
182 }
183
read_feat_hcx_id_field(void)184 static unsigned int read_feat_hcx_id_field(void)
185 {
186 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX_SHIFT,
187 ID_AA64MMFR1_EL1_HCX_MASK);
188 }
read_feat_tcr2_id_field(void)189 static unsigned int read_feat_tcr2_id_field(void)
190 {
191 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX_SHIFT,
192 ID_AA64MMFR3_EL1_TCRX_MASK);
193 }
read_feat_s2pie_id_field(void)194 static unsigned int read_feat_s2pie_id_field(void)
195 {
196 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE_SHIFT,
197 ID_AA64MMFR3_EL1_S2PIE_MASK);
198 }
read_feat_s1pie_id_field(void)199 static unsigned int read_feat_s1pie_id_field(void)
200 {
201 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE_SHIFT,
202 ID_AA64MMFR3_EL1_S1PIE_MASK);
203 }
read_feat_s2poe_id_field(void)204 static unsigned int read_feat_s2poe_id_field(void)
205 {
206 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE_SHIFT,
207 ID_AA64MMFR3_EL1_S2POE_MASK);
208 }
read_feat_s1poe_id_field(void)209 static unsigned int read_feat_s1poe_id_field(void)
210 {
211 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE_SHIFT,
212 ID_AA64MMFR3_EL1_S1POE_MASK);
213 }
read_feat_brbe_id_field(void)214 static unsigned int read_feat_brbe_id_field(void)
215 {
216 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE_SHIFT,
217 ID_AA64DFR0_BRBE_MASK);
218 }
read_feat_trbe_id_field(void)219 static unsigned int read_feat_trbe_id_field(void)
220 {
221 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER_SHIFT,
222 ID_AA64DFR0_TRACEBUFFER_MASK);
223 }
read_feat_sme_id_field(void)224 static unsigned int read_feat_sme_id_field(void)
225 {
226 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME_SHIFT,
227 ID_AA64PFR1_EL1_SME_MASK);
228 }
read_feat_gcs_id_field(void)229 static unsigned int read_feat_gcs_id_field(void)
230 {
231 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS_SHIFT,
232 ID_AA64PFR1_EL1_GCS_MASK);
233 }
234
read_feat_rme_id_field(void)235 static unsigned int read_feat_rme_id_field(void)
236 {
237 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_FEAT_RME_SHIFT,
238 ID_AA64PFR0_FEAT_RME_MASK);
239 }
240
read_feat_pan_id_field(void)241 static unsigned int read_feat_pan_id_field(void)
242 {
243 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN_SHIFT,
244 ID_AA64MMFR1_EL1_PAN_MASK);
245 }
246
read_feat_mtpmu_id_field(void)247 static unsigned int read_feat_mtpmu_id_field(void)
248 {
249 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT,
250 ID_AA64DFR0_MTPMU_MASK);
251
252 }
253
254 /***********************************************************************************
255 * TF-A supports many Arm architectural features starting from arch version
256 * (8.0 till 8.7+). These features are mostly enabled through build flags. This
257 * mechanism helps in validating these build flags in the early boot phase
258 * either in BL1 or BL31 depending on the platform and assists in identifying
259 * and notifying the features which are enabled but not supported by the PE.
260 *
261 * It reads all the enabled features ID-registers and ensures the features
262 * are supported by the PE.
263 * In case if they aren't it stops booting at an early phase and logs the error
264 * messages, notifying the platforms about the features that are not supported.
265 *
266 * Further the procedure is implemented with a tri-state approach for each feature:
267 * ENABLE_FEAT_xxx = 0 : The feature is disabled statically at compile time
268 * ENABLE_FEAT_xxx = 1 : The feature is enabled and must be present in hardware.
269 * There will be panic if feature is not present at cold boot.
270 * ENABLE_FEAT_xxx = 2 : The feature is enabled but dynamically enabled at runtime
271 * depending on hardware capability.
272 *
273 * For better readability, state values are defined with macros, namely:
274 * { FEAT_STATE_DISABLED, FEAT_STATE_ALWAYS, FEAT_STATE_CHECK }, taking values
275 * { 0, 1, 2 }, respectively, as their naming.
276 **********************************************************************************/
detect_arch_features(void)277 void detect_arch_features(void)
278 {
279 tainted = false;
280
281 /* v8.0 features */
282 check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), "SB", 1, 1);
283 check_feature(ENABLE_FEAT_CSV2_2, read_feat_csv2_id_field(),
284 "CSV2_2", 2, 3);
285 /*
286 * Even though the PMUv3 is an OPTIONAL feature, it is always
287 * implemented and Arm prescribes so. So assume it will be there and do
288 * away with a flag for it. This is used to check minor PMUv3px
289 * revisions so that we catch them as they come along
290 */
291 check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(),
292 "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P7);
293
294 /* v8.1 features */
295 check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), "PAN", 1, 3);
296 check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(), "VHE", 1, 1);
297
298 /* v8.2 features */
299 check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(),
300 "SVE", 1, 1);
301 check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(), "RAS", 1, 2);
302
303 /* v8.3 features */
304 /* TODO: Pauth yet to convert to tri-state feat detect logic */
305 read_feat_pauth();
306
307 /* v8.4 features */
308 check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(), "DIT", 1, 1);
309 check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(),
310 "AMUv1", 1, 2);
311 check_feature(ENABLE_FEAT_MPAM, read_feat_mpam_version(),
312 "MPAM", 1, 17);
313 check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(),
314 "NV2", 2, 2);
315 check_feature(ENABLE_FEAT_SEL2, read_feat_sel2_id_field(),
316 "SEL2", 1, 1);
317 check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(),
318 "TRF", 1, 1);
319
320 /* v8.5 features */
321 check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(), "MTE2",
322 MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY);
323 check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(), "RNG", 1, 1);
324 check_feature(ENABLE_BTI, read_feat_bti_id_field(), "BTI", 1, 1);
325 check_feature(ENABLE_FEAT_RNG_TRAP, read_feat_rng_trap_id_field(),
326 "RNG_TRAP", 1, 1);
327
328 /* v8.6 features */
329 check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(),
330 "AMUv1p1", 2, 2);
331 check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), "FGT", 1, 1);
332 check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(), "ECV", 1, 2);
333 check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(),
334 "TWED", 1, 1);
335
336 /*
337 * even though this is a "DISABLE" it does confusingly perform feature
338 * enablement duties like all other flags here. Check it against the HW
339 * feature when we intend to diverge from the default behaviour
340 */
341 check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(), "MTPMU", 1, 1);
342
343 /* v8.7 features */
344 check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX", 1, 1);
345
346 /* v8.9 features */
347 check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(),
348 "TCR2", 1, 1);
349 check_feature(ENABLE_FEAT_S2PIE, read_feat_s2pie_id_field(),
350 "S2PIE", 1, 1);
351 check_feature(ENABLE_FEAT_S1PIE, read_feat_s1pie_id_field(),
352 "S1PIE", 1, 1);
353 check_feature(ENABLE_FEAT_S2POE, read_feat_s2poe_id_field(),
354 "S2POE", 1, 1);
355 check_feature(ENABLE_FEAT_S1POE, read_feat_s1poe_id_field(),
356 "S1POE", 1, 1);
357 check_feature(ENABLE_FEAT_CSV2_3, read_feat_csv2_id_field(),
358 "CSV2_3", 3, 3);
359
360 /* v9.0 features */
361 check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(),
362 "BRBE", 1, 2);
363 check_feature(ENABLE_TRBE_FOR_NS, read_feat_trbe_id_field(),
364 "TRBE", 1, 1);
365
366 /* v9.2 features */
367 check_feature(ENABLE_SME_FOR_NS, read_feat_sme_id_field(),
368 "SME", 1, 2);
369 check_feature(ENABLE_SME2_FOR_NS, read_feat_sme_id_field(),
370 "SME2", 2, 2);
371
372 /* v9.4 features */
373 check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1);
374 check_feature(ENABLE_RME, read_feat_rme_id_field(), "RME", 1, 1);
375
376 if (tainted) {
377 panic();
378 }
379 }
380