1Running on the AEMv8 Base FVP 2============================= 3 4AArch64 with reset to BL1 entrypoint 5^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 6 7The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 8with 8 CPUs using the AArch64 build of TF-A. 9 10.. code:: shell 11 12 <path-to>/FVP_Base_RevC-2xAEMv8A \ 13 -C pctl.startup=0.0.0.0 \ 14 -C bp.secure_memory=1 \ 15 -C bp.tzc_400.diagnostics=1 \ 16 -C cluster0.NUM_CORES=4 \ 17 -C cluster1.NUM_CORES=4 \ 18 -C cache_state_modelled=1 \ 19 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 20 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 21 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 22 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 23 24.. note:: 25 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires 26 a specific DTS for all the CPUs to be loaded. 27 28AArch32 with reset to BL1 entrypoint 29^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 30 31The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 32with 8 CPUs using the AArch32 build of TF-A. 33 34.. code:: shell 35 36 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 37 -C pctl.startup=0.0.0.0 \ 38 -C bp.secure_memory=1 \ 39 -C bp.tzc_400.diagnostics=1 \ 40 -C cluster0.NUM_CORES=4 \ 41 -C cluster1.NUM_CORES=4 \ 42 -C cache_state_modelled=1 \ 43 -C cluster0.cpu0.CONFIG64=0 \ 44 -C cluster0.cpu1.CONFIG64=0 \ 45 -C cluster0.cpu2.CONFIG64=0 \ 46 -C cluster0.cpu3.CONFIG64=0 \ 47 -C cluster1.cpu0.CONFIG64=0 \ 48 -C cluster1.cpu1.CONFIG64=0 \ 49 -C cluster1.cpu2.CONFIG64=0 \ 50 -C cluster1.cpu3.CONFIG64=0 \ 51 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 52 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 53 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 54 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 55 56AArch64 with reset to BL31 entrypoint 57^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 58 59The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux 60with 8 CPUs using the AArch64 build of TF-A. 61 62.. code:: shell 63 64 <path-to>/FVP_Base_RevC-2xAEMv8A \ 65 -C pctl.startup=0.0.0.0 \ 66 -C bp.secure_memory=1 \ 67 -C bp.tzc_400.diagnostics=1 \ 68 -C cluster0.NUM_CORES=4 \ 69 -C cluster1.NUM_CORES=4 \ 70 -C cache_state_modelled=1 \ 71 -C cluster0.cpu0.RVBAR=0x04010000 \ 72 -C cluster0.cpu1.RVBAR=0x04010000 \ 73 -C cluster0.cpu2.RVBAR=0x04010000 \ 74 -C cluster0.cpu3.RVBAR=0x04010000 \ 75 -C cluster1.cpu0.RVBAR=0x04010000 \ 76 -C cluster1.cpu1.RVBAR=0x04010000 \ 77 -C cluster1.cpu2.RVBAR=0x04010000 \ 78 -C cluster1.cpu3.RVBAR=0x04010000 \ 79 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 80 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 81 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 82 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 83 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 84 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 85 86Notes: 87 88- Position Independent Executable (PIE) support is enabled in this 89 config allowing BL31 to be loaded at any valid address for execution. 90 91- Since a FIP is not loaded when using BL31 as reset entrypoint, the 92 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`` 93 parameter is needed to load the individual bootloader images in memory. 94 BL32 image is only needed if BL31 has been built to expect a Secure-EL1 95 Payload. For the same reason, the FDT needs to be compiled from the DT source 96 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000`` 97 parameter. 98 99- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a 100 specific DTS for all the CPUs to be loaded. 101 102- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where 103 X and Y are the cluster and CPU numbers respectively, is used to set the 104 reset vector for each core. 105 106- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require 107 changing the value of 108 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of 109 ``BL32_BASE``. 110 111AArch32 with reset to SP_MIN entrypoint 112^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 113 114The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux 115with 8 CPUs using the AArch32 build of TF-A. 116 117.. code:: shell 118 119 <path-to>/FVP_Base_AEMv8A-AEMv8A \ 120 -C pctl.startup=0.0.0.0 \ 121 -C bp.secure_memory=1 \ 122 -C bp.tzc_400.diagnostics=1 \ 123 -C cluster0.NUM_CORES=4 \ 124 -C cluster1.NUM_CORES=4 \ 125 -C cache_state_modelled=1 \ 126 -C cluster0.cpu0.CONFIG64=0 \ 127 -C cluster0.cpu1.CONFIG64=0 \ 128 -C cluster0.cpu2.CONFIG64=0 \ 129 -C cluster0.cpu3.CONFIG64=0 \ 130 -C cluster1.cpu0.CONFIG64=0 \ 131 -C cluster1.cpu1.CONFIG64=0 \ 132 -C cluster1.cpu2.CONFIG64=0 \ 133 -C cluster1.cpu3.CONFIG64=0 \ 134 -C cluster0.cpu0.RVBAR=0x04002000 \ 135 -C cluster0.cpu1.RVBAR=0x04002000 \ 136 -C cluster0.cpu2.RVBAR=0x04002000 \ 137 -C cluster0.cpu3.RVBAR=0x04002000 \ 138 -C cluster1.cpu0.RVBAR=0x04002000 \ 139 -C cluster1.cpu1.RVBAR=0x04002000 \ 140 -C cluster1.cpu2.RVBAR=0x04002000 \ 141 -C cluster1.cpu3.RVBAR=0x04002000 \ 142 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ 143 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 144 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 145 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 146 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 147 148.. note:: 149 Position Independent Executable (PIE) support is enabled in this 150 config allowing SP_MIN to be loaded at any valid address for execution. 151 152-------------- 153 154*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* 155