1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef COMMON_DEF_H 7 #define COMMON_DEF_H 8 9 #include <common/bl_common.h> 10 #include <lib/utils_def.h> 11 #include <lib/xlat_tables/xlat_tables_defs.h> 12 13 #include <platform_def.h> 14 15 #ifdef __aarch64__ 16 #define SZ_32 UL(0x00000020) 17 #define SZ_64 UL(0x00000040) 18 #define SZ_128 UL(0x00000080) 19 #define SZ_256 UL(0x00000100) 20 #define SZ_512 UL(0x00000200) 21 22 #define SZ_1K UL(0x00000400) 23 #define SZ_2K UL(0x00000800) 24 #define SZ_4K UL(0x00001000) 25 #define SZ_8K UL(0x00002000) 26 #define SZ_16K UL(0x00004000) 27 #define SZ_32K UL(0x00008000) 28 #define SZ_64K UL(0x00010000) 29 #define SZ_128K UL(0x00020000) 30 #define SZ_256K UL(0x00040000) 31 #define SZ_512K UL(0x00080000) 32 33 #define SZ_1M UL(0x00100000) 34 #define SZ_2M UL(0x00200000) 35 #define SZ_4M UL(0x00400000) 36 #define SZ_8M UL(0x00800000) 37 #define SZ_16M UL(0x01000000) 38 #define SZ_32M UL(0x02000000) 39 #define SZ_64M UL(0x04000000) 40 #define SZ_128M UL(0x08000000) 41 #define SZ_256M UL(0x10000000) 42 #define SZ_512M UL(0x20000000) 43 44 #define SZ_1G UL(0x40000000) 45 #define SZ_2G UL(0x80000000) 46 #else /* !__aarch64__ */ 47 #define SZ_32 U(0x00000020) 48 #define SZ_64 U(0x00000040) 49 #define SZ_128 U(0x00000080) 50 #define SZ_256 U(0x00000100) 51 #define SZ_512 U(0x00000200) 52 53 #define SZ_1K U(0x00000400) 54 #define SZ_2K U(0x00000800) 55 #define SZ_4K U(0x00001000) 56 #define SZ_8K U(0x00002000) 57 #define SZ_16K U(0x00004000) 58 #define SZ_32K U(0x00008000) 59 #define SZ_64K U(0x00010000) 60 #define SZ_128K U(0x00020000) 61 #define SZ_256K U(0x00040000) 62 #define SZ_512K U(0x00080000) 63 64 #define SZ_1M U(0x00100000) 65 #define SZ_2M U(0x00200000) 66 #define SZ_4M U(0x00400000) 67 #define SZ_8M U(0x00800000) 68 #define SZ_16M U(0x01000000) 69 #define SZ_32M U(0x02000000) 70 #define SZ_64M U(0x04000000) 71 #define SZ_128M U(0x08000000) 72 #define SZ_256M U(0x10000000) 73 #define SZ_512M U(0x20000000) 74 75 #define SZ_1G U(0x40000000) 76 #define SZ_2G U(0x80000000) 77 #endif /* __aarch64__ */ 78 79 /****************************************************************************** 80 * Required platform porting definitions that are expected to be common to 81 * all platforms 82 *****************************************************************************/ 83 84 /* 85 * Platform binary types for linking 86 */ 87 #ifdef __aarch64__ 88 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 89 #define PLATFORM_LINKER_ARCH aarch64 90 #else 91 #define PLATFORM_LINKER_FORMAT "elf32-littlearm" 92 #define PLATFORM_LINKER_ARCH arm 93 #endif /* __aarch64__ */ 94 95 /* 96 * Generic platform constants 97 */ 98 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 99 100 #define BL2_IMAGE_DESC { \ 101 .image_id = BL2_IMAGE_ID, \ 102 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \ 103 VERSION_2, image_info_t, 0), \ 104 .image_info.image_base = BL2_BASE, \ 105 .image_info.image_max_size = BL2_LIMIT - BL2_BASE,\ 106 SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, \ 107 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),\ 108 .ep_info.pc = BL2_BASE, \ 109 } 110 111 /* 112 * The following constants identify the extents of the code & read-only data 113 * regions. These addresses are used by the MMU setup code and therefore they 114 * must be page-aligned. 115 * 116 * When the code and read-only data are mapped as a single atomic section 117 * (i.e. when SEPARATE_CODE_AND_RODATA=0) then we treat the whole section as 118 * code by specifying the read-only data section as empty. 119 * 120 * BL1 is different than the other images in the sense that its read-write data 121 * originally lives in Trusted ROM and needs to be relocated in Trusted SRAM at 122 * run-time. Therefore, the read-write data in ROM can be mapped with the same 123 * memory attributes as the read-only data region. For this reason, BL1 uses 124 * different macros. 125 * 126 * Note that BL1_ROM_END is not necessarily aligned on a page boundary as it 127 * just points to the end of BL1's actual content in Trusted ROM. Therefore it 128 * needs to be rounded up to the next page size in order to map the whole last 129 * page of it with the right memory attributes. 130 */ 131 #if SEPARATE_CODE_AND_RODATA 132 133 #define BL1_CODE_END BL_CODE_END 134 #define BL1_RO_DATA_BASE BL_RO_DATA_BASE 135 #define BL1_RO_DATA_END round_up(BL1_ROM_END, PAGE_SIZE) 136 #if BL2_IN_XIP_MEM 137 #define BL2_CODE_END BL_CODE_END 138 #define BL2_RO_DATA_BASE BL_RO_DATA_BASE 139 #define BL2_RO_DATA_END round_up(BL2_ROM_END, PAGE_SIZE) 140 #endif /* BL2_IN_XIP_MEM */ 141 #else 142 #define BL_RO_DATA_BASE UL(0) 143 #define BL_RO_DATA_END UL(0) 144 #define BL1_CODE_END round_up(BL1_ROM_END, PAGE_SIZE) 145 #if BL2_IN_XIP_MEM 146 #define BL2_RO_DATA_BASE UL(0) 147 #define BL2_RO_DATA_END UL(0) 148 #define BL2_CODE_END round_up(BL2_ROM_END, PAGE_SIZE) 149 #endif /* BL2_IN_XIP_MEM */ 150 #endif /* SEPARATE_CODE_AND_RODATA */ 151 152 #if MEASURED_BOOT 153 /* 154 * Start critical data Ids from 2^32/2 reserving Ids from 0 to (2^32/2 - 1) 155 * for Images, It is a critical data Id base for all platforms. 156 */ 157 #define CRITICAL_DATA_ID_BASE U(0x80000000) 158 #endif /* MEASURED_BOOT */ 159 160 #endif /* COMMON_DEF_H */ 161