1 /*
2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <lib/pmf/pmf.h>
14 #include <lib/runtime_instr.h>
15 #include <lib/smccc.h>
16 #include <plat/common/platform.h>
17 #include <services/arm_arch_svc.h>
18
19 #include "psci_private.h"
20
21 /*******************************************************************************
22 * PSCI frontend api for servicing SMCs. Described in the PSCI spec.
23 ******************************************************************************/
psci_cpu_on(u_register_t target_cpu,uintptr_t entrypoint,u_register_t context_id)24 int psci_cpu_on(u_register_t target_cpu,
25 uintptr_t entrypoint,
26 u_register_t context_id)
27
28 {
29 int rc;
30 entry_point_info_t ep;
31
32 /* Validate the target CPU */
33 if (!is_valid_mpidr(target_cpu))
34 return PSCI_E_INVALID_PARAMS;
35
36 /* Validate the entry point and get the entry_point_info */
37 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
38 if (rc != PSCI_E_SUCCESS)
39 return rc;
40
41 /*
42 * To turn this cpu on, specify which power
43 * levels need to be turned on
44 */
45 return psci_cpu_on_start(target_cpu, &ep);
46 }
47
psci_version(void)48 unsigned int psci_version(void)
49 {
50 return PSCI_MAJOR_VER | PSCI_MINOR_VER;
51 }
52
psci_cpu_suspend(unsigned int power_state,uintptr_t entrypoint,u_register_t context_id)53 int psci_cpu_suspend(unsigned int power_state,
54 uintptr_t entrypoint,
55 u_register_t context_id)
56 {
57 int rc;
58 unsigned int target_pwrlvl, is_power_down_state;
59 entry_point_info_t ep;
60 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
61 plat_local_state_t cpu_pd_state;
62 #if PSCI_OS_INIT_MODE
63 unsigned int cpu_idx = plat_my_core_pos();
64 plat_local_state_t prev[PLAT_MAX_PWR_LVL];
65 #endif
66
67 /* Validate the power_state parameter */
68 rc = psci_validate_power_state(power_state, &state_info);
69 if (rc != PSCI_E_SUCCESS) {
70 assert(rc == PSCI_E_INVALID_PARAMS);
71 return rc;
72 }
73
74 /*
75 * Get the value of the state type bit from the power state parameter.
76 */
77 is_power_down_state = psci_get_pstate_type(power_state);
78
79 /* Sanity check the requested suspend levels */
80 assert(psci_validate_suspend_req(&state_info, is_power_down_state)
81 == PSCI_E_SUCCESS);
82
83 target_pwrlvl = psci_find_target_suspend_lvl(&state_info);
84 if (target_pwrlvl == PSCI_INVALID_PWR_LVL) {
85 ERROR("Invalid target power level for suspend operation\n");
86 panic();
87 }
88
89 /* Fast path for CPU standby.*/
90 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) {
91 if (psci_plat_pm_ops->cpu_standby == NULL)
92 return PSCI_E_INVALID_PARAMS;
93
94 /*
95 * Set the state of the CPU power domain to the platform
96 * specific retention state and enter the standby state.
97 */
98 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL];
99 psci_set_cpu_local_state(cpu_pd_state);
100
101 #if PSCI_OS_INIT_MODE
102 /*
103 * If in OS-initiated mode, save a copy of the previous
104 * requested local power states and update the new requested
105 * local power states for this CPU.
106 */
107 if (psci_suspend_mode == OS_INIT) {
108 psci_update_req_local_pwr_states(target_pwrlvl, cpu_idx,
109 &state_info, prev);
110 }
111 #endif
112
113 #if ENABLE_PSCI_STAT
114 plat_psci_stat_accounting_start(&state_info);
115 #endif
116
117 #if ENABLE_RUNTIME_INSTRUMENTATION
118 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
119 RT_INSTR_ENTER_HW_LOW_PWR,
120 PMF_NO_CACHE_MAINT);
121 #endif
122
123 psci_plat_pm_ops->cpu_standby(cpu_pd_state);
124
125 /* Upon exit from standby, set the state back to RUN. */
126 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
127
128 #if PSCI_OS_INIT_MODE
129 /*
130 * If in OS-initiated mode, restore the previous requested
131 * local power states for this CPU.
132 */
133 if (psci_suspend_mode == OS_INIT) {
134 psci_restore_req_local_pwr_states(cpu_idx, prev);
135 }
136 #endif
137
138 #if ENABLE_RUNTIME_INSTRUMENTATION
139 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
140 RT_INSTR_EXIT_HW_LOW_PWR,
141 PMF_NO_CACHE_MAINT);
142 #endif
143
144 #if ENABLE_PSCI_STAT
145 plat_psci_stat_accounting_stop(&state_info);
146
147 /* Update PSCI stats */
148 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info);
149 #endif
150
151 return PSCI_E_SUCCESS;
152 }
153
154 /*
155 * If a power down state has been requested, we need to verify entry
156 * point and program entry information.
157 */
158 if (is_power_down_state != 0U) {
159 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
160 if (rc != PSCI_E_SUCCESS)
161 return rc;
162 }
163
164 /*
165 * Do what is needed to enter the power down state. Upon success,
166 * enter the final wfi which will power down this CPU. This function
167 * might return if the power down was abandoned for any reason, e.g.
168 * arrival of an interrupt
169 */
170 rc = psci_cpu_suspend_start(&ep,
171 target_pwrlvl,
172 &state_info,
173 is_power_down_state);
174
175 return rc;
176 }
177
178
psci_system_suspend(uintptr_t entrypoint,u_register_t context_id)179 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id)
180 {
181 int rc;
182 psci_power_state_t state_info;
183 entry_point_info_t ep;
184
185 /* Check if the current CPU is the last ON CPU in the system */
186 if (!psci_is_last_on_cpu())
187 return PSCI_E_DENIED;
188
189 /* Validate the entry point and get the entry_point_info */
190 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
191 if (rc != PSCI_E_SUCCESS)
192 return rc;
193
194 /* Query the psci_power_state for system suspend */
195 psci_query_sys_suspend_pwrstate(&state_info);
196
197 /*
198 * Check if platform allows suspend to Highest power level
199 * (System level)
200 */
201 if (psci_find_target_suspend_lvl(&state_info) < PLAT_MAX_PWR_LVL)
202 return PSCI_E_DENIED;
203
204 /* Ensure that the psci_power_state makes sense */
205 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN)
206 == PSCI_E_SUCCESS);
207 assert(is_local_state_off(
208 state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]) != 0);
209
210 /*
211 * Do what is needed to enter the system suspend state. This function
212 * might return if the power down was abandoned for any reason, e.g.
213 * arrival of an interrupt
214 */
215 rc = psci_cpu_suspend_start(&ep,
216 PLAT_MAX_PWR_LVL,
217 &state_info,
218 PSTATE_TYPE_POWERDOWN);
219
220 return rc;
221 }
222
psci_cpu_off(void)223 int psci_cpu_off(void)
224 {
225 int rc;
226 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL;
227
228 /*
229 * Do what is needed to power off this CPU and possible higher power
230 * levels if it able to do so. Upon success, enter the final wfi
231 * which will power down this CPU.
232 */
233 rc = psci_do_cpu_off(target_pwrlvl);
234
235 /*
236 * The only error cpu_off can return is E_DENIED. So check if that's
237 * indeed the case.
238 */
239 assert(rc == PSCI_E_DENIED);
240
241 return rc;
242 }
243
psci_affinity_info(u_register_t target_affinity,unsigned int lowest_affinity_level)244 int psci_affinity_info(u_register_t target_affinity,
245 unsigned int lowest_affinity_level)
246 {
247 unsigned int target_idx;
248
249 /* Validate the target affinity */
250 if (!is_valid_mpidr(target_affinity))
251 return PSCI_E_INVALID_PARAMS;
252
253 /* We dont support level higher than PSCI_CPU_PWR_LVL */
254 if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
255 return PSCI_E_INVALID_PARAMS;
256
257 /* Calculate the cpu index of the target */
258 target_idx = (unsigned int) plat_core_pos_by_mpidr(target_affinity);
259
260 /*
261 * Generic management:
262 * Perform cache maintanence ahead of reading the target CPU state to
263 * ensure that the data is not stale.
264 * There is a theoretical edge case where the cache may contain stale
265 * data for the target CPU data - this can occur under the following
266 * conditions:
267 * - the target CPU is in another cluster from the current
268 * - the target CPU was the last CPU to shutdown on its cluster
269 * - the cluster was removed from coherency as part of the CPU shutdown
270 *
271 * In this case the cache maintenace that was performed as part of the
272 * target CPUs shutdown was not seen by the current CPU's cluster. And
273 * so the cache may contain stale data for the target CPU.
274 */
275 flush_cpu_data_by_index(target_idx,
276 psci_svc_cpu_data.aff_info_state);
277
278 return psci_get_aff_info_state_by_idx(target_idx);
279 }
280
psci_migrate(u_register_t target_cpu)281 int psci_migrate(u_register_t target_cpu)
282 {
283 int rc;
284 u_register_t resident_cpu_mpidr;
285
286 /* Validate the target cpu */
287 if (!is_valid_mpidr(target_cpu))
288 return PSCI_E_INVALID_PARAMS;
289
290 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
291 if (rc != PSCI_TOS_UP_MIG_CAP)
292 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ?
293 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED;
294
295 /*
296 * Migrate should only be invoked on the CPU where
297 * the Secure OS is resident.
298 */
299 if (resident_cpu_mpidr != read_mpidr_el1())
300 return PSCI_E_NOT_PRESENT;
301
302 /* Check the validity of the specified target cpu */
303 if (!is_valid_mpidr(target_cpu))
304 return PSCI_E_INVALID_PARAMS;
305
306 assert((psci_spd_pm != NULL) && (psci_spd_pm->svc_migrate != NULL));
307
308 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu);
309 assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL));
310
311 return rc;
312 }
313
psci_migrate_info_type(void)314 int psci_migrate_info_type(void)
315 {
316 u_register_t resident_cpu_mpidr;
317
318 return psci_spd_migrate_info(&resident_cpu_mpidr);
319 }
320
psci_migrate_info_up_cpu(void)321 u_register_t psci_migrate_info_up_cpu(void)
322 {
323 u_register_t resident_cpu_mpidr;
324 int rc;
325
326 /*
327 * Return value of this depends upon what
328 * psci_spd_migrate_info() returns.
329 */
330 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
331 if ((rc != PSCI_TOS_NOT_UP_MIG_CAP) && (rc != PSCI_TOS_UP_MIG_CAP))
332 return (u_register_t)(register_t) PSCI_E_INVALID_PARAMS;
333
334 return resident_cpu_mpidr;
335 }
336
psci_node_hw_state(u_register_t target_cpu,unsigned int power_level)337 int psci_node_hw_state(u_register_t target_cpu,
338 unsigned int power_level)
339 {
340 int rc;
341
342 /* Validate target_cpu */
343 if (!is_valid_mpidr(target_cpu))
344 return PSCI_E_INVALID_PARAMS;
345
346 /* Validate power_level against PLAT_MAX_PWR_LVL */
347 if (power_level > PLAT_MAX_PWR_LVL)
348 return PSCI_E_INVALID_PARAMS;
349
350 /*
351 * Dispatch this call to platform to query power controller, and pass on
352 * to the caller what it returns
353 */
354 assert(psci_plat_pm_ops->get_node_hw_state != NULL);
355 rc = psci_plat_pm_ops->get_node_hw_state(target_cpu, power_level);
356 assert(((rc >= HW_ON) && (rc <= HW_STANDBY))
357 || (rc == PSCI_E_NOT_SUPPORTED)
358 || (rc == PSCI_E_INVALID_PARAMS));
359 return rc;
360 }
361
psci_features(unsigned int psci_fid)362 int psci_features(unsigned int psci_fid)
363 {
364 unsigned int local_caps = psci_caps;
365
366 if (psci_fid == SMCCC_VERSION)
367 return PSCI_E_SUCCESS;
368
369 /* Check if it is a 64 bit function */
370 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64)
371 local_caps &= PSCI_CAP_64BIT_MASK;
372
373 /* Check for invalid fid */
374 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid)
375 && is_psci_fid(psci_fid)))
376 return PSCI_E_NOT_SUPPORTED;
377
378
379 /* Check if the psci fid is supported or not */
380 if ((local_caps & define_psci_cap(psci_fid)) == 0U)
381 return PSCI_E_NOT_SUPPORTED;
382
383 /* Format the feature flags */
384 if ((psci_fid == PSCI_CPU_SUSPEND_AARCH32) ||
385 (psci_fid == PSCI_CPU_SUSPEND_AARCH64)) {
386 unsigned int ret = ((FF_PSTATE << FF_PSTATE_SHIFT) |
387 (FF_SUPPORTS_OS_INIT_MODE << FF_MODE_SUPPORT_SHIFT));
388 return (int)ret;
389 }
390
391 /* Return 0 for all other fid's */
392 return PSCI_E_SUCCESS;
393 }
394
395 #if PSCI_OS_INIT_MODE
psci_set_suspend_mode(unsigned int mode)396 int psci_set_suspend_mode(unsigned int mode)
397 {
398 if (psci_suspend_mode == mode) {
399 return PSCI_E_SUCCESS;
400 }
401
402 if (mode == PLAT_COORD) {
403 /* Check if the current CPU is the last ON CPU in the system */
404 if (!psci_is_last_on_cpu_safe()) {
405 return PSCI_E_DENIED;
406 }
407 }
408
409 if (mode == OS_INIT) {
410 /*
411 * Check if all CPUs in the system are ON or if the current
412 * CPU is the last ON CPU in the system.
413 */
414 if (!(psci_are_all_cpus_on_safe() ||
415 psci_is_last_on_cpu_safe())) {
416 return PSCI_E_DENIED;
417 }
418 }
419
420 psci_suspend_mode = mode;
421 psci_flush_dcache_range((uintptr_t)&psci_suspend_mode,
422 sizeof(psci_suspend_mode));
423
424 return PSCI_E_SUCCESS;
425 }
426 #endif
427
428 /*******************************************************************************
429 * PSCI top level handler for servicing SMCs.
430 ******************************************************************************/
psci_smc_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * cookie,void * handle,u_register_t flags)431 u_register_t psci_smc_handler(uint32_t smc_fid,
432 u_register_t x1,
433 u_register_t x2,
434 u_register_t x3,
435 u_register_t x4,
436 void *cookie,
437 void *handle,
438 u_register_t flags)
439 {
440 u_register_t ret;
441
442 if (is_caller_secure(flags))
443 return (u_register_t)SMC_UNK;
444
445 /* Check the fid against the capabilities */
446 if ((psci_caps & define_psci_cap(smc_fid)) == 0U)
447 return (u_register_t)SMC_UNK;
448
449 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
450 /* 32-bit PSCI function, clear top parameter bits */
451
452 uint32_t r1 = (uint32_t)x1;
453 uint32_t r2 = (uint32_t)x2;
454 uint32_t r3 = (uint32_t)x3;
455
456 switch (smc_fid) {
457 case PSCI_VERSION:
458 ret = (u_register_t)psci_version();
459 break;
460
461 case PSCI_CPU_OFF:
462 ret = (u_register_t)psci_cpu_off();
463 break;
464
465 case PSCI_CPU_SUSPEND_AARCH32:
466 ret = (u_register_t)psci_cpu_suspend(r1, r2, r3);
467 break;
468
469 case PSCI_CPU_ON_AARCH32:
470 ret = (u_register_t)psci_cpu_on(r1, r2, r3);
471 break;
472
473 case PSCI_AFFINITY_INFO_AARCH32:
474 ret = (u_register_t)psci_affinity_info(r1, r2);
475 break;
476
477 case PSCI_MIG_AARCH32:
478 ret = (u_register_t)psci_migrate(r1);
479 break;
480
481 case PSCI_MIG_INFO_TYPE:
482 ret = (u_register_t)psci_migrate_info_type();
483 break;
484
485 case PSCI_MIG_INFO_UP_CPU_AARCH32:
486 ret = psci_migrate_info_up_cpu();
487 break;
488
489 case PSCI_NODE_HW_STATE_AARCH32:
490 ret = (u_register_t)psci_node_hw_state(r1, r2);
491 break;
492
493 case PSCI_SYSTEM_SUSPEND_AARCH32:
494 ret = (u_register_t)psci_system_suspend(r1, r2);
495 break;
496
497 case PSCI_SYSTEM_OFF:
498 psci_system_off();
499 /* We should never return from psci_system_off() */
500 break;
501
502 case PSCI_SYSTEM_RESET:
503 psci_system_reset();
504 /* We should never return from psci_system_reset() */
505 break;
506
507 case PSCI_FEATURES:
508 ret = (u_register_t)psci_features(r1);
509 break;
510
511 #if PSCI_OS_INIT_MODE
512 case PSCI_SET_SUSPEND_MODE:
513 ret = (u_register_t)psci_set_suspend_mode(r1);
514 break;
515 #endif
516
517 #if ENABLE_PSCI_STAT
518 case PSCI_STAT_RESIDENCY_AARCH32:
519 ret = psci_stat_residency(r1, r2);
520 break;
521
522 case PSCI_STAT_COUNT_AARCH32:
523 ret = psci_stat_count(r1, r2);
524 break;
525 #endif
526 case PSCI_MEM_PROTECT:
527 ret = psci_mem_protect(r1);
528 break;
529
530 case PSCI_MEM_CHK_RANGE_AARCH32:
531 ret = psci_mem_chk_range(r1, r2);
532 break;
533
534 case PSCI_SYSTEM_RESET2_AARCH32:
535 /* We should never return from psci_system_reset2() */
536 ret = psci_system_reset2(r1, r2);
537 break;
538
539 default:
540 WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid);
541 ret = (u_register_t)SMC_UNK;
542 break;
543 }
544 } else {
545 /* 64-bit PSCI function */
546
547 switch (smc_fid) {
548 case PSCI_CPU_SUSPEND_AARCH64:
549 ret = (u_register_t)
550 psci_cpu_suspend((unsigned int)x1, x2, x3);
551 break;
552
553 case PSCI_CPU_ON_AARCH64:
554 ret = (u_register_t)psci_cpu_on(x1, x2, x3);
555 break;
556
557 case PSCI_AFFINITY_INFO_AARCH64:
558 ret = (u_register_t)
559 psci_affinity_info(x1, (unsigned int)x2);
560 break;
561
562 case PSCI_MIG_AARCH64:
563 ret = (u_register_t)psci_migrate(x1);
564 break;
565
566 case PSCI_MIG_INFO_UP_CPU_AARCH64:
567 ret = psci_migrate_info_up_cpu();
568 break;
569
570 case PSCI_NODE_HW_STATE_AARCH64:
571 ret = (u_register_t)psci_node_hw_state(
572 x1, (unsigned int) x2);
573 break;
574
575 case PSCI_SYSTEM_SUSPEND_AARCH64:
576 ret = (u_register_t)psci_system_suspend(x1, x2);
577 break;
578
579 #if ENABLE_PSCI_STAT
580 case PSCI_STAT_RESIDENCY_AARCH64:
581 ret = psci_stat_residency(x1, (unsigned int) x2);
582 break;
583
584 case PSCI_STAT_COUNT_AARCH64:
585 ret = psci_stat_count(x1, (unsigned int) x2);
586 break;
587 #endif
588
589 case PSCI_MEM_CHK_RANGE_AARCH64:
590 ret = psci_mem_chk_range(x1, x2);
591 break;
592
593 case PSCI_SYSTEM_RESET2_AARCH64:
594 /* We should never return from psci_system_reset2() */
595 ret = psci_system_reset2((uint32_t) x1, x2);
596 break;
597
598 default:
599 WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid);
600 ret = (u_register_t)SMC_UNK;
601 break;
602 }
603 }
604
605 return ret;
606 }
607