1 /*
2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <common/debug.h>
11 #include <drivers/arm/cci.h>
12 #include <drivers/arm/ccn.h>
13 #include <drivers/arm/gicv2.h>
14 #include <drivers/arm/sp804_delay_timer.h>
15 #include <drivers/generic_delay_timer.h>
16 #include <fconf_hw_config_getter.h>
17 #include <lib/mmio.h>
18 #include <lib/smccc.h>
19 #include <lib/xlat_tables/xlat_tables_compat.h>
20 #include <platform_def.h>
21 #include <services/arm_arch_svc.h>
22 #include <services/rmm_core_manifest.h>
23 #if SPM_MM
24 #include <services/spm_mm_partition.h>
25 #endif
26
27 #include <plat/arm/common/arm_config.h>
28 #include <plat/arm/common/plat_arm.h>
29 #include <plat/common/platform.h>
30
31 #include "fvp_private.h"
32
33 /* Defines for GIC Driver build time selection */
34 #define FVP_GICV2 1
35 #define FVP_GICV3 2
36
37 /* Defines for RMM Console*/
38 #define FVP_RMM_CONSOLE_BASE UL(0x1c0c0000)
39 #define FVP_RMM_CONSOLE_BAUD UL(115200)
40 #define FVP_RMM_CONSOLE_CLK_IN_HZ UL(14745600)
41 #define FVP_RMM_CONSOLE_NAME "pl011"
42
43 #define FVP_RMM_CONSOLE_COUNT UL(1)
44
45 /*******************************************************************************
46 * arm_config holds the characteristics of the differences between the three FVP
47 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
48 * at each boot stage by the primary before enabling the MMU (to allow
49 * interconnect configuration) & used thereafter. Each BL will have its own copy
50 * to allow independent operation.
51 ******************************************************************************/
52 arm_config_t arm_config;
53
54 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
55 DEVICE0_SIZE, \
56 MT_DEVICE | MT_RW | MT_SECURE)
57
58 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
59 DEVICE1_SIZE, \
60 MT_DEVICE | MT_RW | MT_SECURE)
61
62 #if FVP_GICR_REGION_PROTECTION
63 #define MAP_GICD_MEM MAP_REGION_FLAT(BASE_GICD_BASE, \
64 BASE_GICD_SIZE, \
65 MT_DEVICE | MT_RW | MT_SECURE)
66
67 /* Map all core's redistributor memory as read-only. After boots up,
68 * per-core map its redistributor memory as read-write */
69 #define MAP_GICR_MEM MAP_REGION_FLAT(BASE_GICR_BASE, \
70 (BASE_GICR_SIZE * PLATFORM_CORE_COUNT),\
71 MT_DEVICE | MT_RO | MT_SECURE)
72 #endif /* FVP_GICR_REGION_PROTECTION */
73
74 /*
75 * Need to be mapped with write permissions in order to set a new non-volatile
76 * counter value.
77 */
78 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
79 DEVICE2_SIZE, \
80 MT_DEVICE | MT_RW | MT_SECURE)
81
82 #if TRANSFER_LIST
83 #ifdef FW_NS_HANDOFF_BASE
84 #define MAP_FW_NS_HANDOFF \
85 MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, PLAT_ARM_FW_HANDOFF_SIZE, \
86 MT_MEMORY | MT_RW | MT_NS)
87 #endif
88 #ifdef PLAT_ARM_EL3_FW_HANDOFF_BASE
89 #define MAP_EL3_FW_HANDOFF \
90 MAP_REGION_FLAT(PLAT_ARM_EL3_FW_HANDOFF_BASE, \
91 PLAT_ARM_FW_HANDOFF_SIZE, MT_MEMORY | MT_RW | EL3_PAS)
92 #endif
93 #endif
94
95 /*
96 * Table of memory regions for various BL stages to map using the MMU.
97 * This doesn't include Trusted SRAM as setup_page_tables() already takes care
98 * of mapping it.
99 */
100 #ifdef IMAGE_BL1
101 const mmap_region_t plat_arm_mmap[] = {
102 ARM_MAP_SHARED_RAM,
103 V2M_MAP_FLASH0_RO,
104 V2M_MAP_IOFPGA,
105 MAP_DEVICE0,
106 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
107 MAP_DEVICE1,
108 #endif
109 #if TRUSTED_BOARD_BOOT
110 /* To access the Root of Trust Public Key registers. */
111 MAP_DEVICE2,
112 /* Map DRAM to authenticate NS_BL2U image. */
113 ARM_MAP_NS_DRAM1,
114 #endif
115 {0}
116 };
117 #endif
118 #ifdef IMAGE_BL2
119 const mmap_region_t plat_arm_mmap[] = {
120 ARM_MAP_SHARED_RAM,
121 V2M_MAP_FLASH0_RW,
122 V2M_MAP_IOFPGA,
123 MAP_DEVICE0,
124 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
125 MAP_DEVICE1,
126 #endif
127 ARM_MAP_NS_DRAM1,
128 #ifdef __aarch64__
129 ARM_MAP_DRAM2,
130 #endif
131 /*
132 * Required to load HW_CONFIG, SPMC and SPs to trusted DRAM.
133 */
134 ARM_MAP_TRUSTED_DRAM,
135
136 /*
137 * Required to load Event Log in TZC secured memory
138 */
139 #if MEASURED_BOOT && (defined(SPD_tspd) || defined(SPD_opteed) || \
140 defined(SPD_spmd))
141 ARM_MAP_EVENT_LOG_DRAM1,
142 #endif /* MEASURED_BOOT && (SPD_tspd || SPD_opteed || SPD_spmd) */
143
144 #if ENABLE_RME
145 ARM_MAP_RMM_DRAM,
146 ARM_MAP_GPT_L1_DRAM,
147 #endif /* ENABLE_RME */
148 #ifdef SPD_tspd
149 ARM_MAP_TSP_SEC_MEM,
150 #endif
151 #if TRUSTED_BOARD_BOOT
152 /* To access the Root of Trust Public Key registers. */
153 MAP_DEVICE2,
154 #endif /* TRUSTED_BOARD_BOOT */
155
156 #if CRYPTO_SUPPORT && !RESET_TO_BL2
157 /*
158 * To access shared the Mbed TLS heap while booting the
159 * system with Crypto support
160 */
161 ARM_MAP_BL1_RW,
162 #endif /* CRYPTO_SUPPORT && !RESET_TO_BL2 */
163 #if SPM_MM || SPMC_AT_EL3
164 ARM_SP_IMAGE_MMAP,
165 #endif
166 #if ARM_BL31_IN_DRAM
167 ARM_MAP_BL31_SEC_DRAM,
168 #endif
169 #ifdef SPD_opteed
170 ARM_MAP_OPTEE_CORE_MEM,
171 ARM_OPTEE_PAGEABLE_LOAD_MEM,
172 #endif
173 #ifdef MAP_EL3_FW_HANDOFF
174 MAP_EL3_FW_HANDOFF,
175 #endif
176 { 0 }
177 };
178 #endif
179 #ifdef IMAGE_BL2U
180 const mmap_region_t plat_arm_mmap[] = {
181 MAP_DEVICE0,
182 V2M_MAP_IOFPGA,
183 {0}
184 };
185 #endif
186 #ifdef IMAGE_BL31
187 const mmap_region_t plat_arm_mmap[] = {
188 ARM_MAP_SHARED_RAM,
189 #if USE_DEBUGFS
190 /* Required by devfip, can be removed if devfip is not used */
191 V2M_MAP_FLASH0_RW,
192 #endif /* USE_DEBUGFS */
193 ARM_MAP_EL3_TZC_DRAM,
194 V2M_MAP_IOFPGA,
195 MAP_DEVICE0,
196 #if FVP_GICR_REGION_PROTECTION
197 MAP_GICD_MEM,
198 MAP_GICR_MEM,
199 #else
200 MAP_DEVICE1,
201 #endif /* FVP_GICR_REGION_PROTECTION */
202 ARM_V2M_MAP_MEM_PROTECT,
203 #if SPM_MM
204 ARM_SPM_BUF_EL3_MMAP,
205 #endif
206 #if ENABLE_RME
207 ARM_MAP_GPT_L1_DRAM,
208 ARM_MAP_EL3_RMM_SHARED_MEM,
209 #endif
210 #ifdef MAP_FW_NS_HANDOFF
211 MAP_FW_NS_HANDOFF,
212 #endif
213 #ifdef MAP_EL3_FW_HANDOFF
214 MAP_EL3_FW_HANDOFF,
215 #endif
216 { 0 }
217 };
218
219 #if defined(IMAGE_BL31) && SPM_MM
220 const mmap_region_t plat_arm_secure_partition_mmap[] = {
221 V2M_MAP_IOFPGA_EL0, /* for the UART */
222 MAP_REGION_FLAT(DEVICE0_BASE,
223 DEVICE0_SIZE,
224 MT_DEVICE | MT_RO | MT_SECURE | MT_USER),
225 ARM_SP_IMAGE_MMAP,
226 ARM_SP_IMAGE_NS_BUF_MMAP,
227 ARM_SP_IMAGE_RW_MMAP,
228 ARM_SPM_BUF_EL0_MMAP,
229 {0}
230 };
231 #endif
232 #endif
233 #ifdef IMAGE_BL32
234 const mmap_region_t plat_arm_mmap[] = {
235 #ifndef __aarch64__
236 ARM_MAP_SHARED_RAM,
237 ARM_V2M_MAP_MEM_PROTECT,
238 #endif
239 V2M_MAP_IOFPGA,
240 MAP_DEVICE0,
241 MAP_DEVICE1,
242 {0}
243 };
244 #endif
245
246 #ifdef IMAGE_RMM
247 const mmap_region_t plat_arm_mmap[] = {
248 V2M_MAP_IOFPGA,
249 MAP_DEVICE0,
250 MAP_DEVICE1,
251 {0}
252 };
253 #endif
254
255 ARM_CASSERT_MMAP
256
257 #if FVP_INTERCONNECT_DRIVER != FVP_CCN
258 static const int fvp_cci400_map[] = {
259 PLAT_FVP_CCI400_CLUS0_SL_PORT,
260 PLAT_FVP_CCI400_CLUS1_SL_PORT,
261 };
262
263 static const int fvp_cci5xx_map[] = {
264 PLAT_FVP_CCI5XX_CLUS0_SL_PORT,
265 PLAT_FVP_CCI5XX_CLUS1_SL_PORT,
266 };
267
get_interconnect_master(void)268 static unsigned int get_interconnect_master(void)
269 {
270 unsigned int master;
271 u_register_t mpidr;
272
273 mpidr = read_mpidr_el1();
274 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ?
275 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);
276
277 assert(master < FVP_CLUSTER_COUNT);
278 return master;
279 }
280 #endif
281
282 #if defined(IMAGE_BL31) && SPM_MM
283 /*
284 * Boot information passed to a secure partition during initialisation. Linear
285 * indices in MP information will be filled at runtime.
286 */
287 static spm_mm_mp_info_t sp_mp_info[] = {
288 [0] = {0x80000000, 0},
289 [1] = {0x80000001, 0},
290 [2] = {0x80000002, 0},
291 [3] = {0x80000003, 0},
292 [4] = {0x80000100, 0},
293 [5] = {0x80000101, 0},
294 [6] = {0x80000102, 0},
295 [7] = {0x80000103, 0},
296 };
297
298 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
299 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
300 .h.version = VERSION_1,
301 .h.size = sizeof(spm_mm_boot_info_t),
302 .h.attr = 0,
303 .sp_mem_base = ARM_SP_IMAGE_BASE,
304 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
305 .sp_image_base = ARM_SP_IMAGE_BASE,
306 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
307 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
308 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
309 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
310 .sp_image_size = ARM_SP_IMAGE_SIZE,
311 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
312 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
313 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
314 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
315 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
316 .num_cpus = PLATFORM_CORE_COUNT,
317 .mp_info = &sp_mp_info[0],
318 };
319
plat_get_secure_partition_mmap(void * cookie)320 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
321 {
322 return plat_arm_secure_partition_mmap;
323 }
324
plat_get_secure_partition_boot_info(void * cookie)325 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
326 void *cookie)
327 {
328 return &plat_arm_secure_partition_boot_info;
329 }
330 #endif
331
332 /*******************************************************************************
333 * A single boot loader stack is expected to work on both the Foundation FVP
334 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
335 * SYS_ID register provides a mechanism for detecting the differences between
336 * these platforms. This information is stored in a per-BL array to allow the
337 * code to take the correct path.Per BL platform configuration.
338 ******************************************************************************/
fvp_config_setup(void)339 void __init fvp_config_setup(void)
340 {
341 unsigned int rev, hbi, bld, arch, sys_id;
342
343 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
344 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
345 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
346 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
347 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
348
349 if (arch != ARCH_MODEL) {
350 ERROR("This firmware is for FVP models\n");
351 panic();
352 }
353
354 /*
355 * The build field in the SYS_ID tells which variant of the GIC
356 * memory is implemented by the model.
357 */
358 switch (bld) {
359 case BLD_GIC_VE_MMAP:
360 ERROR("Legacy Versatile Express memory map for GIC peripheral"
361 " is not supported\n");
362 panic();
363 break;
364 case BLD_GIC_A53A57_MMAP:
365 break;
366 default:
367 ERROR("Unsupported board build %x\n", bld);
368 panic();
369 }
370
371 /*
372 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
373 * for the Foundation FVP.
374 */
375 switch (hbi) {
376 case HBI_FOUNDATION_FVP:
377 arm_config.flags = 0;
378
379 /*
380 * Check for supported revisions of Foundation FVP
381 * Allow future revisions to run but emit warning diagnostic
382 */
383 switch (rev) {
384 case REV_FOUNDATION_FVP_V2_0:
385 case REV_FOUNDATION_FVP_V2_1:
386 case REV_FOUNDATION_FVP_v9_1:
387 case REV_FOUNDATION_FVP_v9_6:
388 break;
389 default:
390 WARN("Unrecognized Foundation FVP revision %x\n", rev);
391 break;
392 }
393 break;
394 case HBI_BASE_FVP:
395 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC);
396
397 /*
398 * Check for supported revisions
399 * Allow future revisions to run but emit warning diagnostic
400 */
401 switch (rev) {
402 case REV_BASE_FVP_V0:
403 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400;
404 break;
405 case REV_BASE_FVP_REVC:
406 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 |
407 ARM_CONFIG_FVP_HAS_CCI5XX);
408 break;
409 default:
410 WARN("Unrecognized Base FVP revision %x\n", rev);
411 break;
412 }
413 break;
414 default:
415 ERROR("Unsupported board HBI number 0x%x\n", hbi);
416 panic();
417 }
418
419 /*
420 * We assume that the presence of MT bit, and therefore shifted
421 * affinities, is uniform across the platform: either all CPUs, or no
422 * CPUs implement it.
423 */
424 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U)
425 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
426 }
427
428
fvp_interconnect_init(void)429 void __init fvp_interconnect_init(void)
430 {
431 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
432 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
433 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported");
434 panic();
435 }
436
437 plat_arm_interconnect_init();
438 #else
439 uintptr_t cci_base = 0U;
440 const int *cci_map = NULL;
441 unsigned int map_size = 0U;
442
443 /* Initialize the right interconnect */
444 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) {
445 cci_base = PLAT_FVP_CCI5XX_BASE;
446 cci_map = fvp_cci5xx_map;
447 map_size = ARRAY_SIZE(fvp_cci5xx_map);
448 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) {
449 cci_base = PLAT_FVP_CCI400_BASE;
450 cci_map = fvp_cci400_map;
451 map_size = ARRAY_SIZE(fvp_cci400_map);
452 } else {
453 return;
454 }
455
456 assert(cci_base != 0U);
457 assert(cci_map != NULL);
458 cci_init(cci_base, cci_map, map_size);
459 #endif
460 }
461
fvp_interconnect_enable(void)462 void fvp_interconnect_enable(void)
463 {
464 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
465 plat_arm_interconnect_enter_coherency();
466 #else
467 unsigned int master;
468
469 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
470 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
471 master = get_interconnect_master();
472 cci_enable_snoop_dvm_reqs(master);
473 }
474 #endif
475 }
476
fvp_interconnect_disable(void)477 void fvp_interconnect_disable(void)
478 {
479 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
480 plat_arm_interconnect_exit_coherency();
481 #else
482 unsigned int master;
483
484 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
485 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
486 master = get_interconnect_master();
487 cci_disable_snoop_dvm_reqs(master);
488 }
489 #endif
490 }
491
492 #if CRYPTO_SUPPORT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)493 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
494 {
495 assert(heap_addr != NULL);
496 assert(heap_size != NULL);
497
498 return arm_get_mbedtls_heap(heap_addr, heap_size);
499 }
500 #endif /* CRYPTO_SUPPORT */
501
fvp_timer_init(void)502 void fvp_timer_init(void)
503 {
504 #if USE_SP804_TIMER
505 /* Enable the clock override for SP804 timer 0, which means that no
506 * clock dividers are applied and the raw (35MHz) clock will be used.
507 */
508 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
509
510 /* Initialize delay timer driver using SP804 dual timer 0 */
511 sp804_timer_init(V2M_SP804_TIMER0_BASE,
512 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
513 #else
514 generic_delay_timer_init();
515
516 /* Enable System level generic timer */
517 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
518 CNTCR_FCREQ(0U) | CNTCR_EN);
519 #endif /* USE_SP804_TIMER */
520 }
521
522 /*****************************************************************************
523 * plat_is_smccc_feature_available() - This function checks whether SMCCC
524 * feature is availabile for platform.
525 * @fid: SMCCC function id
526 *
527 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
528 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
529 *****************************************************************************/
plat_is_smccc_feature_available(u_register_t fid)530 int32_t plat_is_smccc_feature_available(u_register_t fid)
531 {
532 switch (fid) {
533 case SMCCC_ARCH_SOC_ID:
534 return SMC_ARCH_CALL_SUCCESS;
535 default:
536 return SMC_ARCH_CALL_NOT_SUPPORTED;
537 }
538 }
539
540 /* Get SOC version */
plat_get_soc_version(void)541 int32_t plat_get_soc_version(void)
542 {
543 return (int32_t)
544 (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE,
545 ARM_SOC_IDENTIFICATION_CODE) |
546 (FVP_SOC_ID & SOC_ID_IMPL_DEF_MASK));
547 }
548
549 /* Get SOC revision */
plat_get_soc_revision(void)550 int32_t plat_get_soc_revision(void)
551 {
552 unsigned int sys_id;
553
554 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
555 return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) &
556 V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
557 }
558
559 #if ENABLE_RME
560 /*
561 * Get a pointer to the RMM-EL3 Shared buffer and return it
562 * through the pointer passed as parameter.
563 *
564 * This function returns the size of the shared buffer.
565 */
plat_rmmd_get_el3_rmm_shared_mem(uintptr_t * shared)566 size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared)
567 {
568 *shared = (uintptr_t)RMM_SHARED_BASE;
569
570 return (size_t)RMM_SHARED_SIZE;
571 }
572
plat_rmmd_load_manifest(struct rmm_manifest * manifest)573 int plat_rmmd_load_manifest(struct rmm_manifest *manifest)
574 {
575 uint64_t checksum, num_banks, num_consoles;
576 struct ns_dram_bank *bank_ptr;
577 struct console_info *console_ptr;
578
579 assert(manifest != NULL);
580
581 /* Get number of DRAM banks */
582 num_banks = FCONF_GET_PROPERTY(hw_config, dram_layout, num_banks);
583 assert(num_banks <= ARM_DRAM_NUM_BANKS);
584
585 /* Set number of consoles */
586 num_consoles = FVP_RMM_CONSOLE_COUNT;
587
588 manifest->version = RMMD_MANIFEST_VERSION;
589 manifest->padding = 0U; /* RES0 */
590 manifest->plat_data = (uintptr_t)NULL;
591 manifest->plat_dram.num_banks = num_banks;
592 manifest->plat_console.num_consoles = num_consoles;
593
594 /*
595 * Boot Manifest structure illustration, with two dram banks and
596 * a single console.
597 *
598 * +----------------------------------------+
599 * | offset | field | comment |
600 * +--------+----------------+--------------+
601 * | 0 | version | 0x00000003 |
602 * +--------+----------------+--------------+
603 * | 4 | padding | 0x00000000 |
604 * +--------+----------------+--------------+
605 * | 8 | plat_data | NULL |
606 * +--------+----------------+--------------+
607 * | 16 | num_banks | |
608 * +--------+----------------+ |
609 * | 24 | banks | plat_dram |
610 * +--------+----------------+ |
611 * | 32 | checksum | |
612 * +--------+----------------+--------------+
613 * | 40 | num_consoles | |
614 * +--------+----------------+ |
615 * | 48 | consoles | plat_console |
616 * +--------+----------------+ |
617 * | 56 | checksum | |
618 * +--------+----------------+--------------+
619 * | 64 | base 0 | |
620 * +--------+----------------+ bank[0] |
621 * | 72 | size 0 | |
622 * +--------+----------------+--------------+
623 * | 80 | base 1 | |
624 * +--------+----------------+ bank[1] |
625 * | 88 | size 1 | |
626 * +--------+----------------+--------------+
627 * | 96 | base | |
628 * +--------+----------------+ |
629 * | 104 | map_pages | |
630 * +--------+----------------+ |
631 * | 112 | name | |
632 * +--------+----------------+ consoles[0] |
633 * | 120 | clk_in_hz | |
634 * +--------+----------------+ |
635 * | 128 | baud_rate | |
636 * +--------+----------------+ |
637 * | 136 | flags | |
638 * +--------+----------------+--------------+
639 */
640
641 bank_ptr = (struct ns_dram_bank *)
642 (((uintptr_t)manifest) + sizeof(*manifest));
643 console_ptr = (struct console_info *)
644 ((uintptr_t)bank_ptr + (num_banks * sizeof(*bank_ptr)));
645
646 manifest->plat_dram.banks = bank_ptr;
647 manifest->plat_console.consoles = console_ptr;
648
649 /* Ensure the manifest is not larger than the shared buffer */
650 assert((sizeof(struct rmm_manifest) +
651 (sizeof(struct console_info) * manifest->plat_console.num_consoles) +
652 (sizeof(struct ns_dram_bank) * manifest->plat_dram.num_banks)) <= ARM_EL3_RMM_SHARED_SIZE);
653
654 /* Calculate checksum of plat_dram structure */
655 checksum = num_banks + (uint64_t)bank_ptr;
656
657 /* Store FVP DRAM banks data in Boot Manifest */
658 for (unsigned long i = 0UL; i < num_banks; i++) {
659 uintptr_t base = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].base);
660 uint64_t size = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].size);
661
662 bank_ptr[i].base = base;
663 bank_ptr[i].size = size;
664
665 /* Update checksum */
666 checksum += base + size;
667 }
668
669 /* Checksum must be 0 */
670 manifest->plat_dram.checksum = ~checksum + 1UL;
671
672 /* Calculate the checksum of the plat_consoles structure */
673 checksum = num_consoles + (uint64_t)console_ptr;
674
675 /* Zero out the console info struct */
676 memset((void *)console_ptr, '\0', sizeof(struct console_info) * num_consoles);
677
678 console_ptr[0].map_pages = 1;
679 console_ptr[0].base = FVP_RMM_CONSOLE_BASE;
680 console_ptr[0].clk_in_hz = FVP_RMM_CONSOLE_CLK_IN_HZ;
681 console_ptr[0].baud_rate = FVP_RMM_CONSOLE_BAUD;
682
683 strlcpy(console_ptr[0].name, FVP_RMM_CONSOLE_NAME, RMM_CONSOLE_MAX_NAME_LEN-1UL);
684
685 /* Update checksum */
686 checksum += console_ptr[0].base + console_ptr[0].map_pages +
687 console_ptr[0].clk_in_hz + console_ptr[0].baud_rate;
688
689 /* Checksum must be 0 */
690 manifest->plat_console.checksum = ~checksum + 1UL;
691
692 return 0;
693 }
694 #endif /* ENABLE_RME */
695