1/*
2 * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <asm_macros.S>
8#include <platform_def.h>
9#include <cortex_a35.h>
10
11	.globl	plat_is_my_cpu_primary
12	.globl	plat_my_core_pos
13	.globl	plat_calc_core_pos
14	.globl	plat_reset_handler
15	.globl	plat_get_my_entrypoint
16	.globl	plat_secondary_cold_boot_setup
17	.globl	plat_crash_console_init
18	.globl	plat_crash_console_putc
19	.globl	plat_crash_console_flush
20	.globl	platform_mem_init
21	.globl  imx_mailbox_init
22
23	/* --------------------------------------------------------------------
24	 * Helper macro that reads the part number of the current CPU and jumps
25	 * to the given label if it matches the CPU MIDR provided.
26	 *
27	 * Clobbers x0.
28	 * --------------------------------------------------------------------
29	 */
30	.macro  jump_if_cpu_midr _cpu_midr, _label
31
32	mrs	x0, midr_el1
33	ubfx	x0, x0, MIDR_PN_SHIFT, #12
34	cmp     w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
35	b.eq	\_label
36
37	.endm
38
39	/* ----------------------------------------------
40	 * The mailbox_base is used to distinguish warm/cold
41	 * reset. The mailbox_base is in the data section, not
42	 * in .bss, this allows function to start using this
43	 * variable before the runtime memory is initialized.
44	 * ----------------------------------------------
45	 */
46	.section .data.mailbox_base
47	.align 3
48	mailbox_base: .quad 0x0
49
50	/* ----------------------------------------------
51	 * unsigned int plat_is_my_cpu_primary(void);
52	 * This function checks if this is the primary CPU
53	 * ----------------------------------------------
54	 */
55func plat_is_my_cpu_primary
56	mrs	x0, mpidr_el1
57	and	x0, x0, #(MPIDR_CPU_MASK)
58	cmp	x0, #PLAT_PRIMARY_CPU
59	cset	x0, eq
60	ret
61endfunc plat_is_my_cpu_primary
62
63	/* ----------------------------------------------
64	 * unsigned int plat_my_core_pos(void)
65	 * This Function uses the plat_calc_core_pos()
66	 * to get the index of the calling CPU.
67	 * ----------------------------------------------
68	 */
69func plat_my_core_pos
70	mrs	x0, mpidr_el1
71	and	x1, x0, #MPIDR_CPU_MASK
72	and 	x0, x0, #MPIDR_CLUSTER_MASK
73	add	x0, x1, x0, LSR #6
74	ret
75endfunc plat_my_core_pos
76
77	/*
78	 * unsigned int plat_calc_core_pos(uint64_t mpidr)
79	 * helper function to calculate the core position.
80	 * With this function.
81	 */
82func plat_calc_core_pos
83	and	x1, x0, #MPIDR_CPU_MASK
84	and 	x0, x0, #MPIDR_CLUSTER_MASK
85	add	x0, x1, x0, LSR #6
86	ret
87endfunc plat_calc_core_pos
88
89	/* ----------------------------------------------
90	 * function to handle platform specific reset.
91	 * ----------------------------------------------
92	 */
93func plat_reset_handler
94#if defined(PLAT_imx8ulp)
95	/* enable the 512KB cache by default */
96	mov	x0, #IMX_SIM1_BASE
97	/*
98	 * if the RVBADDR is ROM entry, that means we did
99	 * NOT switch the L2 cache to 512KB. default is 256K config,
100	 * so skip
101	 */
102	ldr	w1, [x0, #0x5c]
103	cmp	w1, #0x1000
104	b.eq	1f
105	add	x0, x0, #0x30
106	ldr	w1, [x0]
107	/* if already 512KB config, skip */
108	tbnz	w1, #4, 1f
109	ldr	w1, [x0]
110	orr	w1, w1, #0x10
111	str	w1, [x0]
112	orr	w1, w1, #0x10000
113	str	w1, [x0]
114	b	.
1151:	mrs	x0, CORTEX_A35_CPUECTLR_EL1
116	orr     x0, x0, #(0x1 << 0)
117	orr     x0, x0, #(0x1 << 3)
118	msr	CORTEX_A35_CPUECTLR_EL1, x0
119
120	mrs	x0, CORTEX_A35_L2ECTLR_EL1
121	orr     x0, x0, #(0x1 << 0)
122	msr	CORTEX_A35_L2ECTLR_EL1, x0
123	isb
124#endif
125	/* enable EL2 cpuectlr RW access */
126	mov	x0, #0x73
127	msr	actlr_el3, x0
128	msr	actlr_el2, x0
129	isb
130
131	ret
132endfunc plat_reset_handler
133
134	/* ---------------------------------------------
135	 * function to get the entrypoint.
136	 * ---------------------------------------------
137	 */
138func plat_get_my_entrypoint
139	adrp	x1, mailbox_base
140	ldr	x0, [x1, :lo12:mailbox_base]
141	ret
142endfunc	plat_get_my_entrypoint
143
144func imx_mailbox_init
145	adrp	x1, mailbox_base
146	str	x0, [x1, :lo12:mailbox_base]
147	ret
148endfunc imx_mailbox_init
149
150func plat_secondary_cold_boot_setup
151	b	.
152endfunc plat_secondary_cold_boot_setup
153
154func plat_crash_console_init
155	mov	x0, #1
156	ret
157endfunc plat_crash_console_init
158
159func plat_crash_console_putc
160	ret
161endfunc plat_crash_console_putc
162
163func plat_crash_console_flush
164	mov	x0, #0
165	ret
166endfunc plat_crash_console_flush
167
168func platform_mem_init
169	ret
170endfunc platform_mem_init
171