1 /*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef PWR_CTRL_H
8 #define PWR_CTRL_H
9
10 #include <stdbool.h>
11
12 #include <lib/mmio.h>
13
14 #include <platform_def.h>
15
16 /*******************************************************************************
17 * GPC definitions & declarations
18 ******************************************************************************/
19 /* GPC GLOBAL */
20 #define GPC_GLOBAL_BASE U(GPC_BASE + 0x4000)
21 #define GPC_AUTHEN_CTRL U(0x4)
22 #define GPC_DOMAIN U(0x10)
23 #define GPC_MASTER U(0x1c)
24 #define GPC_SYS_SLEEP U(0x40)
25 #define PMIC_CTRL U(0x100)
26 #define PMIC_PRE_DLY_CTRL U(0x104)
27 #define PMIC_STBY_ACK_CTRL U(0x108)
28 #define GPC_ROSC_CTRL U(0x200)
29 #define GPC_AON_MEM_CTRL U(0x204)
30 #define GPC_EFUSE_CTRL U(0x208)
31
32 #define FORCE_CPUx_DISABLE(x) (1 << (16 + (x)))
33 #define PMIC_STBY_EN BIT(0)
34 #define ROSC_OFF_EN BIT(0)
35
36 /* GPC CPU_CTRL */
37 #define CM_SLICE(x) (GPC_BASE + 0x800 * (x))
38 #define CM_AUTHEN_CTRL U(0x4)
39 #define CM_MISC U(0xc)
40 #define CM_MODE_CTRL U(0x10)
41 #define CM_IRQ_WAKEUP_MASK0 U(0x100)
42 #define CM_SYS_SLEEP_CTRL U(0x380)
43 #define IMR_NUM U(8)
44
45 /* CM_MISC */
46 #define SLEEP_HOLD_EN BIT(1)
47 #define IRQ_MUX BIT(5)
48 #define SW_WAKEUP BIT(6)
49
50 /* CM_SYS_SLEEP_CTRL */
51 #define SS_WAIT BIT(0)
52 #define SS_STOP BIT(1)
53 #define SS_SUSPEND BIT(2)
54
55 #define CM_MODE_RUN U(0x0)
56 #define CM_MODE_WAIT U(0x1)
57 #define CM_MODE_STOP U(0x2)
58 #define CM_MODE_SUSPEND U(0x3)
59
60 #define LPM_SETTING(d, m) ((m) << (((d) % 8) * 4))
61
62 enum gpc_cmc_slice {
63 CPU_M33,
64 CPU_A55C0,
65 CPU_A55C1,
66 CPU_A55_PLAT,
67 };
68
69 /* set gpc domain assignment */
gpc_assign_domains(unsigned int domains)70 static inline void gpc_assign_domains(unsigned int domains)
71 {
72 mmio_write_32(GPC_GLOBAL_BASE + GPC_DOMAIN, domains);
73 }
74
75 /* force a cpu into sleep status */
gpc_force_cpu_suspend(unsigned int cpu)76 static inline void gpc_force_cpu_suspend(unsigned int cpu)
77 {
78 mmio_setbits_32(GPC_GLOBAL_BASE + GPC_SYS_SLEEP, FORCE_CPUx_DISABLE(cpu));
79 }
80
gpc_pmic_stby_en(bool en)81 static inline void gpc_pmic_stby_en(bool en)
82 {
83 mmio_write_32(GPC_GLOBAL_BASE + PMIC_CTRL, en ? 1 : 0);
84 }
85
gpc_rosc_off(bool off)86 static inline void gpc_rosc_off(bool off)
87 {
88 mmio_write_32(GPC_GLOBAL_BASE + GPC_ROSC_CTRL, off ? 1 : 0);
89 }
90
gpc_set_cpu_mode(unsigned int cpu,unsigned int mode)91 static inline void gpc_set_cpu_mode(unsigned int cpu, unsigned int mode)
92 {
93 mmio_write_32(CM_SLICE(cpu) + CM_MODE_CTRL, mode);
94 }
95
gpc_select_wakeup_gic(unsigned int cpu)96 static inline void gpc_select_wakeup_gic(unsigned int cpu)
97 {
98 mmio_setbits_32(CM_SLICE(cpu) + CM_MISC, IRQ_MUX);
99 }
100
gpc_select_wakeup_raw_irq(unsigned int cpu)101 static inline void gpc_select_wakeup_raw_irq(unsigned int cpu)
102 {
103 mmio_clrbits_32(CM_SLICE(cpu) + CM_MISC, IRQ_MUX);
104 }
105
gpc_assert_sw_wakeup(unsigned int cpu)106 static inline void gpc_assert_sw_wakeup(unsigned int cpu)
107 {
108 mmio_setbits_32(CM_SLICE(cpu) + CM_MISC, SW_WAKEUP);
109 }
110
gpc_deassert_sw_wakeup(unsigned int cpu)111 static inline void gpc_deassert_sw_wakeup(unsigned int cpu)
112 {
113 mmio_clrbits_32(CM_SLICE(cpu) + CM_MISC, SW_WAKEUP);
114 }
115
gpc_clear_cpu_sleep_hold(unsigned int cpu)116 static inline void gpc_clear_cpu_sleep_hold(unsigned int cpu)
117 {
118 mmio_clrbits_32(CM_SLICE(cpu) + CM_MISC, SLEEP_HOLD_EN);
119 }
120
gpc_set_irq_mask(unsigned int cpu,unsigned int idx,uint32_t mask)121 static inline void gpc_set_irq_mask(unsigned int cpu, unsigned int idx, uint32_t mask)
122 {
123 mmio_write_32(CM_SLICE(cpu) + idx * 0x4 + CM_IRQ_WAKEUP_MASK0, mask);
124 }
125
126 /*******************************************************************************
127 * SRC definitions & declarations
128 ******************************************************************************/
129 #define SRC_SLICE(x) (SRC_BASE + 0x400 * (x))
130 #define SRC_AUTHEN_CTRL U(0x4)
131 #define SRC_LPM_SETTING0 U(0x10)
132 #define SRC_LPM_SETTING1 U(0x14)
133 #define SRC_LPM_SETTING2 U(0x18)
134 #define SRC_SLICE_SW_CTRL U(0x20)
135
136 #define SRC_MEM_CTRL U(0x4)
137 #define MEM_LP_EN BIT(2)
138 #define MEM_LP_RETN BIT(1)
139
140 enum mix_mem_mode {
141 MEM_OFF,
142 MEM_RETN,
143 };
144
145 enum src_mix_mem_slice {
146 SRC_GLOBAL,
147
148 /* MIX slice */
149 SRC_SENTINEL,
150 SRC_AON,
151 SRC_WKUP,
152 SRC_DDR,
153 SRC_DPHY,
154 SRC_ML,
155 SRC_NIC,
156 SRC_HSIO,
157 SRC_MEDIA,
158 SRC_M33P,
159 SRC_A55C0,
160 SRC_A55C1,
161 SRC_A55P,
162
163 /* MEM slice */
164 SRC_AON_MEM,
165 SRC_WKUP_MEM,
166 SRC_DDR_MEM,
167 SRC_DPHY_MEM,
168 SRC_ML_MEM,
169 SRC_NIC_MEM,
170 SRC_NIC_OCRAM,
171 SRC_HSIO_MEM,
172 SRC_MEDIA_MEM,
173 SRC_A55P0_MEM,
174 SRC_A55P1_MEM,
175 SRC_A55_SCU_MEM,
176 SRC_A55_L3_MEM,
177 };
178
src_authen_config(unsigned int mix,unsigned int wlist,unsigned int lpm_en)179 static inline void src_authen_config(unsigned int mix, unsigned int wlist,
180 unsigned int lpm_en)
181 {
182 mmio_write_32(SRC_SLICE(mix) + SRC_AUTHEN_CTRL, (wlist << 16) | (lpm_en << 2));
183 }
184
src_mix_set_lpm(unsigned int mix,unsigned int did,unsigned int lpm_mode)185 static inline void src_mix_set_lpm(unsigned int mix, unsigned int did, unsigned int lpm_mode)
186 {
187 mmio_clrsetbits_32(SRC_SLICE(mix) + SRC_LPM_SETTING1 + (did / 8) * 0x4,
188 LPM_SETTING(did, 0x7), LPM_SETTING(did, lpm_mode));
189 }
190
src_mem_lpm_en(unsigned int mix,bool retn)191 static inline void src_mem_lpm_en(unsigned int mix, bool retn)
192 {
193 mmio_setbits_32(SRC_SLICE(mix) + SRC_MEM_CTRL, MEM_LP_EN | (retn ? MEM_LP_RETN : 0));
194 }
195
src_mem_lpm_dis(unsigned int mix)196 static inline void src_mem_lpm_dis(unsigned int mix)
197 {
198 mmio_clrbits_32(SRC_SLICE(mix) + SRC_MEM_CTRL, MEM_LP_EN | MEM_LP_RETN);
199 }
200
201 /*******************************************************************************
202 * BLK_CTRL_S definitions & declarations
203 ******************************************************************************/
204 #define HW_LP_HANDHSK U(0x110)
205 #define HW_LP_HANDHSK2 U(0x114)
206 #define CA55_CPUWAIT U(0x118)
207 #define CA55_RVBADDR0_L U(0x11c)
208 #define CA55_RVBADDR0_H U(0x120)
209
210 /*******************************************************************************
211 * Other definitions & declarations
212 ******************************************************************************/
213 void pwr_sys_init(void);
214
215 #endif /* PWR_CTRL_H */
216
217