1# 2# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. 3# Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4# 5# SPDX-License-Identifier: BSD-3-Clause 6# 7include lib/xlat_tables_v2/xlat_tables.mk 8PLAT_INCLUDES := \ 9 -Iplat/intel/soc/agilex5/include/ \ 10 -Iplat/intel/soc/common/drivers/ \ 11 -Iplat/intel/soc/common/include/ 12 13# GIC-600 configuration 14GICV3_SUPPORT_GIC600 := 1 15# Include GICv3 driver files 16include drivers/arm/gic/v3/gicv3.mk 17AGX5_GICv3_SOURCES := \ 18 ${GICV3_SOURCES} \ 19 plat/common/plat_gicv3.c 20 21PLAT_BL_COMMON_SOURCES := \ 22 ${AGX5_GICv3_SOURCES} \ 23 drivers/cadence/combo_phy/cdns_combo_phy.c \ 24 drivers/cadence/emmc/cdns_sdmmc.c \ 25 drivers/cadence/nand/cdns_nand.c \ 26 drivers/delay_timer/delay_timer.c \ 27 drivers/delay_timer/generic_delay_timer.c \ 28 drivers/ti/uart/aarch64/16550_console.S \ 29 plat/intel/soc/common/aarch64/platform_common.c \ 30 plat/intel/soc/common/aarch64/plat_helpers.S \ 31 plat/intel/soc/common/drivers/ccu/ncore_ccu.c \ 32 plat/intel/soc/common/drivers/combophy/combophy.c \ 33 plat/intel/soc/common/drivers/sdmmc/sdmmc.c \ 34 plat/intel/soc/common/drivers/ddr/ddr.c \ 35 plat/intel/soc/common/drivers/nand/nand.c \ 36 plat/intel/soc/common/socfpga_delay_timer.c 37 38BL2_SOURCES += \ 39 common/desc_image_load.c \ 40 lib/xlat_tables_v2/aarch64/enable_mmu.S \ 41 lib/xlat_tables_v2/xlat_tables_context.c \ 42 lib/xlat_tables_v2/xlat_tables_core.c \ 43 lib/xlat_tables_v2/aarch64/xlat_tables_arch.c \ 44 lib/xlat_tables_v2/xlat_tables_utils.c \ 45 drivers/mmc/mmc.c \ 46 drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ 47 drivers/io/io_storage.c \ 48 drivers/io/io_block.c \ 49 drivers/io/io_fip.c \ 50 drivers/io/io_mtd.c \ 51 drivers/partition/partition.c \ 52 drivers/partition/gpt.c \ 53 drivers/synopsys/emmc/dw_mmc.c \ 54 lib/cpus/aarch64/cortex_a55.S \ 55 lib/cpus/aarch64/cortex_a76.S \ 56 plat/intel/soc/agilex5/soc/agilex5_clock_manager.c \ 57 plat/intel/soc/agilex5/soc/agilex5_memory_controller.c \ 58 plat/intel/soc/agilex5/soc/agilex5_mmc.c \ 59 plat/intel/soc/agilex5/soc/agilex5_pinmux.c \ 60 plat/intel/soc/agilex5/soc/agilex5_power_manager.c \ 61 plat/intel/soc/common/bl2_plat_mem_params_desc.c \ 62 plat/intel/soc/common/socfpga_image_load.c \ 63 plat/intel/soc/common/socfpga_ros.c \ 64 plat/intel/soc/common/socfpga_storage.c \ 65 plat/intel/soc/common/socfpga_vab.c \ 66 plat/intel/soc/common/soc/socfpga_emac.c \ 67 plat/intel/soc/common/soc/socfpga_firewall.c \ 68 plat/intel/soc/common/soc/socfpga_handoff.c \ 69 plat/intel/soc/common/soc/socfpga_mailbox.c \ 70 plat/intel/soc/common/soc/socfpga_reset_manager.c \ 71 plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ 72 plat/intel/soc/agilex5/bl2_plat_setup.c \ 73 plat/intel/soc/common/drivers/wdt/watchdog.c 74 75include lib/zlib/zlib.mk 76PLAT_INCLUDES += -Ilib/zlib 77BL2_SOURCES += $(ZLIB_SOURCES) 78 79BL31_SOURCES += \ 80 drivers/arm/cci/cci.c \ 81 ${XLAT_TABLES_LIB_SRCS} \ 82 lib/cpus/aarch64/aem_generic.S \ 83 lib/cpus/aarch64/cortex_a55.S \ 84 lib/cpus/aarch64/cortex_a76.S \ 85 plat/common/plat_psci_common.c \ 86 plat/intel/soc/agilex5/bl31_plat_setup.c \ 87 plat/intel/soc/agilex5/soc/agilex5_clock_manager.c \ 88 plat/intel/soc/agilex5/soc/agilex5_power_manager.c \ 89 plat/intel/soc/common/socfpga_psci.c \ 90 plat/intel/soc/common/socfpga_sip_svc.c \ 91 plat/intel/soc/common/socfpga_sip_svc_v2.c \ 92 plat/intel/soc/common/socfpga_topology.c \ 93 plat/intel/soc/common/sip/socfpga_sip_ecc.c \ 94 plat/intel/soc/common/sip/socfpga_sip_fcs.c \ 95 plat/intel/soc/common/soc/socfpga_mailbox.c \ 96 plat/intel/soc/common/soc/socfpga_reset_manager.c 97 98# Configs for A76 and A55 99HW_ASSISTED_COHERENCY := 1 100USE_COHERENT_MEM := 0 101CTX_INCLUDE_AARCH32_REGS := 0 102ERRATA_A55_1530923 := 1 103 104# Don't have the Linux kernel as a BL33 image by default 105ARM_LINUX_KERNEL_AS_BL33 := 0 106$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33)) 107$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) 108$(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) 109 110PROGRAMMABLE_RESET_ADDRESS := 0 111RESET_TO_BL2 := 1 112BL2_INV_DCACHE := 0 113