1 /*
2 * Copyright (c) 2018-2023, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <inttypes.h>
8 #include <stdint.h>
9 #include <string.h>
10
11 #include <libfdt.h>
12
13 #include <platform_def.h>
14
15 #include <arch_helpers.h>
16 #include <bl1/bl1.h>
17 #include <common/bl_common.h>
18 #include <common/debug.h>
19 #include <common/desc_image_load.h>
20 #include <common/image_decompress.h>
21 #include <drivers/console.h>
22 #include <drivers/io/io_driver.h>
23 #include <drivers/io/io_storage.h>
24 #include <lib/mmio.h>
25 #include <lib/xlat_tables/xlat_tables_defs.h>
26 #include <plat/common/platform.h>
27 #if RCAR_GEN3_BL33_GZIP == 1
28 #include <tf_gunzip.h>
29 #endif
30
31 #include "avs_driver.h"
32 #include "boot_init_dram.h"
33 #include "cpg_registers.h"
34 #include "board.h"
35 #include "emmc_def.h"
36 #include "emmc_hal.h"
37 #include "emmc_std.h"
38
39 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
40 #include "iic_dvfs.h"
41 #endif
42
43 #include "io_common.h"
44 #include "io_rcar.h"
45 #include "qos_init.h"
46 #include "rcar_def.h"
47 #include "rcar_private.h"
48 #include "rcar_version.h"
49 #include "rom_api.h"
50
51 /*
52 * Following symbols are only used during plat_arch_setup()
53 */
54 static const uint64_t BL2_RO_BASE = BL_CODE_BASE;
55 static const uint64_t BL2_RO_LIMIT = BL_CODE_END;
56
57 #if USE_COHERENT_MEM
58 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
59 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
60 #endif
61
62 extern void plat_rcar_gic_driver_init(void);
63 extern void plat_rcar_gic_init(void);
64 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info);
65 extern void bl2_system_cpg_init(void);
66 extern void bl2_secure_setting(void);
67 extern void bl2_ram_security_setting_finish(void);
68 extern void bl2_cpg_init(void);
69 extern void rcar_io_emmc_setup(void);
70 extern void rcar_io_setup(void);
71 extern void rcar_swdt_release(void);
72 extern void rcar_swdt_init(void);
73 extern void rcar_rpc_init(void);
74 extern void rcar_pfc_init(void);
75 extern void rcar_dma_init(void);
76
77 static void bl2_init_generic_timer(void);
78
79 /* R-Car Gen3 product check */
80 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
81 #define TARGET_PRODUCT PRR_PRODUCT_H3
82 #define TARGET_NAME "R-Car H3"
83 #elif RCAR_LSI == RCAR_M3
84 #define TARGET_PRODUCT PRR_PRODUCT_M3
85 #define TARGET_NAME "R-Car M3"
86 #elif RCAR_LSI == RCAR_M3N
87 #define TARGET_PRODUCT PRR_PRODUCT_M3N
88 #define TARGET_NAME "R-Car M3N"
89 #elif RCAR_LSI == RCAR_V3M
90 #define TARGET_PRODUCT PRR_PRODUCT_V3M
91 #define TARGET_NAME "R-Car V3M"
92 #elif RCAR_LSI == RCAR_E3
93 #define TARGET_PRODUCT PRR_PRODUCT_E3
94 #define TARGET_NAME "R-Car E3"
95 #elif RCAR_LSI == RCAR_D3
96 #define TARGET_PRODUCT PRR_PRODUCT_D3
97 #define TARGET_NAME "R-Car D3"
98 #elif RCAR_LSI == RCAR_AUTO
99 #define TARGET_NAME "R-Car H3/M3/M3N/V3M"
100 #endif
101
102 #if (RCAR_LSI == RCAR_E3)
103 #define GPIO_INDT (GPIO_INDT6)
104 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U)
105 #else
106 #define GPIO_INDT (GPIO_INDT1)
107 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U)
108 #endif
109
110 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100)
111 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE),
112 assert_bl31_params_do_not_fit_in_shared_memory);
113
114 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
115
116 /* FDT with DRAM configuration */
117 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)];
118 static void *fdt = (void *)fdt_blob;
119
unsigned_num_print(unsigned long long int unum,unsigned int radix,char * string)120 static void unsigned_num_print(unsigned long long int unum, unsigned int radix,
121 char *string)
122 {
123 /* Just need enough space to store 64 bit decimal integer */
124 char num_buf[20];
125 int i = 0;
126 unsigned int rem;
127
128 do {
129 rem = unum % radix;
130 if (rem < 0xa)
131 num_buf[i] = '0' + rem;
132 else
133 num_buf[i] = 'a' + (rem - 0xa);
134 i++;
135 unum /= radix;
136 } while (unum > 0U);
137
138 while (--i >= 0)
139 *string++ = num_buf[i];
140 *string = 0;
141 }
142
143 #if (RCAR_LOSSY_ENABLE == 1)
144 typedef struct bl2_lossy_info {
145 uint32_t magic;
146 uint32_t a0;
147 uint32_t b0;
148 } bl2_lossy_info_t;
149
bl2_lossy_gen_fdt(uint32_t no,uint64_t start_addr,uint64_t end_addr,uint32_t format,uint32_t enable,int fcnlnode)150 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr,
151 uint64_t end_addr, uint32_t format,
152 uint32_t enable, int fcnlnode)
153 {
154 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr);
155 char nodename[40] = { 0 };
156 int ret, node;
157
158 /* Ignore undefined addresses */
159 if (start_addr == 0 && end_addr == 0)
160 return;
161
162 snprintf(nodename, sizeof(nodename), "lossy-decompression@");
163 unsigned_num_print(start_addr, 16, nodename + strlen(nodename));
164
165 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename);
166 if (ret < 0) {
167 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret);
168 panic();
169 }
170
171 ret = fdt_setprop_string(fdt, node, "compatible",
172 "renesas,lossy-decompression");
173 if (ret < 0) {
174 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret);
175 panic();
176 }
177
178 ret = fdt_appendprop_string(fdt, node, "compatible",
179 "shared-dma-pool");
180 if (ret < 0) {
181 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret);
182 panic();
183 }
184
185 ret = fdt_setprop_u64(fdt, node, "reg", start_addr);
186 if (ret < 0) {
187 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret);
188 panic();
189 }
190
191 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize));
192 if (ret < 0) {
193 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret);
194 panic();
195 }
196
197 ret = fdt_setprop(fdt, node, "no-map", NULL, 0);
198 if (ret < 0) {
199 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret);
200 panic();
201 }
202
203 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format);
204 if (ret < 0) {
205 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret);
206 panic();
207 }
208 }
209
bl2_lossy_setting(uint32_t no,uint64_t start_addr,uint64_t end_addr,uint32_t format,uint32_t enable,int fcnlnode)210 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr,
211 uint64_t end_addr, uint32_t format,
212 uint32_t enable, int fcnlnode)
213 {
214 bl2_lossy_info_t info;
215 uint32_t reg;
216
217 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode);
218
219 reg = format | (start_addr >> 20);
220 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg);
221 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20);
222 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable);
223
224 info.magic = 0x12345678U;
225 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no);
226 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no);
227
228 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic);
229 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0);
230 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0);
231
232 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no,
233 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no),
234 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no));
235 }
236
bl2_create_reserved_memory(void)237 static int bl2_create_reserved_memory(void)
238 {
239 int ret;
240
241 int fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory");
242 if (fcnlnode < 0) {
243 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n",
244 fcnlnode);
245 panic();
246 }
247
248 ret = fdt_setprop(fdt, fcnlnode, "ranges", NULL, 0);
249 if (ret < 0) {
250 NOTICE("BL2: Cannot add FCNL ranges prop (ret=%i)\n", ret);
251 panic();
252 }
253
254 ret = fdt_setprop_u32(fdt, fcnlnode, "#address-cells", 2);
255 if (ret < 0) {
256 NOTICE("BL2: Cannot add FCNL #address-cells prop (ret=%i)\n", ret);
257 panic();
258 }
259
260 ret = fdt_setprop_u32(fdt, fcnlnode, "#size-cells", 2);
261 if (ret < 0) {
262 NOTICE("BL2: Cannot add FCNL #size-cells prop (ret=%i)\n", ret);
263 panic();
264 }
265
266 return fcnlnode;
267 }
268
bl2_create_fcnl_reserved_memory(void)269 static void bl2_create_fcnl_reserved_memory(void)
270 {
271 int fcnlnode;
272
273 NOTICE("BL2: Lossy Decomp areas\n");
274
275 fcnlnode = bl2_create_reserved_memory();
276
277 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0,
278 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode);
279 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1,
280 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode);
281 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2,
282 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode);
283 }
284 #else
bl2_create_fcnl_reserved_memory(void)285 static void bl2_create_fcnl_reserved_memory(void) {}
286 #endif
287
bl2_plat_flush_bl31_params(void)288 void bl2_plat_flush_bl31_params(void)
289 {
290 uint32_t product_cut, product, cut;
291 uint32_t boot_dev, boot_cpu;
292 uint32_t lcs, reg, val;
293
294 reg = mmio_read_32(RCAR_MODEMR);
295 boot_dev = reg & MODEMR_BOOT_DEV_MASK;
296
297 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
298 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
299 emmc_terminate();
300
301 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7)
302 bl2_secure_setting();
303
304 reg = mmio_read_32(RCAR_PRR);
305 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
306 product = reg & PRR_PRODUCT_MASK;
307 cut = reg & PRR_CUT_MASK;
308
309 if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut)
310 goto tlb;
311
312 if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut)
313 goto tlb;
314
315 /* Disable MFIS write protection */
316 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1);
317
318 tlb:
319 reg = mmio_read_32(RCAR_MODEMR);
320 boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
321 if (boot_cpu != MODEMR_BOOT_CPU_CA57 &&
322 boot_cpu != MODEMR_BOOT_CPU_CA53)
323 goto mmu;
324
325 if (product_cut == PRR_PRODUCT_H3_CUT20) {
326 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
327 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE);
328 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
329 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE);
330 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE);
331 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE);
332 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
333 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) {
334 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
335 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
336 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) ||
337 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) {
338 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
339 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE);
340 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
341 }
342
343 if (product_cut == (PRR_PRODUCT_H3_CUT20) ||
344 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
345 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) ||
346 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) {
347 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE);
348 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE);
349 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE);
350
351 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE);
352 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE);
353 }
354
355 mmu:
356 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE);
357 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT);
358
359 val = rcar_rom_get_lcs(&lcs);
360 if (val) {
361 ERROR("BL2: Failed to get the LCS. (%d)\n", val);
362 panic();
363 }
364
365 if (lcs == LCS_SE)
366 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT);
367
368 rcar_swdt_release();
369 bl2_system_cpg_init();
370
371 /* Disable data cache (clean and invalidate) */
372 disable_mmu_el3();
373 #if RCAR_BL2_DCACHE == 1
374 dcsw_op_all(DCCISW);
375 #endif
376 tlbialle3();
377 disable_mmu_icache_el3();
378 plat_invalidate_icache();
379 dsbsy();
380 isb();
381 }
382
is_ddr_backup_mode(void)383 static uint32_t is_ddr_backup_mode(void)
384 {
385 #if RCAR_SYSTEM_SUSPEND
386 static uint32_t reason = RCAR_COLD_BOOT;
387 static uint32_t once;
388
389 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
390 uint8_t data;
391 #endif
392 if (once)
393 return reason;
394
395 once = 1;
396 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0)
397 return reason;
398
399 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
400 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) {
401 ERROR("BL2: REG Keep10 READ ERROR.\n");
402 panic();
403 }
404
405 if (KEEP10_MAGIC != data)
406 reason = RCAR_WARM_BOOT;
407 #else
408 reason = RCAR_WARM_BOOT;
409 #endif
410 return reason;
411 #else
412 return RCAR_COLD_BOOT;
413 #endif
414 }
415
416 #if RCAR_GEN3_BL33_GZIP == 1
bl2_plat_preload_setup(void)417 void bl2_plat_preload_setup(void)
418 {
419 image_decompress_init(BL33_COMP_BASE, BL33_COMP_SIZE, gunzip);
420 }
421 #endif
422
check_secure_load_area(uintptr_t base,uint32_t size,uintptr_t dest,uint32_t len)423 static uint64_t check_secure_load_area(uintptr_t base, uint32_t size,
424 uintptr_t dest, uint32_t len)
425 {
426 uintptr_t free_end, requested_end;
427
428 /*
429 * Handle corner cases first.
430 *
431 * The order of the 2 tests is important, because if there's no space
432 * left (i.e. free_size == 0) but we don't ask for any memory
433 * (i.e. size == 0) then we should report that the memory is free.
434 */
435 if (len == 0U) {
436 WARN("BL2: load data size is zero\n");
437 return 0; /* A zero-byte region is always free */
438 }
439 if (size == 0U) {
440 goto err;
441 }
442
443 /*
444 * Check that the end addresses don't overflow.
445 * If they do, consider that this memory region is not free, as this
446 * is an invalid scenario.
447 */
448 if (check_uptr_overflow(base, size - 1U)) {
449 goto err;
450 }
451 free_end = base + (size - 1U);
452
453 if (check_uptr_overflow(dest, len - 1U)) {
454 goto err;
455 }
456 requested_end = dest + (len - 1U);
457
458 /*
459 * Finally, check that the requested memory region lies within the free
460 * region.
461 */
462 if ((dest < base) || (requested_end > free_end)) {
463 goto err;
464 }
465
466 return 0;
467
468 err:
469 ERROR("BL2: load data is outside the loadable area.\n");
470 ERROR("BL2: dst=0x%lx, len=%d(0x%x)\n", dest, len, len);
471 return 1;
472 }
473
rcar_get_dest_addr_from_cert(uint32_t certid,uintptr_t * dest,uint32_t * len)474 static uint64_t rcar_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest,
475 uint32_t *len)
476 {
477 uint32_t cert;
478 int ret;
479
480 ret = rcar_get_certificate(certid, &cert);
481 if (ret) {
482 ERROR("%s : cert file load error", __func__);
483 return 1;
484 }
485
486 rcar_read_certificate((uint64_t) cert, len, dest);
487
488 return 0;
489 }
490
bl2_plat_handle_pre_image_load(unsigned int image_id)491 int bl2_plat_handle_pre_image_load(unsigned int image_id)
492 {
493 u_register_t *boot_kind = (void *) BOOT_KIND_BASE;
494 bl_mem_params_node_t *bl_mem_params;
495 uintptr_t dev_handle;
496 uintptr_t image_spec;
497 uintptr_t dest;
498 uint32_t len;
499 uint64_t ui64_ret;
500 int iret;
501
502 bl_mem_params = get_bl_mem_params_node(image_id);
503 if (bl_mem_params == NULL) {
504 ERROR("BL2: Failed to get loading parameter.\n");
505 return 1;
506 }
507
508 switch (image_id) {
509 case BL31_IMAGE_ID:
510 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) {
511 iret = plat_get_image_source(image_id, &dev_handle,
512 &image_spec);
513 if (iret != 0) {
514 return 1;
515 }
516
517 ui64_ret = rcar_get_dest_addr_from_cert(
518 SOC_FW_CONTENT_CERT_ID, &dest, &len);
519 if (ui64_ret != 0U) {
520 return 1;
521 }
522
523 ui64_ret = check_secure_load_area(
524 BL31_BASE, BL31_LIMIT - BL31_BASE,
525 dest, len);
526 if (ui64_ret != 0U) {
527 return 1;
528 }
529
530 *boot_kind = RCAR_COLD_BOOT;
531 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
532
533 bl_mem_params->image_info.image_base = dest;
534 bl_mem_params->image_info.image_size = len;
535 } else {
536 *boot_kind = RCAR_WARM_BOOT;
537 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
538
539 console_flush();
540 bl2_plat_flush_bl31_params();
541
542 /* will not return */
543 bl2_enter_bl31(&bl_mem_params->ep_info);
544 }
545
546 return 0;
547 #ifndef SPD_NONE
548 case BL32_IMAGE_ID:
549 ui64_ret = rcar_get_dest_addr_from_cert(
550 TRUSTED_OS_FW_CONTENT_CERT_ID, &dest, &len);
551 if (ui64_ret != 0U) {
552 return 1;
553 }
554
555 ui64_ret = check_secure_load_area(
556 BL32_BASE, BL32_LIMIT - BL32_BASE, dest, len);
557 if (ui64_ret != 0U) {
558 return 1;
559 }
560
561 bl_mem_params->image_info.image_base = dest;
562 bl_mem_params->image_info.image_size = len;
563
564 return 0;
565 #endif
566 case BL33_IMAGE_ID:
567 /* case of image_id == BL33_IMAGE_ID */
568 ui64_ret = rcar_get_dest_addr_from_cert(
569 NON_TRUSTED_FW_CONTENT_CERT_ID,
570 &dest, &len);
571
572 if (ui64_ret != 0U) {
573 return 1;
574 }
575
576 #if RCAR_GEN3_BL33_GZIP == 1
577 image_decompress_prepare(&bl_mem_params->image_info);
578 #endif
579
580 return 0;
581 default:
582 return 1;
583 }
584
585 return 0;
586 }
587
bl2_plat_handle_post_image_load(unsigned int image_id)588 int bl2_plat_handle_post_image_load(unsigned int image_id)
589 {
590 static bl2_to_bl31_params_mem_t *params;
591 bl_mem_params_node_t *bl_mem_params;
592
593 if (!params) {
594 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE;
595 memset((void *)PARAMS_BASE, 0, sizeof(*params));
596 }
597
598 bl_mem_params = get_bl_mem_params_node(image_id);
599 if (!bl_mem_params) {
600 ERROR("BL2: Failed to get loading parameter.\n");
601 return 1;
602 }
603
604 switch (image_id) {
605 case BL31_IMAGE_ID:
606 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
607 return 0;
608 case BL32_IMAGE_ID:
609 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
610 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info,
611 sizeof(entry_point_info_t));
612 return 0;
613 case BL33_IMAGE_ID:
614 #if RCAR_GEN3_BL33_GZIP == 1
615 int ret;
616 if ((mmio_read_32(BL33_COMP_BASE) & 0xffff) == 0x8b1f) {
617 /* decompress gzip-compressed image */
618 ret = image_decompress(&bl_mem_params->image_info);
619 if (ret != 0) {
620 return ret;
621 }
622 } else {
623 /* plain image, copy it in place */
624 memcpy((void *)BL33_BASE, (void *)BL33_COMP_BASE,
625 bl_mem_params->image_info.image_size);
626 }
627 #endif
628 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info,
629 sizeof(entry_point_info_t));
630 return 0;
631 default:
632 return 1;
633 }
634
635 return 0;
636 }
637
bl2_plat_sec_mem_layout(void)638 struct meminfo *bl2_plat_sec_mem_layout(void)
639 {
640 return &bl2_tzram_layout;
641 }
642
bl2_populate_compatible_string(void * dt)643 static void bl2_populate_compatible_string(void *dt)
644 {
645 uint32_t board_type;
646 uint32_t board_rev;
647 uint32_t reg;
648 int ret;
649
650 fdt_setprop_u32(dt, 0, "#address-cells", 2);
651 fdt_setprop_u32(dt, 0, "#size-cells", 2);
652
653 /* Populate compatible string */
654 rcar_get_board_type(&board_type, &board_rev);
655 switch (board_type) {
656 case BOARD_SALVATOR_X:
657 ret = fdt_setprop_string(dt, 0, "compatible",
658 "renesas,salvator-x");
659 break;
660 case BOARD_SALVATOR_XS:
661 ret = fdt_setprop_string(dt, 0, "compatible",
662 "renesas,salvator-xs");
663 break;
664 case BOARD_STARTER_KIT:
665 ret = fdt_setprop_string(dt, 0, "compatible",
666 "renesas,m3ulcb");
667 break;
668 case BOARD_STARTER_KIT_PRE:
669 ret = fdt_setprop_string(dt, 0, "compatible",
670 "renesas,h3ulcb");
671 break;
672 case BOARD_EAGLE:
673 ret = fdt_setprop_string(dt, 0, "compatible",
674 "renesas,eagle");
675 break;
676 case BOARD_EBISU:
677 case BOARD_EBISU_4D:
678 ret = fdt_setprop_string(dt, 0, "compatible",
679 "renesas,ebisu");
680 break;
681 case BOARD_DRAAK:
682 ret = fdt_setprop_string(dt, 0, "compatible",
683 "renesas,draak");
684 break;
685 default:
686 NOTICE("BL2: Cannot set compatible string, board unsupported\n");
687 panic();
688 }
689
690 if (ret < 0) {
691 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
692 panic();
693 }
694
695 reg = mmio_read_32(RCAR_PRR);
696 switch (reg & PRR_PRODUCT_MASK) {
697 case PRR_PRODUCT_H3:
698 ret = fdt_appendprop_string(dt, 0, "compatible",
699 "renesas,r8a7795");
700 break;
701 case PRR_PRODUCT_M3:
702 ret = fdt_appendprop_string(dt, 0, "compatible",
703 "renesas,r8a7796");
704 break;
705 case PRR_PRODUCT_M3N:
706 ret = fdt_appendprop_string(dt, 0, "compatible",
707 "renesas,r8a77965");
708 break;
709 case PRR_PRODUCT_V3M:
710 ret = fdt_appendprop_string(dt, 0, "compatible",
711 "renesas,r8a77970");
712 break;
713 case PRR_PRODUCT_E3:
714 ret = fdt_appendprop_string(dt, 0, "compatible",
715 "renesas,r8a77990");
716 break;
717 case PRR_PRODUCT_D3:
718 ret = fdt_appendprop_string(dt, 0, "compatible",
719 "renesas,r8a77995");
720 break;
721 default:
722 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n");
723 panic();
724 }
725
726 if (ret < 0) {
727 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
728 panic();
729 }
730 }
731
bl2_add_rpc_node(void)732 static void bl2_add_rpc_node(void)
733 {
734 #if (RCAR_RPC_HYPERFLASH_LOCKED == 0)
735 int ret, node;
736
737 node = ret = fdt_add_subnode(fdt, 0, "soc");
738 if (ret < 0) {
739 goto err;
740 }
741
742 node = ret = fdt_add_subnode(fdt, node, "spi@ee200000");
743 if (ret < 0) {
744 goto err;
745 }
746
747 ret = fdt_setprop_string(fdt, node, "status", "okay");
748 if (ret < 0) {
749 goto err;
750 }
751
752 return;
753 err:
754 NOTICE("BL2: Cannot add RPC node to FDT (ret=%i)\n", ret);
755 panic();
756 #endif
757 }
758
bl2_add_dram_entry(uint64_t start,uint64_t size)759 static void bl2_add_dram_entry(uint64_t start, uint64_t size)
760 {
761 char nodename[32] = { 0 };
762 uint64_t fdtsize;
763 int ret, node;
764
765 fdtsize = cpu_to_fdt64(size);
766
767 snprintf(nodename, sizeof(nodename), "memory@");
768 unsigned_num_print(start, 16, nodename + strlen(nodename));
769 node = ret = fdt_add_subnode(fdt, 0, nodename);
770 if (ret < 0) {
771 goto err;
772 }
773
774 ret = fdt_setprop_string(fdt, node, "device_type", "memory");
775 if (ret < 0) {
776 goto err;
777 }
778
779 ret = fdt_setprop_u64(fdt, node, "reg", start);
780 if (ret < 0) {
781 goto err;
782 }
783
784 ret = fdt_appendprop(fdt, node, "reg", &fdtsize,
785 sizeof(fdtsize));
786 if (ret < 0) {
787 goto err;
788 }
789
790 return;
791 err:
792 NOTICE("BL2: Cannot add memory node [%" PRIx64 " - %" PRIx64 "] to FDT (ret=%i)\n",
793 start, start + size - 1, ret);
794 panic();
795 }
796
bl2_advertise_dram_entries(uint64_t dram_config[8])797 static void bl2_advertise_dram_entries(uint64_t dram_config[8])
798 {
799 uint64_t start, size, size32;
800 int chan;
801
802 for (chan = 0; chan < 4; chan++) {
803 start = dram_config[2 * chan];
804 size = dram_config[2 * chan + 1];
805 if (!size)
806 continue;
807
808 NOTICE("BL2: CH%d: %" PRIx64 " - %" PRIx64 ", %" PRId64 " %siB\n",
809 chan, start, start + size - 1,
810 (size >> 30) ? : size >> 20,
811 (size >> 30) ? "G" : "M");
812 }
813
814 /*
815 * We add the DT nodes in reverse order here. The fdt_add_subnode()
816 * adds the DT node before the first existing DT node, so we have
817 * to add them in reverse order to get nodes sorted by address in
818 * the resulting DT.
819 */
820 for (chan = 3; chan >= 0; chan--) {
821 start = dram_config[2 * chan];
822 size = dram_config[2 * chan + 1];
823 if (!size)
824 continue;
825
826 /*
827 * Channel 0 is mapped in 32bit space and the first
828 * 128 MiB are reserved and the maximum size is 2GiB.
829 */
830 if (chan == 0) {
831 /* Limit the 32bit entry to 2 GiB - 128 MiB */
832 size32 = size - 0x8000000U;
833 if (size32 >= 0x78000000U) {
834 size32 = 0x78000000U;
835 }
836
837 /* Emit 32bit entry, up to 2 GiB - 128 MiB long. */
838 bl2_add_dram_entry(0x48000000, size32);
839
840 /*
841 * If channel 0 is less than 2 GiB long, the
842 * entire memory fits into the 32bit space entry,
843 * so move on to the next channel.
844 */
845 if (size <= 0x80000000U) {
846 continue;
847 }
848
849 /*
850 * If channel 0 is more than 2 GiB long, emit
851 * another entry which covers the rest of the
852 * memory in channel 0, in the 64bit space.
853 *
854 * Start of this new entry is at 2 GiB offset
855 * from the beginning of the 64bit channel 0
856 * address, size is 2 GiB shorter than total
857 * size of the channel.
858 */
859 start += 0x80000000U;
860 size -= 0x80000000U;
861 }
862
863 bl2_add_dram_entry(start, size);
864 }
865 }
866
bl2_advertise_dram_size(uint32_t product)867 static void bl2_advertise_dram_size(uint32_t product)
868 {
869 uint64_t dram_config[8] = {
870 [0] = 0x400000000ULL,
871 [2] = 0x500000000ULL,
872 [4] = 0x600000000ULL,
873 [6] = 0x700000000ULL,
874 };
875 uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
876
877 switch (product) {
878 case PRR_PRODUCT_H3:
879 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
880 /* 4GB(1GBx4) */
881 dram_config[1] = 0x40000000ULL;
882 dram_config[3] = 0x40000000ULL;
883 dram_config[5] = 0x40000000ULL;
884 dram_config[7] = 0x40000000ULL;
885 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \
886 (RCAR_DRAM_CHANNEL == 5) && \
887 (RCAR_DRAM_SPLIT == 2)
888 /* 4GB(2GBx2 2ch split) */
889 dram_config[1] = 0x80000000ULL;
890 dram_config[3] = 0x80000000ULL;
891 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15)
892 /* 8GB(2GBx4: default) */
893 dram_config[1] = 0x80000000ULL;
894 dram_config[3] = 0x80000000ULL;
895 dram_config[5] = 0x80000000ULL;
896 dram_config[7] = 0x80000000ULL;
897 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */
898 break;
899
900 case PRR_PRODUCT_M3:
901 if (cut < PRR_PRODUCT_30) {
902 #if (RCAR_GEN3_ULCB == 1)
903 /* 2GB(1GBx2 2ch split) */
904 dram_config[1] = 0x40000000ULL;
905 dram_config[5] = 0x40000000ULL;
906 #else
907 /* 4GB(2GBx2 2ch split) */
908 dram_config[1] = 0x80000000ULL;
909 dram_config[5] = 0x80000000ULL;
910 #endif
911 } else {
912 /* 8GB(2GBx4 2ch split) */
913 dram_config[1] = 0x100000000ULL;
914 dram_config[5] = 0x100000000ULL;
915 }
916 break;
917
918 case PRR_PRODUCT_M3N:
919 #if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
920 /* 4GB(4GBx1) */
921 dram_config[1] = 0x100000000ULL;
922 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1)
923 /* 2GB(1GBx2) */
924 dram_config[1] = 0x80000000ULL;
925 #endif
926 break;
927
928 case PRR_PRODUCT_V3M:
929 /* 1GB(512MBx2) */
930 dram_config[1] = 0x40000000ULL;
931 break;
932
933 case PRR_PRODUCT_E3:
934 #if (RCAR_DRAM_DDR3L_MEMCONF == 0)
935 /* 1GB(512MBx2) */
936 dram_config[1] = 0x40000000ULL;
937 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1)
938 /* 2GB(512MBx4) */
939 dram_config[1] = 0x80000000ULL;
940 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2)
941 /* 4GB(1GBx4) */
942 dram_config[1] = 0x100000000ULL;
943 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */
944 break;
945
946 case PRR_PRODUCT_D3:
947 /* 512MB */
948 dram_config[1] = 0x20000000ULL;
949 break;
950 }
951
952 bl2_advertise_dram_entries(dram_config);
953 }
954
bl2_el3_early_platform_setup(u_register_t arg1,u_register_t arg2,u_register_t arg3,u_register_t arg4)955 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
956 u_register_t arg3, u_register_t arg4)
957 {
958 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev;
959 uint32_t product, product_cut, major, minor;
960 int32_t ret;
961 const char *str;
962 const char *unknown = "unknown";
963 const char *cpu_ca57 = "CA57";
964 const char *cpu_ca53 = "CA53";
965 const char *product_m3n = "M3N";
966 const char *product_h3 = "H3";
967 const char *product_m3 = "M3";
968 const char *product_e3 = "E3";
969 const char *product_d3 = "D3";
970 const char *product_v3m = "V3M";
971 const char *lcs_secure = "SE";
972 const char *lcs_cm = "CM";
973 const char *lcs_dm = "DM";
974 const char *lcs_sd = "SD";
975 const char *lcs_fa = "FA";
976 const char *sscg_off = "PLL1 nonSSCG Clock select";
977 const char *sscg_on = "PLL1 SSCG Clock select";
978 const char *boot_hyper80 = "HyperFlash(80MHz)";
979 const char *boot_qspi40 = "QSPI Flash(40MHz)";
980 const char *boot_qspi80 = "QSPI Flash(80MHz)";
981 const char *boot_emmc25x1 = "eMMC(25MHz x1)";
982 const char *boot_emmc50x8 = "eMMC(50MHz x8)";
983 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
984 const char *boot_hyper160 = "HyperFlash(150MHz)";
985 #else
986 const char *boot_hyper160 = "HyperFlash(160MHz)";
987 #endif
988
989 bl2_init_generic_timer();
990
991 reg = mmio_read_32(RCAR_MODEMR);
992 boot_dev = reg & MODEMR_BOOT_DEV_MASK;
993 boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
994
995 bl2_cpg_init();
996
997 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
998 boot_cpu == MODEMR_BOOT_CPU_CA53) {
999 rcar_pfc_init();
1000 rcar_console_boot_init();
1001 }
1002
1003 plat_rcar_gic_driver_init();
1004 plat_rcar_gic_init();
1005 rcar_swdt_init();
1006
1007 /* FIQ interrupts are taken to EL3 */
1008 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
1009
1010 write_daifclr(DAIF_FIQ_BIT);
1011
1012 reg = read_midr();
1013 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT);
1014 switch (midr) {
1015 case MIDR_CA57:
1016 str = cpu_ca57;
1017 break;
1018 case MIDR_CA53:
1019 str = cpu_ca53;
1020 break;
1021 default:
1022 str = unknown;
1023 break;
1024 }
1025
1026 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str,
1027 version_of_renesas);
1028
1029 reg = mmio_read_32(RCAR_PRR);
1030 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
1031 product = reg & PRR_PRODUCT_MASK;
1032
1033 switch (product) {
1034 case PRR_PRODUCT_H3:
1035 str = product_h3;
1036 break;
1037 case PRR_PRODUCT_M3:
1038 str = product_m3;
1039 break;
1040 case PRR_PRODUCT_M3N:
1041 str = product_m3n;
1042 break;
1043 case PRR_PRODUCT_V3M:
1044 str = product_v3m;
1045 break;
1046 case PRR_PRODUCT_E3:
1047 str = product_e3;
1048 break;
1049 case PRR_PRODUCT_D3:
1050 str = product_d3;
1051 break;
1052 default:
1053 str = unknown;
1054 break;
1055 }
1056
1057 if ((PRR_PRODUCT_M3 == product) &&
1058 (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) {
1059 if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) {
1060 /* M3 Ver.1.1 or Ver.1.2 */
1061 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n",
1062 str);
1063 } else {
1064 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n",
1065 str,
1066 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET);
1067 }
1068 } else if (product == PRR_PRODUCT_D3) {
1069 if (RCAR_D3_CUT_VER10 == (reg & PRR_CUT_MASK)) {
1070 NOTICE("BL2: PRR is R-Car %s Ver.1.0\n", str);
1071 } else if (RCAR_D3_CUT_VER11 == (reg & PRR_CUT_MASK)) {
1072 NOTICE("BL2: PRR is R-Car %s Ver.1.1\n", str);
1073 } else {
1074 NOTICE("BL2: PRR is R-Car %s Ver.X.X\n", str);
1075 }
1076 } else {
1077 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT;
1078 major = major + RCAR_MAJOR_OFFSET;
1079 minor = reg & RCAR_MINOR_MASK;
1080 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor);
1081 }
1082
1083 if (PRR_PRODUCT_E3 == product || PRR_PRODUCT_D3 == product) {
1084 reg = mmio_read_32(RCAR_MODEMR);
1085 sscg = reg & RCAR_SSCG_MASK;
1086 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
1087 NOTICE("BL2: %s\n", str);
1088 }
1089
1090 rcar_get_board_type(&type, &rev);
1091
1092 switch (type) {
1093 case BOARD_SALVATOR_X:
1094 case BOARD_KRIEK:
1095 case BOARD_STARTER_KIT:
1096 case BOARD_SALVATOR_XS:
1097 case BOARD_EBISU:
1098 case BOARD_STARTER_KIT_PRE:
1099 case BOARD_EBISU_4D:
1100 case BOARD_DRAAK:
1101 case BOARD_EAGLE:
1102 break;
1103 default:
1104 type = BOARD_UNKNOWN;
1105 break;
1106 }
1107
1108 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN)
1109 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type));
1110 else {
1111 NOTICE("BL2: Board is %s Rev.%d.%d\n",
1112 GET_BOARD_NAME(type),
1113 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev));
1114 }
1115
1116 #if RCAR_LSI != RCAR_AUTO
1117 if (product != TARGET_PRODUCT) {
1118 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME);
1119 ERROR("BL2: Please write the correct IPL to flash memory.\n");
1120 panic();
1121 }
1122 #endif
1123 rcar_avs_init();
1124 rcar_avs_setting();
1125
1126 switch (boot_dev) {
1127 case MODEMR_BOOT_DEV_HYPERFLASH160:
1128 str = boot_hyper160;
1129 break;
1130 case MODEMR_BOOT_DEV_HYPERFLASH80:
1131 str = boot_hyper80;
1132 break;
1133 case MODEMR_BOOT_DEV_QSPI_FLASH40:
1134 str = boot_qspi40;
1135 break;
1136 case MODEMR_BOOT_DEV_QSPI_FLASH80:
1137 str = boot_qspi80;
1138 break;
1139 case MODEMR_BOOT_DEV_EMMC_25X1:
1140 #if RCAR_LSI == RCAR_D3
1141 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n");
1142 panic();
1143 #endif
1144 str = boot_emmc25x1;
1145 break;
1146 case MODEMR_BOOT_DEV_EMMC_50X8:
1147 str = boot_emmc50x8;
1148 break;
1149 default:
1150 str = unknown;
1151 break;
1152 }
1153 NOTICE("BL2: Boot device is %s\n", str);
1154
1155 rcar_avs_setting();
1156 reg = rcar_rom_get_lcs(&lcs);
1157 if (reg) {
1158 str = unknown;
1159 goto lcm_state;
1160 }
1161
1162 switch (lcs) {
1163 case LCS_CM:
1164 str = lcs_cm;
1165 break;
1166 case LCS_DM:
1167 str = lcs_dm;
1168 break;
1169 case LCS_SD:
1170 str = lcs_sd;
1171 break;
1172 case LCS_SE:
1173 str = lcs_secure;
1174 break;
1175 case LCS_FA:
1176 str = lcs_fa;
1177 break;
1178 default:
1179 str = unknown;
1180 break;
1181 }
1182
1183 lcm_state:
1184 NOTICE("BL2: LCM state is %s\n", str);
1185
1186 rcar_avs_end();
1187 is_ddr_backup_mode();
1188
1189 bl2_tzram_layout.total_base = BL31_BASE;
1190 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE;
1191
1192 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
1193 boot_cpu == MODEMR_BOOT_CPU_CA53) {
1194 ret = rcar_dram_init();
1195 if (ret) {
1196 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret);
1197 panic();
1198 }
1199 rcar_qos_init();
1200 }
1201
1202 /* Set up FDT */
1203 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob));
1204 if (ret) {
1205 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret);
1206 panic();
1207 }
1208
1209 /* Add platform compatible string */
1210 bl2_populate_compatible_string(fdt);
1211
1212 /* Enable RPC if unlocked */
1213 bl2_add_rpc_node();
1214
1215 /* Print DRAM layout */
1216 bl2_advertise_dram_size(product);
1217
1218 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
1219 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) {
1220 if (rcar_emmc_init() != EMMC_SUCCESS) {
1221 NOTICE("BL2: Failed to eMMC driver initialize.\n");
1222 panic();
1223 }
1224 rcar_emmc_memcard_power(EMMC_POWER_ON);
1225 if (rcar_emmc_mount() != EMMC_SUCCESS) {
1226 NOTICE("BL2: Failed to eMMC mount operation.\n");
1227 panic();
1228 }
1229 } else {
1230 rcar_rpc_init();
1231 rcar_dma_init();
1232 }
1233
1234 reg = mmio_read_32(RST_WDTRSTCR);
1235 reg &= ~WDTRSTCR_RWDT_RSTMSK;
1236 reg |= WDTRSTCR_PASSWORD;
1237 mmio_write_32(RST_WDTRSTCR, reg);
1238
1239 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD);
1240 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD);
1241
1242 reg = mmio_read_32(RCAR_PRR);
1243 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57)
1244 mmio_write_32(CPG_CA57DBGRCR,
1245 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR));
1246
1247 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53)
1248 mmio_write_32(CPG_CA53DBGRCR,
1249 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR));
1250
1251 if (product_cut == PRR_PRODUCT_H3_CUT10) {
1252 reg = mmio_read_32(CPG_PLL2CR);
1253 reg &= ~((uint32_t) 1 << 5);
1254 mmio_write_32(CPG_PLL2CR, reg);
1255
1256 reg = mmio_read_32(CPG_PLL4CR);
1257 reg &= ~((uint32_t) 1 << 5);
1258 mmio_write_32(CPG_PLL4CR, reg);
1259
1260 reg = mmio_read_32(CPG_PLL0CR);
1261 reg &= ~((uint32_t) 1 << 12);
1262 mmio_write_32(CPG_PLL0CR, reg);
1263 }
1264
1265 bl2_create_fcnl_reserved_memory();
1266
1267 fdt_pack(fdt);
1268 NOTICE("BL2: FDT at %p\n", fdt);
1269
1270 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
1271 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
1272 rcar_io_emmc_setup();
1273 else
1274 rcar_io_setup();
1275 }
1276
bl2_el3_plat_arch_setup(void)1277 void bl2_el3_plat_arch_setup(void)
1278 {
1279 rcar_configure_mmu_el3(BL2_BASE,
1280 BL2_END - BL2_BASE,
1281 BL2_RO_BASE, BL2_RO_LIMIT
1282 #if USE_COHERENT_MEM
1283 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT
1284 #endif
1285 );
1286 }
1287
bl2_el3_plat_prepare_exit(void)1288 void bl2_el3_plat_prepare_exit(void)
1289 {
1290 bl2_ram_security_setting_finish();
1291 }
1292
bl2_platform_setup(void)1293 void bl2_platform_setup(void)
1294 {
1295
1296 }
1297
bl2_init_generic_timer(void)1298 static void bl2_init_generic_timer(void)
1299 {
1300 /* FIXME: V3M 16.666 MHz ? */
1301 #if RCAR_LSI == RCAR_D3
1302 uint32_t reg_cntfid = EXTAL_DRAAK;
1303 #elif RCAR_LSI == RCAR_E3
1304 uint32_t reg_cntfid = EXTAL_EBISU;
1305 #else /* RCAR_LSI == RCAR_E3 */
1306 uint32_t reg;
1307 uint32_t reg_cntfid;
1308 uint32_t modemr;
1309 uint32_t modemr_pll;
1310 uint32_t board_type;
1311 uint32_t board_rev;
1312 uint32_t pll_table[] = {
1313 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */
1314 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */
1315 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */
1316 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */
1317 };
1318
1319 modemr = mmio_read_32(RCAR_MODEMR);
1320 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK);
1321
1322 /* Set frequency data in CNTFID0 */
1323 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
1324 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
1325 switch (modemr_pll) {
1326 case MD14_MD13_TYPE_0:
1327 rcar_get_board_type(&board_type, &board_rev);
1328 if (BOARD_SALVATOR_XS == board_type) {
1329 reg_cntfid = EXTAL_SALVATOR_XS;
1330 }
1331 break;
1332 case MD14_MD13_TYPE_3:
1333 if (PRR_PRODUCT_H3_CUT10 == reg) {
1334 reg_cntfid = reg_cntfid >> 1U;
1335 }
1336 break;
1337 default:
1338 /* none */
1339 break;
1340 }
1341 #endif /* RCAR_LSI == RCAR_E3 */
1342 /* Update memory mapped and register based frequency */
1343 write_cntfrq_el0((u_register_t )reg_cntfid);
1344 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid);
1345 /* Enable counter */
1346 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF,
1347 (uint32_t)CNTCR_EN);
1348 }
1349