1 /*
2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <string.h>
10
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <common/desc_image_load.h>
15 #include <drivers/generic_delay_timer.h>
16 #include <drivers/mmc.h>
17 #include <drivers/st/bsec.h>
18 #include <drivers/st/regulator_fixed.h>
19 #include <drivers/st/stm32_iwdg.h>
20 #include <drivers/st/stm32_rng.h>
21 #include <drivers/st/stm32_uart.h>
22 #include <drivers/st/stm32mp1_clk.h>
23 #include <drivers/st/stm32mp1_pwr.h>
24 #include <drivers/st/stm32mp1_ram.h>
25 #include <drivers/st/stm32mp_pmic.h>
26 #include <lib/fconf/fconf.h>
27 #include <lib/fconf/fconf_dyn_cfg_getter.h>
28 #include <lib/mmio.h>
29 #include <lib/optee_utils.h>
30 #include <lib/xlat_tables/xlat_tables_v2.h>
31 #include <plat/common/platform.h>
32
33 #include <platform_def.h>
34 #include <stm32mp_common.h>
35 #include <stm32mp1_dbgmcu.h>
36
37 #if DEBUG
38 static const char debug_msg[] = {
39 "***************************************************\n"
40 "** DEBUG ACCESS PORT IS OPEN! **\n"
41 "** This boot image is only for debugging purpose **\n"
42 "** and is unsafe for production use. **\n"
43 "** **\n"
44 "** If you see this message and you are not **\n"
45 "** debugging report this immediately to your **\n"
46 "** vendor! **\n"
47 "***************************************************\n"
48 };
49 #endif
50
print_reset_reason(void)51 static void print_reset_reason(void)
52 {
53 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
54
55 if (rstsr == 0U) {
56 WARN("Reset reason unknown\n");
57 return;
58 }
59
60 INFO("Reset reason (0x%x):\n", rstsr);
61
62 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
63 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
64 INFO("System exits from STANDBY\n");
65 return;
66 }
67
68 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
69 INFO("MPU exits from CSTANDBY\n");
70 return;
71 }
72 }
73
74 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
75 INFO(" Power-on Reset (rst_por)\n");
76 return;
77 }
78
79 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
80 INFO(" Brownout Reset (rst_bor)\n");
81 return;
82 }
83
84 #if STM32MP15
85 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
86 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
87 INFO(" System reset generated by MCU (MCSYSRST)\n");
88 } else {
89 INFO(" Local reset generated by MCU (MCSYSRST)\n");
90 }
91 return;
92 }
93 #endif
94
95 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
96 INFO(" System reset generated by MPU (MPSYSRST)\n");
97 return;
98 }
99
100 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
101 INFO(" Reset due to a clock failure on HSE\n");
102 return;
103 }
104
105 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
106 INFO(" IWDG1 Reset (rst_iwdg1)\n");
107 return;
108 }
109
110 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
111 INFO(" IWDG2 Reset (rst_iwdg2)\n");
112 return;
113 }
114
115 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) {
116 INFO(" MPU Processor 0 Reset\n");
117 return;
118 }
119
120 #if STM32MP15
121 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
122 INFO(" MPU Processor 1 Reset\n");
123 return;
124 }
125 #endif
126
127 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
128 INFO(" Pad Reset from NRST\n");
129 return;
130 }
131
132 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
133 INFO(" Reset due to a failure of VDD_CORE\n");
134 return;
135 }
136
137 ERROR(" Unidentified reset reason\n");
138 }
139
bl2_el3_early_platform_setup(u_register_t arg0,u_register_t arg1 __unused,u_register_t arg2 __unused,u_register_t arg3 __unused)140 void bl2_el3_early_platform_setup(u_register_t arg0,
141 u_register_t arg1 __unused,
142 u_register_t arg2 __unused,
143 u_register_t arg3 __unused)
144 {
145 stm32mp_save_boot_ctx_address(arg0);
146 }
147
bl2_platform_setup(void)148 void bl2_platform_setup(void)
149 {
150 int ret;
151
152 ret = stm32mp1_ddr_probe();
153 if (ret < 0) {
154 ERROR("Invalid DDR init: error %d\n", ret);
155 panic();
156 }
157
158 /* Map DDR for binary load, now with cacheable attribute */
159 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
160 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE);
161 if (ret < 0) {
162 ERROR("DDR mapping: error %d\n", ret);
163 panic();
164 }
165 }
166
167 #if STM32MP15
update_monotonic_counter(void)168 static void update_monotonic_counter(void)
169 {
170 uint32_t version;
171 uint32_t otp;
172
173 CASSERT(STM32_TF_VERSION <= MAX_MONOTONIC_VALUE,
174 assert_stm32mp1_monotonic_counter_reach_max);
175
176 /* Check if monotonic counter needs to be incremented */
177 if (stm32_get_otp_index(MONOTONIC_OTP, &otp, NULL) != 0) {
178 panic();
179 }
180
181 if (stm32_get_otp_value_from_idx(otp, &version) != 0) {
182 panic();
183 }
184
185 if ((version + 1U) < BIT(STM32_TF_VERSION)) {
186 uint32_t result;
187
188 /* Need to increment the monotonic counter. */
189 version = BIT(STM32_TF_VERSION) - 1U;
190
191 result = bsec_program_otp(version, otp);
192 if (result != BSEC_OK) {
193 ERROR("BSEC: MONOTONIC_OTP program Error %u\n",
194 result);
195 panic();
196 }
197 INFO("Monotonic counter has been incremented (value 0x%x)\n",
198 version);
199 }
200 }
201 #endif
202
bl2_el3_plat_arch_setup(void)203 void bl2_el3_plat_arch_setup(void)
204 {
205 const char *board_model;
206 boot_api_context_t *boot_context =
207 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
208 uintptr_t pwr_base;
209 uintptr_t rcc_base;
210
211 if (bsec_probe() != 0U) {
212 panic();
213 }
214
215 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
216 BL_CODE_END - BL_CODE_BASE,
217 MT_CODE | MT_SECURE);
218
219 /* Prevent corruption of preloaded Device Tree */
220 mmap_add_region(DTB_BASE, DTB_BASE,
221 DTB_LIMIT - DTB_BASE,
222 MT_RO_DATA | MT_SECURE);
223
224 configure_mmu();
225
226 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
227 panic();
228 }
229
230 pwr_base = stm32mp_pwr_base();
231 rcc_base = stm32mp_rcc_base();
232
233 /*
234 * Disable the backup domain write protection.
235 * The protection is enable at each reset by hardware
236 * and must be disabled by software.
237 */
238 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP);
239
240 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) {
241 ;
242 }
243
244 /* Reset backup domain on cold boot cases */
245 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
246 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
247
248 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) ==
249 0U) {
250 ;
251 }
252
253 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
254 }
255
256 /*
257 * Set minimum reset pulse duration to 31ms for discrete power
258 * supplied boards.
259 */
260 if (dt_pmic_status() <= 0) {
261 mmio_clrsetbits_32(rcc_base + RCC_RDLSICR,
262 RCC_RDLSICR_MRD_MASK,
263 31U << RCC_RDLSICR_MRD_SHIFT);
264 }
265
266 generic_delay_timer_init();
267
268 #if STM32MP_UART_PROGRAMMER
269 /* Disable programmer UART before changing clock tree */
270 if (boot_context->boot_interface_selected ==
271 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) {
272 uintptr_t uart_prog_addr =
273 get_uart_address(boot_context->boot_interface_instance);
274
275 stm32_uart_stop(uart_prog_addr);
276 }
277 #endif
278 if (stm32mp1_clk_probe() < 0) {
279 panic();
280 }
281
282 if (stm32mp1_clk_init() < 0) {
283 panic();
284 }
285
286 stm32_save_boot_info(boot_context);
287
288 #if STM32MP_USB_PROGRAMMER && STM32MP15
289 /* Deconfigure all UART RX pins configured by ROM code */
290 stm32mp1_deconfigure_uart_pins();
291 #endif
292
293 if (stm32mp_uart_console_setup() != 0) {
294 goto skip_console_init;
295 }
296
297 stm32mp_print_cpuinfo();
298
299 board_model = dt_get_board_model();
300 if (board_model != NULL) {
301 NOTICE("Model: %s\n", board_model);
302 }
303
304 stm32mp_print_boardinfo();
305
306 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) {
307 NOTICE("Bootrom authentication %s\n",
308 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ?
309 "failed" : "succeeded");
310 }
311
312 skip_console_init:
313 #if !TRUSTED_BOARD_BOOT
314 if (stm32mp_check_closed_device() == STM32MP_CHIP_SEC_CLOSED) {
315 /* Closed chip mandates authentication */
316 ERROR("Secure chip: TRUSTED_BOARD_BOOT must be enabled\n");
317 panic();
318 }
319 #endif
320
321 if (fixed_regulator_register() != 0) {
322 panic();
323 }
324
325 if (dt_pmic_status() > 0) {
326 initialize_pmic();
327 if (pmic_voltages_init() != 0) {
328 ERROR("PMIC voltages init failed\n");
329 panic();
330 }
331 print_pmic_info_and_debug();
332 }
333
334 stm32mp1_syscfg_init();
335
336 if (stm32_iwdg_init() < 0) {
337 panic();
338 }
339
340 stm32_iwdg_refresh();
341
342 if (bsec_read_debug_conf() != 0U) {
343 if (stm32mp_check_closed_device() == STM32MP_CHIP_SEC_CLOSED) {
344 #if DEBUG
345 WARN("\n%s", debug_msg);
346 #else
347 ERROR("***Debug opened on closed chip***\n");
348 #endif
349 }
350 }
351
352 #if STM32MP13
353 if (stm32_rng_init() != 0) {
354 panic();
355 }
356 #endif
357
358 stm32mp1_arch_security_setup();
359
360 print_reset_reason();
361
362 #if STM32MP15
363 if (stm32mp_check_closed_device() == STM32MP_CHIP_SEC_CLOSED) {
364 update_monotonic_counter();
365 }
366 #endif
367
368 stm32mp1_syscfg_enable_io_compensation_finish();
369
370 fconf_populate("TB_FW", STM32MP_DTB_BASE);
371
372 stm32mp_io_setup();
373 }
374
375 /*******************************************************************************
376 * This function can be used by the platforms to update/use image
377 * information for given `image_id`.
378 ******************************************************************************/
bl2_plat_handle_post_image_load(unsigned int image_id)379 int bl2_plat_handle_post_image_load(unsigned int image_id)
380 {
381 int err = 0;
382 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
383 bl_mem_params_node_t *bl32_mem_params;
384 bl_mem_params_node_t *pager_mem_params __unused;
385 bl_mem_params_node_t *paged_mem_params __unused;
386 const struct dyn_cfg_dtb_info_t *config_info;
387 bl_mem_params_node_t *tos_fw_mem_params;
388 unsigned int i;
389 unsigned int idx;
390 unsigned long long ddr_top __unused;
391 const unsigned int image_ids[] = {
392 BL32_IMAGE_ID,
393 BL33_IMAGE_ID,
394 HW_CONFIG_ID,
395 TOS_FW_CONFIG_ID,
396 };
397
398 assert(bl_mem_params != NULL);
399
400 switch (image_id) {
401 case FW_CONFIG_ID:
402 /* Set global DTB info for fixed fw_config information */
403 set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE,
404 FW_CONFIG_ID);
405 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE);
406
407 idx = dyn_cfg_dtb_info_get_index(TOS_FW_CONFIG_ID);
408
409 /* Iterate through all the fw config IDs */
410 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) {
411 if ((image_ids[i] == TOS_FW_CONFIG_ID) && (idx == FCONF_INVALID_IDX)) {
412 continue;
413 }
414
415 bl_mem_params = get_bl_mem_params_node(image_ids[i]);
416 assert(bl_mem_params != NULL);
417
418 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]);
419 if (config_info == NULL) {
420 continue;
421 }
422
423 bl_mem_params->image_info.image_base = config_info->config_addr;
424 bl_mem_params->image_info.image_max_size = config_info->config_max_size;
425
426 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
427
428 switch (image_ids[i]) {
429 case BL32_IMAGE_ID:
430 bl_mem_params->ep_info.pc = config_info->config_addr;
431
432 /* In case of OPTEE, initialize address space with tos_fw addr */
433 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
434 assert(pager_mem_params != NULL);
435 pager_mem_params->image_info.image_base = config_info->config_addr;
436 pager_mem_params->image_info.image_max_size =
437 config_info->config_max_size;
438
439 /* Init base and size for pager if exist */
440 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
441 if (paged_mem_params != NULL) {
442 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
443 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE -
444 STM32MP_DDR_SHMEM_SIZE);
445 paged_mem_params->image_info.image_max_size =
446 STM32MP_DDR_S_SIZE;
447 }
448 break;
449
450 case BL33_IMAGE_ID:
451 bl_mem_params->ep_info.pc = config_info->config_addr;
452 break;
453
454 case HW_CONFIG_ID:
455 case TOS_FW_CONFIG_ID:
456 break;
457
458 default:
459 return -EINVAL;
460 }
461 }
462 break;
463
464 case BL32_IMAGE_ID:
465 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) {
466 image_info_t *paged_image_info = NULL;
467
468 /* BL32 is OP-TEE header */
469 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
470 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
471 assert(pager_mem_params != NULL);
472
473 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
474 if (paged_mem_params != NULL) {
475 paged_image_info = &paged_mem_params->image_info;
476 }
477
478 err = parse_optee_header(&bl_mem_params->ep_info,
479 &pager_mem_params->image_info,
480 paged_image_info);
481 if (err != 0) {
482 ERROR("OPTEE header parse error.\n");
483 panic();
484 }
485
486 /* Set optee boot info from parsed header data */
487 if (paged_mem_params != NULL) {
488 bl_mem_params->ep_info.args.arg0 =
489 paged_mem_params->image_info.image_base;
490 } else {
491 bl_mem_params->ep_info.args.arg0 = 0U;
492 }
493
494 bl_mem_params->ep_info.args.arg1 = 0U; /* Unused */
495 bl_mem_params->ep_info.args.arg2 = 0U; /* No DT supported */
496 } else {
497 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
498 tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID);
499 assert(tos_fw_mem_params != NULL);
500 bl_mem_params->image_info.image_max_size +=
501 tos_fw_mem_params->image_info.image_max_size;
502 bl_mem_params->ep_info.args.arg0 = 0;
503 }
504 break;
505
506 case BL33_IMAGE_ID:
507 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
508 assert(bl32_mem_params != NULL);
509 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
510 #if PSA_FWU_SUPPORT
511 stm32mp1_fwu_set_boot_idx();
512 #endif /* PSA_FWU_SUPPORT */
513 break;
514
515 default:
516 /* Do nothing in default case */
517 break;
518 }
519
520 #if STM32MP_SDMMC || STM32MP_EMMC
521 /*
522 * Invalidate remaining data read from MMC but not flushed by load_image_flush().
523 * We take the worst case which is 2 MMC blocks.
524 */
525 if ((image_id != FW_CONFIG_ID) &&
526 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) {
527 inv_dcache_range(bl_mem_params->image_info.image_base +
528 bl_mem_params->image_info.image_size,
529 2U * MMC_BLOCK_SIZE);
530 }
531 #endif /* STM32MP_SDMMC || STM32MP_EMMC */
532
533 return err;
534 }
535
bl2_el3_plat_prepare_exit(void)536 void bl2_el3_plat_prepare_exit(void)
537 {
538 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
539 uint16_t boot_itf = stm32mp_get_boot_itf_selected();
540
541 if ((boot_itf == BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) ||
542 (boot_itf == BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB)) {
543 /* Invalidate the downloaded buffer used with io_memmap */
544 inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE);
545 }
546 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */
547
548 stm32mp1_security_setup();
549 }
550