1 /*
2  * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
3  * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /* Versal IPI management enums and defines */
9 
10 #ifndef PLAT_IPI_H
11 #define PLAT_IPI_H
12 
13 #include <stdint.h>
14 
15 #include <ipi.h>
16 
17 /*********************************************************************
18  * IPI agent IDs macros
19  ********************************************************************/
20 #define IPI_ID_PMC	1U
21 #define IPI_ID_APU	2U
22 #define IPI_ID_RPU0	3U
23 #define IPI_ID_RPU1	4U
24 #define IPI_ID_3	5U
25 #define IPI_ID_4	6U
26 #define IPI_ID_5	7U
27 
28 /*********************************************************************
29  * IPI message buffers
30  ********************************************************************/
31 #define IPI_BUFFER_BASEADDR	0xFF3F0000U
32 
33 #define IPI_LOCAL_ID		IPI_ID_APU
34 #define IPI_REMOTE_ID		IPI_ID_PMC
35 
36 #define IPI_BUFFER_LOCAL_BASE	(IPI_BUFFER_BASEADDR + (IPI_LOCAL_ID * 0x200U))
37 #define IPI_BUFFER_REMOTE_BASE	(IPI_BUFFER_BASEADDR + (IPI_REMOTE_ID * 0x200U))
38 
39 #define IPI_BUFFER_TARGET_LOCAL_OFFSET	(IPI_LOCAL_ID * 0x40U)
40 #define IPI_BUFFER_TARGET_REMOTE_OFFSET	(IPI_REMOTE_ID * 0x40U)
41 
42 #define IPI_BUFFER_MAX_WORDS	8
43 
44 #define IPI_BUFFER_REQ_OFFSET	0x0U
45 #define IPI_BUFFER_RESP_OFFSET	0x20U
46 
47 /*********************************************************************
48  * Platform specific IPI API declarations
49  ********************************************************************/
50 
51 /* Configure IPI table for versal */
52 void versal_ipi_config_table_init(void);
53 
54 /* IPI registers and bitfields */
55 #define PMC_REG_BASE		U(0xFF320000)
56 #define PMC_IPI_TRIG_BIT	(1U << 1U)
57 #define IPI0_REG_BASE		U(0xFF330000)
58 #define IPI0_TRIG_BIT		(1U << 2U)
59 #define IPI1_REG_BASE		U(0xFF340000)
60 #define IPI1_TRIG_BIT		(1U << 3U)
61 #define IPI2_REG_BASE		U(0xFF350000)
62 #define IPI2_TRIG_BIT		(1U << 4U)
63 #define IPI3_REG_BASE		U(0xFF360000)
64 #define IPI3_TRIG_BIT		(1U << 5U)
65 #define IPI4_REG_BASE		U(0xFF370000)
66 #define IPI4_TRIG_BIT		(1U << 5U)
67 #define IPI5_REG_BASE		U(0xFF380000)
68 #define IPI5_TRIG_BIT		(1U << 6U)
69 
70 #endif /* PLAT_IPI_H */
71