1 /*
2  * Copyright (c) 2019 LK Trusty Authors. All Rights Reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining
5  * a copy of this software and associated documentation files
6  * (the "Software"), to deal in the Software without restriction,
7  * including without limitation the rights to use, copy, modify, merge,
8  * publish, distribute, sublicense, and/or sell copies of the Software,
9  * and to permit persons to whom the Software is furnished to do so,
10  * subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be
13  * included in all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19  * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #pragma once
25 
26 #include <stdint.h>
27 
28 /**
29  * struct pci_type0_config - Type 00h Configuration Space Header
30  * @vendor_id:              The manufacturer of the device identifier.
31  * @device_id:              The particular device identifier.
32  * @command:                Control over a device's ability to generate and
33  *                          respond to PCI cycles.
34  * @status:                 Record status information for PCI bus related
35  *                          events.
36  * @revision_id:            Device specific revision identifier.
37  * @class_code:             Identify the generic function of the device.
38  * @cache_line_size:        Specify the system cacheline size.
39  * @latency_timer:          The value of the Latency Timer for this PCI bus
40  *                          master in units of PCI bus clocks.
41  * @header_type:            Identify the layout of the second part of the
42  *                          predefined header.
43  * @bist:                   Control and status of Built-in Self Test.
44  * @base_addr_reg0:         Base Address register 0
45  * @base_addr_reg1:         Base Address register 1
46  * @base_addr_reg2:         Base Address register 2
47  * @base_addr_reg3:         Base Address register 3
48  * @base_addr_reg4:         Base Address register 4
49  * @base_addr_reg5:         Base Address register 5
50  * @cardbus_cis_pointer:    Used by those devices that want to share silicon
51  *                          between CardBus and PCI.
52  * @subsystem_vendor_id:    Vendor of the add-in card or subsystem.
53  * @subsystem_id:           Vendor specific identifier.
54  * @expansion_rom_base:     Base address and size information for expansion ROM.
55  * @capabilities_pointer:   Point to a linked list of new capabilities
56  *                          implemented by this device.
57  * @rsvd:                   Reserved.
58  * @interrupt_line:         Communicate interrupt line routing information.
59  * @interrupt_pin:          Interrupt pin the device (or device function) uses.
60  * @min_gnt:                Specify how long a burst period the device needs
61  *                          assuming a clock rate of 33 MHz.
62  * @max_lat:                Specify how often the device needs to gain access
63  *                          to the PCI bus.
64  */
65 struct pci_type0_config {
66     uint16_t vendor_id;
67     uint16_t device_id;
68     uint16_t command;
69     uint16_t status;
70     uint8_t revision_id;
71     uint8_t class_code[3];
72     uint8_t cache_line_size;
73     uint8_t latency_timer;
74     uint8_t header_type;
75     uint8_t bist;
76     uint32_t base_addr_reg0;
77     uint32_t base_addr_reg1;
78     uint32_t base_addr_reg2;
79     uint32_t base_addr_reg3;
80     uint32_t base_addr_reg4;
81     uint32_t base_addr_reg5;
82     uint32_t cardbus_cis_pointer;
83     uint16_t subsystem_vendor_id;
84     uint16_t subsystem_id;
85     uint32_t expansion_rom_base;
86     uint8_t capabilities_pointer;
87     uint8_t rsvd[7];
88     uint8_t interrupt_line;
89     uint8_t interrupt_pin;
90     uint8_t min_gnt;
91     uint8_t max_lat;
92 };
93 
94 /*
95  * Memory Space bit in Command Register.
96  *  Control a device's response to Memory Space access.
97  */
98 #define CMD_MEM_SPACE_BIT_POSITION 1
99 
100 /*
101  * Capabilites bit in Status Register.
102  *  This optional ready-only bit indicates whether or not this device
103  *  implements the pointer for a New Capabilities linked list at
104  *  offset 34h.
105  */
106 #define STATUS_CAP_LIST_BIT_POSITION 4
107