1 /**************************************************************************
2 *
3 * Copyright 2020 Google LLC
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 **************************************************************************/
24
25 /*
26 * basic library initialisation, teardown, reset
27 * and context creation tests.
28 */
29
30 #include <check.h>
31 #include <errno.h>
32 #include <poll.h>
33 #include <stdlib.h>
34 #include <unistd.h>
35 #include <virglrenderer.h>
36
37 #include "testvirgl.h"
38
START_TEST(virgl_fence_create)39 START_TEST(virgl_fence_create)
40 {
41 int ret;
42 ret = testvirgl_init_single_ctx();
43 ck_assert_int_eq(ret, 0);
44
45 testvirgl_reset_fence();
46 ret = virgl_renderer_create_fence(1, 0);
47 ck_assert_int_eq(ret, 0);
48
49 testvirgl_fini_single_ctx();
50 }
51 END_TEST
52
START_TEST(virgl_fence_poll)53 START_TEST(virgl_fence_poll)
54 {
55 const int target_seqno = 50;
56 int ret;
57 ret = testvirgl_init_single_ctx();
58 ck_assert_int_eq(ret, 0);
59
60 testvirgl_reset_fence();
61 ret = virgl_renderer_create_fence(target_seqno, 0);
62 ck_assert_int_eq(ret, 0);
63
64 do {
65 int seqno;
66
67 virgl_renderer_poll();
68 seqno = testvirgl_get_last_fence();
69 if (seqno == target_seqno)
70 break;
71
72 ck_assert_int_eq(seqno, 0);
73 usleep(1000);
74 } while(1);
75
76 testvirgl_fini_single_ctx();
77 }
78 END_TEST
79
START_TEST(virgl_fence_poll_many)80 START_TEST(virgl_fence_poll_many)
81 {
82 const int fence_count = 100;
83 const int base_seqno = 50;
84 const int target_seqno = base_seqno + fence_count - 1;
85 int last_seqno;
86 int ret;
87 int i;
88
89 ret = testvirgl_init_single_ctx();
90 ck_assert_int_eq(ret, 0);
91
92 testvirgl_reset_fence();
93 last_seqno = 0;
94
95 for (i = 0; i < fence_count; i++) {
96 ret = virgl_renderer_create_fence(base_seqno + i, 0);
97 ck_assert_int_eq(ret, 0);
98 }
99
100 do {
101 int seqno;
102
103 virgl_renderer_poll();
104 seqno = testvirgl_get_last_fence();
105 if (seqno == target_seqno)
106 break;
107
108 ck_assert(seqno == 0 || (seqno >= base_seqno && seqno < target_seqno));
109
110 /* monotonic increasing */
111 ck_assert_int_ge(seqno, last_seqno);
112 last_seqno = seqno;
113
114 usleep(1000);
115 } while(1);
116
117 testvirgl_fini_single_ctx();
118 }
119 END_TEST
120
121 static int
wait_sync_fd(int fd,int timeout)122 wait_sync_fd(int fd, int timeout)
123 {
124 struct pollfd pollfd = {
125 .fd = fd,
126 .events = POLLIN,
127 };
128 int ret;
129 do {
130 ret = poll(&pollfd, 1, timeout);
131 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
132
133 if (ret < 0)
134 return -errno;
135 else if (ret > 0 && !(pollfd.revents & POLLIN))
136 return -EINVAL;
137
138 return ret ? 0 : -ETIME;
139 }
140
START_TEST(virgl_fence_export)141 START_TEST(virgl_fence_export)
142 {
143 const int target_seqno = 50;
144 int fd;
145 int ret;
146
147 ret = testvirgl_init_single_ctx();
148 ck_assert_int_eq(ret, 0);
149
150 testvirgl_reset_fence();
151 ret = virgl_renderer_create_fence(target_seqno, 0);
152 ck_assert_int_eq(ret, 0);
153
154 ret = virgl_renderer_export_fence(target_seqno, &fd);
155 ck_assert_int_eq(ret, 0);
156
157 ret = wait_sync_fd(fd, -1);
158 ck_assert_int_eq(ret, 0);
159
160 virgl_renderer_poll();
161 ck_assert_int_eq(testvirgl_get_last_fence(), target_seqno);
162
163 close(fd);
164
165 testvirgl_fini_single_ctx();
166 }
167 END_TEST
168
START_TEST(virgl_fence_export_signaled)169 START_TEST(virgl_fence_export_signaled)
170 {
171 const int target_seqno = 50;
172 const int test_range = 10;
173 int fd;
174 int ret;
175 int i;
176
177 ret = testvirgl_init_single_ctx();
178 ck_assert_int_eq(ret, 0);
179
180 /* when there is no active fence, a signaled fd is always returned */
181 for (i = 0; i < test_range; i++) {
182 ret = virgl_renderer_export_fence(target_seqno + 1 + i, &fd);
183 ck_assert_int_eq(ret, 0);
184
185 ret = wait_sync_fd(fd, 0);
186 ck_assert_int_eq(ret, 0);
187
188 close(fd);
189 }
190
191 ret = virgl_renderer_create_fence(target_seqno, 0);
192 ck_assert_int_eq(ret, 0);
193
194 /* when there is any active fence, a signaled fd is returned when the
195 * requested seqno is smaller than the first active fence
196 */
197 for (i = 0; i < test_range; i++) {
198 ret = virgl_renderer_export_fence(target_seqno - 1 - i, &fd);
199 ck_assert_int_eq(ret, 0);
200
201 ret = wait_sync_fd(fd, 0);
202 ck_assert_int_eq(ret, 0);
203
204 close(fd);
205 }
206
207 testvirgl_fini_single_ctx();
208 }
209 END_TEST
210
START_TEST(virgl_fence_export_invalid)211 START_TEST(virgl_fence_export_invalid)
212 {
213 const int target_seqno = 50;
214 const int target_seqno2 = 55;
215 int seqno;
216 int fd;
217 int ret;
218
219 ret = testvirgl_init_single_ctx();
220 ck_assert_int_eq(ret, 0);
221
222 ret = virgl_renderer_create_fence(target_seqno, 0);
223 ck_assert_int_eq(ret, 0);
224 ret = virgl_renderer_create_fence(target_seqno2, 0);
225 ck_assert_int_eq(ret, 0);
226
227 for (seqno = target_seqno; seqno <= target_seqno2 + 1; seqno++) {
228 ret = virgl_renderer_export_fence(seqno, &fd);
229 if (seqno == target_seqno || seqno == target_seqno2) {
230 ck_assert_int_eq(ret, 0);
231 close(fd);
232 } else {
233 ck_assert_int_eq(ret, -EINVAL);
234 }
235 }
236
237 testvirgl_fini_single_ctx();
238 }
239 END_TEST
240
virgl_init_suite(bool include_fence_export)241 static Suite *virgl_init_suite(bool include_fence_export)
242 {
243 Suite *s;
244 TCase *tc_core;
245
246 s = suite_create("virgl_fence");
247 tc_core = tcase_create("fence");
248
249 tcase_add_test(tc_core, virgl_fence_create);
250 tcase_add_test(tc_core, virgl_fence_poll);
251 tcase_add_test(tc_core, virgl_fence_poll_many);
252
253 if (include_fence_export) {
254 tcase_add_test(tc_core, virgl_fence_export);
255 tcase_add_test(tc_core, virgl_fence_export_signaled);
256 tcase_add_test(tc_core, virgl_fence_export_invalid);
257 }
258
259 suite_add_tcase(s, tc_core);
260
261 return s;
262 }
263
detect_fence_export_support(void)264 static bool detect_fence_export_support(void)
265 {
266 int dummy_cookie;
267 struct virgl_renderer_callbacks dummy_cbs;
268 int fd;
269 int ret;
270
271 memset(&dummy_cbs, 0, sizeof(dummy_cbs));
272 dummy_cbs.version = 1;
273
274 ret = virgl_renderer_init(&dummy_cookie, context_flags, &dummy_cbs);
275 if (ret)
276 return false;
277
278 ret = virgl_renderer_export_fence(0, &fd);
279 if (ret) {
280 virgl_renderer_cleanup(&dummy_cookie);
281 return false;
282 }
283
284 close(fd);
285 virgl_renderer_cleanup(&dummy_cookie);
286 return true;
287 }
288
main(void)289 int main(void)
290 {
291 Suite *s;
292 SRunner *sr;
293 int number_failed;
294 bool include_fence_export = false;
295
296 if (getenv("VRENDTEST_USE_EGL_SURFACELESS"))
297 context_flags |= VIRGL_RENDERER_USE_SURFACELESS;
298 if (getenv("VRENDTEST_USE_EGL_GLES")) {
299 context_flags |= VIRGL_RENDERER_USE_GLES;
300 include_fence_export = detect_fence_export_support();
301 }
302
303 s = virgl_init_suite(include_fence_export);
304 sr = srunner_create(s);
305
306 srunner_run_all(sr, CK_NORMAL);
307 number_failed = srunner_ntests_failed(sr);
308 srunner_free(sr);
309
310 return number_failed == 0 ? EXIT_SUCCESS : EXIT_FAILURE;
311 }
312