1 /*
2  * Copyright (C) 2022 The Android Open Source Project
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #ifndef ANDROID_EXYNOS_HWC_MODULE_ZUMA_H_
18 #define ANDROID_EXYNOS_HWC_MODULE_ZUMA_H_
19 
20 #include "../../gs201/libhwc2.1/ExynosHWCModule.h"
21 #include "ExynosHWCHelper.h"
22 
23 namespace zuma {
24 
25 static const char *early_wakeup_node_0_base =
26     "/sys/devices/platform/19470000.drmdecon/early_wakeup";
27 
28 typedef enum assignOrderType {
29     ORDER_AFBC,
30     ORDER_WCG,
31     ORDER_AXI,
32 } assignOrderType_t;
33 
34 typedef enum DPUblockId {
35     DPUF0,
36     DPUF1,
37     DPU_BLOCK_CNT,
38 } DPUblockId_t;
39 
40 const std::unordered_map<DPUblockId_t, String8> DPUBlocks = {
41     {DPUF0, String8("DPUF0")},
42     {DPUF1, String8("DPUF1")},
43 };
44 
45 typedef enum AXIPortId {
46     AXI0,
47     AXI1,
48     AXI_PORT_MAX_CNT,
49     AXI_DONT_CARE
50 } AXIPortId_t;
51 
52 const std::map<AXIPortId_t, String8> AXIPorts = {
53         {AXI0, String8("AXI0")},
54         {AXI1, String8("AXI1")},
55 };
56 
57 typedef enum ConstraintRev {
58     CONSTRAINT_NONE = 0, // don't care
59     CONSTRAINT_A0,
60     CONSTRAINT_B0
61 } ConstraintRev_t;
62 
63 static const dpp_channel_map_t idma_channel_map[] = {
64     /* GF physical index is switched to change assign order */
65     /* DECON_IDMA is not used */
66     {MPP_DPP_GFS,     0, IDMA(0),   IDMA(0)},
67     {MPP_DPP_VGRFS,   0, IDMA(1),   IDMA(1)},
68     {MPP_DPP_GFS,     1, IDMA(2),   IDMA(2)},
69     {MPP_DPP_VGRFS,   1, IDMA(3),   IDMA(3)},
70     {MPP_DPP_GFS,     2, IDMA(4),   IDMA(4)},
71     {MPP_DPP_VGRFS,   2, IDMA(5),   IDMA(5)},
72     {MPP_DPP_GFS,     3, IDMA(6),   IDMA(6)},
73     {MPP_DPP_GFS,     4, IDMA(7),   IDMA(7)},
74     {MPP_DPP_VGRFS,   3, IDMA(8),   IDMA(8)},
75     {MPP_DPP_GFS,     5, IDMA(9),   IDMA(9)},
76     {MPP_DPP_VGRFS,   4, IDMA(10),  IDMA(10)},
77     {MPP_DPP_GFS,     6, IDMA(11),  IDMA(11)},
78     {MPP_DPP_VGRFS,   5, IDMA(12),  IDMA(12)},
79     {MPP_DPP_GFS,     7, IDMA(13),  IDMA(13)},
80     {MPP_P_TYPE_MAX,  0, ODMA_WB,   IDMA(14)}, // not idma but..
81     {static_cast<mpp_phycal_type_t>(MAX_DECON_DMA_TYPE), 0, MAX_DECON_DMA_TYPE,
82         IDMA(15)}
83 };
84 
85 static const exynos_mpp_t available_otf_mpp_units[] = {
86     // Zuma has 8 Graphics-Only Layers
87     // Zuma has 6 Video-Graphics Layers
88     // Zuma has total 14 Layers
89 
90     // DPP0(IDMA_GFS0) in DPUF0 is connected with AXI0 port
91     {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS0", 0, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
92      static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)},
93     // DPP1(IDMA_VGRFS0) in DPUF0 is connected with AXI0 port
94     {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS0", 0, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
95      static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)},
96     // DPP2(IDMA_GFS1) in DPUF0 is connected with AXI0 port
97     {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS1", 1, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
98      static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)},
99     // DPP3(IDMA_VGRFS1) in DPUF0 is connected with AXI0 port
100     {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS1", 1, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
101      static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)},
102 
103     // DPP4(IDMA_GFS2) in DPUF0 is connected with AXI1 port
104     {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS2", 2, 0, HWC_RESERVE_DISPLAY_MINOR_BIT,
105      static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI1)},
106     // DPP5(IDMA_VGRFS2) in DPUF0 is connected with AXI1 port
107     {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS2", 2, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
108      static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI1)},
109     // DPP6(IDMA_GFS3) in DPUF0 is connected with AXI1 port
110     {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS3", 3, 0, HWC_RESERVE_DISPLAY_MINOR_BIT,
111      static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI1)},
112 
113     // DPP7(IDMA_GFS4) in DPUF1 is connected with AXI1 port
114     {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS4", 4, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
115      static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)},
116     // DPP8(IDMA_VGRFS3) in DPUF1 is connected with AXI1 port
117     {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS3", 3, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
118      static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)},
119     // DPP9(IDMA_GFS5) in DPUF1 is connected with AXI1 port
120     {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS5", 5, 0, HWC_RESERVE_DISPLAY_MINOR_BIT,
121      static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)},
122     // DPP10(IDMA_VGRFS4) in DPUF1 is connected with AXI1 port
123     {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS4", 4, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
124      static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)},
125 
126     // DPP11(IDMA_GFS6) in DPUF1 is connected with AXI0 port
127     {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS6", 6, 0, HWC_RESERVE_DISPLAY_MINOR_BIT,
128      static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)},
129     // DPP12(IDMA_VGRFS5) in DPUF1 is connected with AXI0 port
130     {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS5", 5, 0, HWC_RESERVE_DISPLAY_MINOR_BIT,
131      static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)},
132     // DPP13(IDMA_GFS7) in DPUF1 is connected with AXI0 port
133     {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS7", 7, 0, HWC_RESERVE_DISPLAY_MINOR_BIT,
134      static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)},
135 };
136 
137 static const std::array<exynos_display_t, 3> AVAILABLE_DISPLAY_UNITS = {{
138     {HWC_DISPLAY_PRIMARY, 0, "PrimaryDisplay", "/dev/dri/card0", ""},
139     {HWC_DISPLAY_PRIMARY, 1, "SecondaryDisplay", "/dev/dri/card0", ""},
140     {HWC_DISPLAY_EXTERNAL, 0, "ExternalDisplay", "/dev/dri/card0", ""}
141 }};
142 
143 /*
144  * Note :
145  * When External or Virtual display is connected,
146  * Primary amount = total - others
147  */
148 class HWResourceIndexes {
149     private:
150         tdm_attr_t attr;
151         DPUblockId_t DPUBlockNo;
152         AXIPortId_t axiId;
153         ConstraintRev_t constraintRev;
154 
155     public:
HWResourceIndexes(const tdm_attr_t & _attr,const DPUblockId_t & _DPUBlockNo,const AXIPortId_t & _axiId,const ConstraintRev_t & _constraintRev)156         HWResourceIndexes(const tdm_attr_t& _attr, const DPUblockId_t& _DPUBlockNo,
157                           const AXIPortId_t& _axiId, const ConstraintRev_t& _constraintRev)
158               : attr(_attr),
159                 DPUBlockNo(_DPUBlockNo),
160                 axiId(_axiId),
161                 constraintRev(_constraintRev) {}
162         bool operator<(const HWResourceIndexes& rhs) const {
163             if (attr != rhs.attr) return attr < rhs.attr;
164 
165             if (DPUBlockNo != rhs.DPUBlockNo) return DPUBlockNo < rhs.DPUBlockNo;
166 
167             if (axiId != AXI_DONT_CARE && rhs.axiId != AXI_DONT_CARE && axiId != rhs.axiId)
168                 return axiId < rhs.axiId;
169 
170             if (constraintRev != CONSTRAINT_NONE) return constraintRev < rhs.constraintRev;
171 
172             return false;
173         }
toString8()174         String8 toString8() const {
175             String8 log;
176             log.appendFormat("attr=%d,DPUBlockNo=%d,axiId=%d,constraintRev=%d", attr, DPUBlockNo,
177                              axiId, constraintRev);
178             return log;
179         }
180 };
181 
182 typedef struct HWResourceAmounts {
183     int mainAmount;
184     int minorAmount;
185     int total;
186 } HWResourceAmounts_t;
187 
188 /* Note :
189  * When External or Virtual display is connected,
190  * Primary amount = total - others */
191 
192 const std::map<HWResourceIndexes, HWResourceAmounts_t> HWResourceTables = {
193     // SRAM
194     {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {50, 30, 80}},
195     {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {50, 30, 80}},
196     // SCALE
197     {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {2, 0, 2}},
198     {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {1, 1, 2}},
199     // SBWC
200     {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {2, 0, 2}},
201     {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {0, 2, 2}},
202     // AFBC
203     {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {3, 1, 4}},
204     {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {1, 3, 4}},
205     // ITP
206     {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {3, 1, 4}},
207     {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {1, 3, 4}},
208     // ROT_90
209     {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {1, 1, 2}},
210     {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {1, 1, 2}},
211     // WCG
212     {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI_DONT_CARE, CONSTRAINT_A0), {2, 0, 2}},
213     {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI_DONT_CARE, CONSTRAINT_A0), {0, 2, 2}},
214     {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI0, CONSTRAINT_B0), {2, 0, 2}},
215     {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI1, CONSTRAINT_B0), {2, 0, 2}},
216     {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI0, CONSTRAINT_B0), {0, 2, 2}},
217     {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI1, CONSTRAINT_B0), {0, 2, 2}},
218 };
219 
220 typedef enum lbWidthIndex {
221     LB_W_8_512,
222     LB_W_513_1024,
223     LB_W_1025_1536,
224     LB_W_1537_2048,
225     LB_W_2049_2304,
226     LB_W_2305_2560,
227     LB_W_2561_3072,
228     LB_W_3073_INF,
229 } lbWidthIndex_t;
230 
231 typedef struct lbWidthBoundary {
232     uint32_t widthDownto;
233     uint32_t widthUpto;
234 } lbWidthBoundary_t;
235 
236 const std::map<lbWidthIndex_t, lbWidthBoundary_t> LB_WIDTH_INDEX_MAP = {
237     {LB_W_8_512,     {8, 512}},
238     {LB_W_513_1024,  {513, 1024}},
239     {LB_W_1025_1536, {1025, 1536}},
240     {LB_W_1537_2048, {1537, 2048}},
241     {LB_W_2049_2304, {2049, 2304}},
242     {LB_W_2305_2560, {2035, 2560}},
243     {LB_W_2561_3072, {2561, 3072}},
244     {LB_W_3073_INF,  {3073, 0xffff}},
245 };
246 
247 class sramAmountParams {
248 private:
249     tdm_attr_t attr;
250     uint32_t formatProperty;
251     lbWidthIndex_t widthIndex;
252 
253 public:
sramAmountParams(tdm_attr_t _attr,uint32_t _formatProperty,lbWidthIndex_t _widthIndex)254     sramAmountParams(tdm_attr_t _attr, uint32_t _formatProperty, lbWidthIndex_t _widthIndex)
255           : attr(_attr), formatProperty(_formatProperty), widthIndex(_widthIndex) {}
256     bool operator<(const sramAmountParams& rhs) const {
257         if (attr != rhs.attr) return attr < rhs.attr;
258 
259         if (formatProperty != rhs.formatProperty) return formatProperty < rhs.formatProperty;
260 
261         if (widthIndex != rhs.widthIndex) return widthIndex < rhs.widthIndex;
262 
263         return false;
264     }
265 };
266 
267 enum {
268     SBWC_Y = 0,
269     SBWC_UV,
270     NON_SBWC_Y,
271     NON_SBWC_UV,
272 };
273 
274 const std::map<sramAmountParams, uint32_t> sramAmountMap = {
275     /** Non rotation **/
276     /** BIT8 = 32bit format **/
277     {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_8_512),     4},
278     {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_513_1024),  4},
279     {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_1025_1536), 8},
280     {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_1537_2048), 8},
281     {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_2049_2304), 12},
282     {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_2305_2560), 12},
283     {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_2561_3072), 12},
284     {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_3073_INF),  16},
285 
286     /** 16bit format **/
287     {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_8_512),     2},
288     {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_513_1024),  2},
289     {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_1025_1536), 4},
290     {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_1537_2048), 4},
291     {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_2049_2304), 6},
292     {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_2305_2560), 6},
293     {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_2561_3072), 6},
294     {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_3073_INF),  8},
295 
296     {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_8_512),     1},
297     {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_513_1024),  1},
298     {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_1025_1536), 1},
299     {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_1537_2048), 1},
300     {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_2049_2304), 2},
301     {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_2305_2560), 2},
302     {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_2561_3072), 2},
303     {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_3073_INF),  2},
304 
305     {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_8_512),     2},
306     {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_513_1024),  2},
307     {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_1025_1536), 2},
308     {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_1537_2048), 2},
309     {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_2049_2304), 2},
310     {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_2305_2560), 2},
311     {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_2561_3072), 2},
312     {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_3073_INF),  2},
313 
314     /** Rotation **/
315     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_8_512),     4},
316     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_513_1024),  8},
317     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_1025_1536), 12},
318     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_1537_2048), 16},
319     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_2049_2304), 18},
320     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_2305_2560), 18},
321     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_2561_3072), 18},
322     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_3073_INF),  18},
323 
324     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_8_512),     2},
325     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_513_1024),  4},
326     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_1025_1536), 6},
327     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_1537_2048), 8},
328     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_2049_2304), 10},
329     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_2305_2560), 10},
330     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_2561_3072), 10},
331     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_3073_INF),  10},
332 
333     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_8_512),     2},
334     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_513_1024),  4},
335     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_1025_1536), 6},
336     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_1537_2048), 8},
337     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_2049_2304), 9},
338     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_2305_2560), 9},
339     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_2561_3072), 9},
340     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_3073_INF),  9},
341 
342     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_8_512),     2},
343     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_513_1024),  2},
344     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_1025_1536), 4},
345     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_1537_2048), 4},
346     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_2049_2304), 6},
347     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_2305_2560), 6},
348     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_2561_3072), 6},
349     {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_3073_INF),  6},
350 
351     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_8_512),     2},
352     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_513_1024),  4},
353     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_1025_1536), 6},
354     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_1537_2048), 8},
355     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_2049_2304), 9},
356     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_2305_2560), 9},
357     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_2561_3072), 9},
358     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_3073_INF),  9},
359 
360     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_8_512),     2},
361     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_513_1024),  2},
362     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_1025_1536), 4},
363     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_1537_2048), 4},
364     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_2049_2304), 6},
365     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_2305_2560), 6},
366     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_2561_3072), 6},
367     {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_3073_INF),  6},
368 
369     {sramAmountParams(TDM_ATTR_ITP, BIT8, LB_W_3073_INF),  2},
370     {sramAmountParams(TDM_ATTR_ITP, BIT10, LB_W_3073_INF), 2},
371 
372     /* It's meaning like ow,
373      * FORMAT_YUV_MASK == has no alpha, FORMAT_RGB_MASK == has alpha */
374     {sramAmountParams(TDM_ATTR_SCALE, FORMAT_YUV_MASK, LB_W_3073_INF), 12},
375     {sramAmountParams(TDM_ATTR_SCALE, FORMAT_RGB_MASK, LB_W_3073_INF), 16}};
376 } // namespace zuma
377 
378 #endif // ANDROID_EXYNOS_HWC_MODULE_ZUMA_H_
379