1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _UAPI_I915_DRM_H_ 8 #define _UAPI_I915_DRM_H_ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 14 #define I915_ERROR_UEVENT "ERROR" 15 #define I915_RESET_UEVENT "RESET" 16 struct i915_user_extension { 17 __u64 next_extension; 18 __u32 name; 19 __u32 flags; 20 __u32 rsvd[4]; 21 }; 22 enum i915_mocs_table_index { 23 I915_MOCS_UNCACHED, 24 I915_MOCS_PTE, 25 I915_MOCS_CACHED, 26 }; 27 enum drm_i915_gem_engine_class { 28 I915_ENGINE_CLASS_RENDER = 0, 29 I915_ENGINE_CLASS_COPY = 1, 30 I915_ENGINE_CLASS_VIDEO = 2, 31 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, 32 I915_ENGINE_CLASS_COMPUTE = 4, 33 I915_ENGINE_CLASS_INVALID = - 1 34 }; 35 struct i915_engine_class_instance { 36 __u16 engine_class; 37 #define I915_ENGINE_CLASS_INVALID_NONE - 1 38 #define I915_ENGINE_CLASS_INVALID_VIRTUAL - 2 39 __u16 engine_instance; 40 }; 41 enum drm_i915_pmu_engine_sample { 42 I915_SAMPLE_BUSY = 0, 43 I915_SAMPLE_WAIT = 1, 44 I915_SAMPLE_SEMA = 2 45 }; 46 #define I915_PMU_SAMPLE_BITS (4) 47 #define I915_PMU_SAMPLE_MASK (0xf) 48 #define I915_PMU_SAMPLE_INSTANCE_BITS (8) 49 #define I915_PMU_CLASS_SHIFT (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) 50 #define __I915_PMU_ENGINE(__linux_class,instance,sample) ((__linux_class) << I915_PMU_CLASS_SHIFT | (instance) << I915_PMU_SAMPLE_BITS | (sample)) 51 #define I915_PMU_ENGINE_BUSY(__linux_class,instance) __I915_PMU_ENGINE(__linux_class, instance, I915_SAMPLE_BUSY) 52 #define I915_PMU_ENGINE_WAIT(__linux_class,instance) __I915_PMU_ENGINE(__linux_class, instance, I915_SAMPLE_WAIT) 53 #define I915_PMU_ENGINE_SEMA(__linux_class,instance) __I915_PMU_ENGINE(__linux_class, instance, I915_SAMPLE_SEMA) 54 #define __I915_PMU_GT_SHIFT (60) 55 #define ___I915_PMU_OTHER(gt,x) (((__u64) __I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | ((__u64) (gt) << __I915_PMU_GT_SHIFT)) 56 #define __I915_PMU_OTHER(x) ___I915_PMU_OTHER(0, x) 57 #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) 58 #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) 59 #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) 60 #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) 61 #define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4) 62 #define I915_PMU_LAST I915_PMU_RC6_RESIDENCY 63 #define __I915_PMU_ACTUAL_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 0) 64 #define __I915_PMU_REQUESTED_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 1) 65 #define __I915_PMU_INTERRUPTS(gt) ___I915_PMU_OTHER(gt, 2) 66 #define __I915_PMU_RC6_RESIDENCY(gt) ___I915_PMU_OTHER(gt, 3) 67 #define __I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt) ___I915_PMU_OTHER(gt, 4) 68 #define I915_NR_TEX_REGIONS 255 69 #define I915_LOG_MIN_TEX_REGION_SIZE 14 70 typedef struct _drm_i915_init { 71 enum { 72 I915_INIT_DMA = 0x01, 73 I915_CLEANUP_DMA = 0x02, 74 I915_RESUME_DMA = 0x03 75 } func; 76 unsigned int mmio_offset; 77 int sarea_priv_offset; 78 unsigned int ring_start; 79 unsigned int ring_end; 80 unsigned int ring_size; 81 unsigned int front_offset; 82 unsigned int back_offset; 83 unsigned int depth_offset; 84 unsigned int w; 85 unsigned int h; 86 unsigned int pitch; 87 unsigned int pitch_bits; 88 unsigned int back_pitch; 89 unsigned int depth_pitch; 90 unsigned int cpp; 91 unsigned int chipset; 92 } drm_i915_init_t; 93 typedef struct _drm_i915_sarea { 94 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 95 int last_upload; 96 int last_enqueue; 97 int last_dispatch; 98 int ctxOwner; 99 int texAge; 100 int pf_enabled; 101 int pf_active; 102 int pf_current_page; 103 int perf_boxes; 104 int width, height; 105 drm_handle_t front_handle; 106 int front_offset; 107 int front_size; 108 drm_handle_t back_handle; 109 int back_offset; 110 int back_size; 111 drm_handle_t depth_handle; 112 int depth_offset; 113 int depth_size; 114 drm_handle_t tex_handle; 115 int tex_offset; 116 int tex_size; 117 int log_tex_granularity; 118 int pitch; 119 int rotation; 120 int rotated_offset; 121 int rotated_size; 122 int rotated_pitch; 123 int virtualX, virtualY; 124 unsigned int front_tiled; 125 unsigned int back_tiled; 126 unsigned int depth_tiled; 127 unsigned int rotated_tiled; 128 unsigned int rotated2_tiled; 129 int pipeA_x; 130 int pipeA_y; 131 int pipeA_w; 132 int pipeA_h; 133 int pipeB_x; 134 int pipeB_y; 135 int pipeB_w; 136 int pipeB_h; 137 drm_handle_t unused_handle; 138 __u32 unused1, unused2, unused3; 139 __u32 front_bo_handle; 140 __u32 back_bo_handle; 141 __u32 unused_bo_handle; 142 __u32 depth_bo_handle; 143 } drm_i915_sarea_t; 144 #define planeA_x pipeA_x 145 #define planeA_y pipeA_y 146 #define planeA_w pipeA_w 147 #define planeA_h pipeA_h 148 #define planeB_x pipeB_x 149 #define planeB_y pipeB_y 150 #define planeB_w pipeB_w 151 #define planeB_h pipeB_h 152 #define I915_BOX_RING_EMPTY 0x1 153 #define I915_BOX_FLIP 0x2 154 #define I915_BOX_WAIT 0x4 155 #define I915_BOX_TEXTURE_LOAD 0x8 156 #define I915_BOX_LOST_CONTEXT 0x10 157 #define DRM_I915_INIT 0x00 158 #define DRM_I915_FLUSH 0x01 159 #define DRM_I915_FLIP 0x02 160 #define DRM_I915_BATCHBUFFER 0x03 161 #define DRM_I915_IRQ_EMIT 0x04 162 #define DRM_I915_IRQ_WAIT 0x05 163 #define DRM_I915_GETPARAM 0x06 164 #define DRM_I915_SETPARAM 0x07 165 #define DRM_I915_ALLOC 0x08 166 #define DRM_I915_FREE 0x09 167 #define DRM_I915_INIT_HEAP 0x0a 168 #define DRM_I915_CMDBUFFER 0x0b 169 #define DRM_I915_DESTROY_HEAP 0x0c 170 #define DRM_I915_SET_VBLANK_PIPE 0x0d 171 #define DRM_I915_GET_VBLANK_PIPE 0x0e 172 #define DRM_I915_VBLANK_SWAP 0x0f 173 #define DRM_I915_HWS_ADDR 0x11 174 #define DRM_I915_GEM_INIT 0x13 175 #define DRM_I915_GEM_EXECBUFFER 0x14 176 #define DRM_I915_GEM_PIN 0x15 177 #define DRM_I915_GEM_UNPIN 0x16 178 #define DRM_I915_GEM_BUSY 0x17 179 #define DRM_I915_GEM_THROTTLE 0x18 180 #define DRM_I915_GEM_ENTERVT 0x19 181 #define DRM_I915_GEM_LEAVEVT 0x1a 182 #define DRM_I915_GEM_CREATE 0x1b 183 #define DRM_I915_GEM_PREAD 0x1c 184 #define DRM_I915_GEM_PWRITE 0x1d 185 #define DRM_I915_GEM_MMAP 0x1e 186 #define DRM_I915_GEM_SET_DOMAIN 0x1f 187 #define DRM_I915_GEM_SW_FINISH 0x20 188 #define DRM_I915_GEM_SET_TILING 0x21 189 #define DRM_I915_GEM_GET_TILING 0x22 190 #define DRM_I915_GEM_GET_APERTURE 0x23 191 #define DRM_I915_GEM_MMAP_GTT 0x24 192 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 193 #define DRM_I915_GEM_MADVISE 0x26 194 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 195 #define DRM_I915_OVERLAY_ATTRS 0x28 196 #define DRM_I915_GEM_EXECBUFFER2 0x29 197 #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 198 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 199 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 200 #define DRM_I915_GEM_WAIT 0x2c 201 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 202 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 203 #define DRM_I915_GEM_SET_CACHING 0x2f 204 #define DRM_I915_GEM_GET_CACHING 0x30 205 #define DRM_I915_REG_READ 0x31 206 #define DRM_I915_GET_RESET_STATS 0x32 207 #define DRM_I915_GEM_USERPTR 0x33 208 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 209 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 210 #define DRM_I915_PERF_OPEN 0x36 211 #define DRM_I915_PERF_ADD_CONFIG 0x37 212 #define DRM_I915_PERF_REMOVE_CONFIG 0x38 213 #define DRM_I915_QUERY 0x39 214 #define DRM_I915_GEM_VM_CREATE 0x3a 215 #define DRM_I915_GEM_VM_DESTROY 0x3b 216 #define DRM_I915_GEM_CREATE_EXT 0x3c 217 #define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 218 #define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH) 219 #define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP) 220 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 221 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 222 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 223 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 224 #define DRM_IOCTL_I915_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 225 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 226 #define DRM_IOCTL_I915_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 227 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 228 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 229 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 230 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 231 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 232 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 233 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 234 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 235 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 236 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 237 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 238 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 239 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 240 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 241 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 242 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 243 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 244 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 245 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 246 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 247 #define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext) 248 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 249 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 250 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 251 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 252 #define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset) 253 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 254 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 255 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 256 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 257 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 258 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 259 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 260 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 261 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 262 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 263 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 264 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 265 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 266 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext) 267 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 268 #define DRM_IOCTL_I915_REG_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 269 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 270 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 271 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 272 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 273 #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 274 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) 275 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) 276 #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) 277 #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control) 278 #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control) 279 typedef struct drm_i915_batchbuffer { 280 int start; 281 int used; 282 int DR1; 283 int DR4; 284 int num_cliprects; 285 struct drm_clip_rect * cliprects; 286 } drm_i915_batchbuffer_t; 287 typedef struct _drm_i915_cmdbuffer { 288 char * buf; 289 int sz; 290 int DR1; 291 int DR4; 292 int num_cliprects; 293 struct drm_clip_rect * cliprects; 294 } drm_i915_cmdbuffer_t; 295 typedef struct drm_i915_irq_emit { 296 int * irq_seq; 297 } drm_i915_irq_emit_t; 298 typedef struct drm_i915_irq_wait { 299 int irq_seq; 300 } drm_i915_irq_wait_t; 301 #define I915_GEM_PPGTT_NONE 0 302 #define I915_GEM_PPGTT_ALIASING 1 303 #define I915_GEM_PPGTT_FULL 2 304 #define I915_PARAM_IRQ_ACTIVE 1 305 #define I915_PARAM_ALLOW_BATCHBUFFER 2 306 #define I915_PARAM_LAST_DISPATCH 3 307 #define I915_PARAM_CHIPSET_ID 4 308 #define I915_PARAM_HAS_GEM 5 309 #define I915_PARAM_NUM_FENCES_AVAIL 6 310 #define I915_PARAM_HAS_OVERLAY 7 311 #define I915_PARAM_HAS_PAGEFLIPPING 8 312 #define I915_PARAM_HAS_EXECBUF2 9 313 #define I915_PARAM_HAS_BSD 10 314 #define I915_PARAM_HAS_BLT 11 315 #define I915_PARAM_HAS_RELAXED_FENCING 12 316 #define I915_PARAM_HAS_COHERENT_RINGS 13 317 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 318 #define I915_PARAM_HAS_RELAXED_DELTA 15 319 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 320 #define I915_PARAM_HAS_LLC 17 321 #define I915_PARAM_HAS_ALIASING_PPGTT 18 322 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 323 #define I915_PARAM_HAS_SEMAPHORES 20 324 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 325 #define I915_PARAM_HAS_VEBOX 22 326 #define I915_PARAM_HAS_SECURE_BATCHES 23 327 #define I915_PARAM_HAS_PINNED_BATCHES 24 328 #define I915_PARAM_HAS_EXEC_NO_RELOC 25 329 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 330 #define I915_PARAM_HAS_WT 27 331 #define I915_PARAM_CMD_PARSER_VERSION 28 332 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 333 #define I915_PARAM_MMAP_VERSION 30 334 #define I915_PARAM_HAS_BSD2 31 335 #define I915_PARAM_REVISION 32 336 #define I915_PARAM_SUBSLICE_TOTAL 33 337 #define I915_PARAM_EU_TOTAL 34 338 #define I915_PARAM_HAS_GPU_RESET 35 339 #define I915_PARAM_HAS_RESOURCE_STREAMER 36 340 #define I915_PARAM_HAS_EXEC_SOFTPIN 37 341 #define I915_PARAM_HAS_POOLED_EU 38 342 #define I915_PARAM_MIN_EU_IN_POOL 39 343 #define I915_PARAM_MMAP_GTT_VERSION 40 344 #define I915_PARAM_HAS_SCHEDULER 41 345 #define I915_SCHEDULER_CAP_ENABLED (1ul << 0) 346 #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) 347 #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) 348 #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) 349 #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) 350 #define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5) 351 #define I915_PARAM_HUC_STATUS 42 352 #define I915_PARAM_HAS_EXEC_ASYNC 43 353 #define I915_PARAM_HAS_EXEC_FENCE 44 354 #define I915_PARAM_HAS_EXEC_CAPTURE 45 355 #define I915_PARAM_SLICE_MASK 46 356 #define I915_PARAM_SUBSLICE_MASK 47 357 #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 358 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 359 #define I915_PARAM_HAS_CONTEXT_ISOLATION 50 360 #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 361 #define I915_PARAM_MMAP_GTT_COHERENT 52 362 #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53 363 #define I915_PARAM_PERF_REVISION 54 364 #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55 365 #define I915_PARAM_HAS_USERPTR_PROBE 56 366 #define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57 367 #define I915_PARAM_PXP_STATUS 58 368 #define I915_PARAM_HAS_CONTEXT_FREQ_HINT 59 369 struct drm_i915_getparam { 370 __s32 param; 371 int * value; 372 }; 373 typedef struct drm_i915_getparam drm_i915_getparam_t; 374 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 375 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 376 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 377 #define I915_SETPARAM_NUM_USED_FENCES 4 378 typedef struct drm_i915_setparam { 379 int param; 380 int value; 381 } drm_i915_setparam_t; 382 #define I915_MEM_REGION_AGP 1 383 typedef struct drm_i915_mem_alloc { 384 int region; 385 int alignment; 386 int size; 387 int * region_offset; 388 } drm_i915_mem_alloc_t; 389 typedef struct drm_i915_mem_free { 390 int region; 391 int region_offset; 392 } drm_i915_mem_free_t; 393 typedef struct drm_i915_mem_init_heap { 394 int region; 395 int size; 396 int start; 397 } drm_i915_mem_init_heap_t; 398 typedef struct drm_i915_mem_destroy_heap { 399 int region; 400 } drm_i915_mem_destroy_heap_t; 401 #define DRM_I915_VBLANK_PIPE_A 1 402 #define DRM_I915_VBLANK_PIPE_B 2 403 typedef struct drm_i915_vblank_pipe { 404 int pipe; 405 } drm_i915_vblank_pipe_t; 406 typedef struct drm_i915_vblank_swap { 407 drm_drawable_t drawable; 408 enum drm_vblank_seq_type seqtype; 409 unsigned int sequence; 410 } drm_i915_vblank_swap_t; 411 typedef struct drm_i915_hws_addr { 412 __u64 addr; 413 } drm_i915_hws_addr_t; 414 struct drm_i915_gem_init { 415 __u64 gtt_start; 416 __u64 gtt_end; 417 }; 418 struct drm_i915_gem_create { 419 __u64 size; 420 __u32 handle; 421 __u32 pad; 422 }; 423 struct drm_i915_gem_pread { 424 __u32 handle; 425 __u32 pad; 426 __u64 offset; 427 __u64 size; 428 __u64 data_ptr; 429 }; 430 struct drm_i915_gem_pwrite { 431 __u32 handle; 432 __u32 pad; 433 __u64 offset; 434 __u64 size; 435 __u64 data_ptr; 436 }; 437 struct drm_i915_gem_mmap { 438 __u32 handle; 439 __u32 pad; 440 __u64 offset; 441 __u64 size; 442 __u64 addr_ptr; 443 __u64 flags; 444 #define I915_MMAP_WC 0x1 445 }; 446 struct drm_i915_gem_mmap_gtt { 447 __u32 handle; 448 __u32 pad; 449 __u64 offset; 450 }; 451 struct drm_i915_gem_mmap_offset { 452 __u32 handle; 453 __u32 pad; 454 __u64 offset; 455 __u64 flags; 456 #define I915_MMAP_OFFSET_GTT 0 457 #define I915_MMAP_OFFSET_WC 1 458 #define I915_MMAP_OFFSET_WB 2 459 #define I915_MMAP_OFFSET_UC 3 460 #define I915_MMAP_OFFSET_FIXED 4 461 __u64 extensions; 462 }; 463 struct drm_i915_gem_set_domain { 464 __u32 handle; 465 __u32 read_domains; 466 __u32 write_domain; 467 }; 468 struct drm_i915_gem_sw_finish { 469 __u32 handle; 470 }; 471 struct drm_i915_gem_relocation_entry { 472 __u32 target_handle; 473 __u32 delta; 474 __u64 offset; 475 __u64 presumed_offset; 476 __u32 read_domains; 477 __u32 write_domain; 478 }; 479 #define I915_GEM_DOMAIN_CPU 0x00000001 480 #define I915_GEM_DOMAIN_RENDER 0x00000002 481 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 482 #define I915_GEM_DOMAIN_COMMAND 0x00000008 483 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 484 #define I915_GEM_DOMAIN_VERTEX 0x00000020 485 #define I915_GEM_DOMAIN_GTT 0x00000040 486 #define I915_GEM_DOMAIN_WC 0x00000080 487 struct drm_i915_gem_exec_object { 488 __u32 handle; 489 __u32 relocation_count; 490 __u64 relocs_ptr; 491 __u64 alignment; 492 __u64 offset; 493 }; 494 struct drm_i915_gem_execbuffer { 495 __u64 buffers_ptr; 496 __u32 buffer_count; 497 __u32 batch_start_offset; 498 __u32 batch_len; 499 __u32 DR1; 500 __u32 DR4; 501 __u32 num_cliprects; 502 __u64 cliprects_ptr; 503 }; 504 struct drm_i915_gem_exec_object2 { 505 __u32 handle; 506 __u32 relocation_count; 507 __u64 relocs_ptr; 508 __u64 alignment; 509 __u64 offset; 510 #define EXEC_OBJECT_NEEDS_FENCE (1 << 0) 511 #define EXEC_OBJECT_NEEDS_GTT (1 << 1) 512 #define EXEC_OBJECT_WRITE (1 << 2) 513 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1 << 3) 514 #define EXEC_OBJECT_PINNED (1 << 4) 515 #define EXEC_OBJECT_PAD_TO_SIZE (1 << 5) 516 #define EXEC_OBJECT_ASYNC (1 << 6) 517 #define EXEC_OBJECT_CAPTURE (1 << 7) 518 #define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_CAPTURE << 1) 519 __u64 flags; 520 union { 521 __u64 rsvd1; 522 __u64 pad_to_size; 523 }; 524 __u64 rsvd2; 525 }; 526 struct drm_i915_gem_exec_fence { 527 __u32 handle; 528 __u32 flags; 529 #define I915_EXEC_FENCE_WAIT (1 << 0) 530 #define I915_EXEC_FENCE_SIGNAL (1 << 1) 531 #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (- (I915_EXEC_FENCE_SIGNAL << 1)) 532 }; 533 struct drm_i915_gem_execbuffer_ext_timeline_fences { 534 #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0 535 struct i915_user_extension base; 536 __u64 fence_count; 537 __u64 handles_ptr; 538 __u64 values_ptr; 539 }; 540 struct drm_i915_gem_execbuffer2 { 541 __u64 buffers_ptr; 542 __u32 buffer_count; 543 __u32 batch_start_offset; 544 __u32 batch_len; 545 __u32 DR1; 546 __u32 DR4; 547 __u32 num_cliprects; 548 __u64 cliprects_ptr; 549 __u64 flags; 550 #define I915_EXEC_RING_MASK (0x3f) 551 #define I915_EXEC_DEFAULT (0 << 0) 552 #define I915_EXEC_RENDER (1 << 0) 553 #define I915_EXEC_BSD (2 << 0) 554 #define I915_EXEC_BLT (3 << 0) 555 #define I915_EXEC_VEBOX (4 << 0) 556 #define I915_EXEC_CONSTANTS_MASK (3 << 6) 557 #define I915_EXEC_CONSTANTS_REL_GENERAL (0 << 6) 558 #define I915_EXEC_CONSTANTS_ABSOLUTE (1 << 6) 559 #define I915_EXEC_CONSTANTS_REL_SURFACE (2 << 6) 560 #define I915_EXEC_GEN7_SOL_RESET (1 << 8) 561 #define I915_EXEC_SECURE (1 << 9) 562 #define I915_EXEC_IS_PINNED (1 << 10) 563 #define I915_EXEC_NO_RELOC (1 << 11) 564 #define I915_EXEC_HANDLE_LUT (1 << 12) 565 #define I915_EXEC_BSD_SHIFT (13) 566 #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 567 #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 568 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 569 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 570 #define I915_EXEC_RESOURCE_STREAMER (1 << 15) 571 #define I915_EXEC_FENCE_IN (1 << 16) 572 #define I915_EXEC_FENCE_OUT (1 << 17) 573 #define I915_EXEC_BATCH_FIRST (1 << 18) 574 #define I915_EXEC_FENCE_ARRAY (1 << 19) 575 #define I915_EXEC_FENCE_SUBMIT (1 << 20) 576 #define I915_EXEC_USE_EXTENSIONS (1 << 21) 577 #define __I915_EXEC_UNKNOWN_FLAGS (- (I915_EXEC_USE_EXTENSIONS << 1)) 578 __u64 rsvd1; 579 __u64 rsvd2; 580 }; 581 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 582 #define i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 583 #define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 584 struct drm_i915_gem_pin { 585 __u32 handle; 586 __u32 pad; 587 __u64 alignment; 588 __u64 offset; 589 }; 590 struct drm_i915_gem_unpin { 591 __u32 handle; 592 __u32 pad; 593 }; 594 struct drm_i915_gem_busy { 595 __u32 handle; 596 __u32 busy; 597 }; 598 struct drm_i915_gem_caching { 599 __u32 handle; 600 #define I915_CACHING_NONE 0 601 #define I915_CACHING_CACHED 1 602 #define I915_CACHING_DISPLAY 2 603 __u32 caching; 604 }; 605 #define I915_TILING_NONE 0 606 #define I915_TILING_X 1 607 #define I915_TILING_Y 2 608 #define I915_TILING_LAST I915_TILING_Y 609 #define I915_BIT_6_SWIZZLE_NONE 0 610 #define I915_BIT_6_SWIZZLE_9 1 611 #define I915_BIT_6_SWIZZLE_9_10 2 612 #define I915_BIT_6_SWIZZLE_9_11 3 613 #define I915_BIT_6_SWIZZLE_9_10_11 4 614 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 615 #define I915_BIT_6_SWIZZLE_9_17 6 616 #define I915_BIT_6_SWIZZLE_9_10_17 7 617 struct drm_i915_gem_set_tiling { 618 __u32 handle; 619 __u32 tiling_mode; 620 __u32 stride; 621 __u32 swizzle_mode; 622 }; 623 struct drm_i915_gem_get_tiling { 624 __u32 handle; 625 __u32 tiling_mode; 626 __u32 swizzle_mode; 627 __u32 phys_swizzle_mode; 628 }; 629 struct drm_i915_gem_get_aperture { 630 __u64 aper_size; 631 __u64 aper_available_size; 632 }; 633 struct drm_i915_get_pipe_from_crtc_id { 634 __u32 crtc_id; 635 __u32 pipe; 636 }; 637 #define I915_MADV_WILLNEED 0 638 #define I915_MADV_DONTNEED 1 639 #define __I915_MADV_PURGED 2 640 struct drm_i915_gem_madvise { 641 __u32 handle; 642 __u32 madv; 643 __u32 retained; 644 }; 645 #define I915_OVERLAY_TYPE_MASK 0xff 646 #define I915_OVERLAY_YUV_PLANAR 0x01 647 #define I915_OVERLAY_YUV_PACKED 0x02 648 #define I915_OVERLAY_RGB 0x03 649 #define I915_OVERLAY_DEPTH_MASK 0xff00 650 #define I915_OVERLAY_RGB24 0x1000 651 #define I915_OVERLAY_RGB16 0x2000 652 #define I915_OVERLAY_RGB15 0x3000 653 #define I915_OVERLAY_YUV422 0x0100 654 #define I915_OVERLAY_YUV411 0x0200 655 #define I915_OVERLAY_YUV420 0x0300 656 #define I915_OVERLAY_YUV410 0x0400 657 #define I915_OVERLAY_SWAP_MASK 0xff0000 658 #define I915_OVERLAY_NO_SWAP 0x000000 659 #define I915_OVERLAY_UV_SWAP 0x010000 660 #define I915_OVERLAY_Y_SWAP 0x020000 661 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 662 #define I915_OVERLAY_FLAGS_MASK 0xff000000 663 #define I915_OVERLAY_ENABLE 0x01000000 664 struct drm_intel_overlay_put_image { 665 __u32 flags; 666 __u32 bo_handle; 667 __u16 stride_Y; 668 __u16 stride_UV; 669 __u32 offset_Y; 670 __u32 offset_U; 671 __u32 offset_V; 672 __u16 src_width; 673 __u16 src_height; 674 __u16 src_scan_width; 675 __u16 src_scan_height; 676 __u32 crtc_id; 677 __u16 dst_x; 678 __u16 dst_y; 679 __u16 dst_width; 680 __u16 dst_height; 681 }; 682 #define I915_OVERLAY_UPDATE_ATTRS (1 << 0) 683 #define I915_OVERLAY_UPDATE_GAMMA (1 << 1) 684 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1 << 2) 685 struct drm_intel_overlay_attrs { 686 __u32 flags; 687 __u32 color_key; 688 __s32 brightness; 689 __u32 contrast; 690 __u32 saturation; 691 __u32 gamma0; 692 __u32 gamma1; 693 __u32 gamma2; 694 __u32 gamma3; 695 __u32 gamma4; 696 __u32 gamma5; 697 }; 698 #define I915_SET_COLORKEY_NONE (1 << 0) 699 #define I915_SET_COLORKEY_DESTINATION (1 << 1) 700 #define I915_SET_COLORKEY_SOURCE (1 << 2) 701 struct drm_intel_sprite_colorkey { 702 __u32 plane_id; 703 __u32 min_value; 704 __u32 channel_mask; 705 __u32 max_value; 706 __u32 flags; 707 }; 708 struct drm_i915_gem_wait { 709 __u32 bo_handle; 710 __u32 flags; 711 __s64 timeout_ns; 712 }; 713 struct drm_i915_gem_context_create { 714 __u32 ctx_id; 715 __u32 pad; 716 }; 717 struct drm_i915_gem_context_create_ext { 718 __u32 ctx_id; 719 __u32 flags; 720 #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0) 721 #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1) 722 #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN (- (I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)) 723 __u64 extensions; 724 #define I915_CONTEXT_CREATE_EXT_SETPARAM 0 725 #define I915_CONTEXT_CREATE_EXT_CLONE 1 726 }; 727 struct drm_i915_gem_context_param { 728 __u32 ctx_id; 729 __u32 size; 730 __u64 param; 731 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 732 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 733 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 734 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 735 #define I915_CONTEXT_PARAM_BANNABLE 0x5 736 #define I915_CONTEXT_PARAM_PRIORITY 0x6 737 #define I915_CONTEXT_MAX_USER_PRIORITY 1023 738 #define I915_CONTEXT_DEFAULT_PRIORITY 0 739 #define I915_CONTEXT_MIN_USER_PRIORITY - 1023 740 #define I915_CONTEXT_PARAM_SSEU 0x7 741 #define I915_CONTEXT_PARAM_RECOVERABLE 0x8 742 #define I915_CONTEXT_PARAM_VM 0x9 743 #define I915_CONTEXT_PARAM_ENGINES 0xa 744 #define I915_CONTEXT_PARAM_PERSISTENCE 0xb 745 #define I915_CONTEXT_PARAM_RINGSIZE 0xc 746 #define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd 747 #define I915_CONTEXT_PARAM_LOW_LATENCY 0xe 748 #define I915_CONTEXT_PARAM_CONTEXT_IMAGE 0xf 749 __u64 value; 750 }; 751 struct drm_i915_gem_context_param_sseu { 752 struct i915_engine_class_instance engine; 753 __u32 flags; 754 #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0) 755 __u64 slice_mask; 756 __u64 subslice_mask; 757 __u16 min_eus_per_subslice; 758 __u16 max_eus_per_subslice; 759 __u32 rsvd; 760 }; 761 struct i915_context_engines_load_balance { 762 struct i915_user_extension base; 763 __u16 engine_index; 764 __u16 num_siblings; 765 __u32 flags; 766 __u64 mbz64; 767 struct i915_engine_class_instance engines[]; 768 } __attribute__((packed)); 769 #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__,N__) struct { struct i915_user_extension base; __u16 engine_index; __u16 num_siblings; __u32 flags; __u64 mbz64; struct i915_engine_class_instance engines[N__]; \ 770 } __attribute__((packed)) name__ 771 struct i915_context_engines_bond { 772 struct i915_user_extension base; 773 struct i915_engine_class_instance master; 774 __u16 virtual_index; 775 __u16 num_bonds; 776 __u64 flags; 777 __u64 mbz64[4]; 778 struct i915_engine_class_instance engines[]; 779 } __attribute__((packed)); 780 #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__,N__) struct { struct i915_user_extension base; struct i915_engine_class_instance master; __u16 virtual_index; __u16 num_bonds; __u64 flags; __u64 mbz64[4]; struct i915_engine_class_instance engines[N__]; \ 781 } __attribute__((packed)) name__ 782 struct i915_context_engines_parallel_submit { 783 struct i915_user_extension base; 784 __u16 engine_index; 785 __u16 width; 786 __u16 num_siblings; 787 __u16 mbz16; 788 __u64 flags; 789 __u64 mbz64[3]; 790 struct i915_engine_class_instance engines[]; 791 } __attribute__((__packed__)); 792 #define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__,N__) struct { struct i915_user_extension base; __u16 engine_index; __u16 width; __u16 num_siblings; __u16 mbz16; __u64 flags; __u64 mbz64[3]; struct i915_engine_class_instance engines[N__]; \ 793 } __attribute__((packed)) name__ 794 struct i915_context_param_engines { 795 __u64 extensions; 796 #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 797 #define I915_CONTEXT_ENGINES_EXT_BOND 1 798 #define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 799 struct i915_engine_class_instance engines[]; 800 } __attribute__((packed)); 801 #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__,N__) struct { __u64 extensions; struct i915_engine_class_instance engines[N__]; \ 802 } __attribute__((packed)) name__ 803 struct i915_gem_context_param_context_image { 804 struct i915_engine_class_instance engine; 805 __u32 flags; 806 #define I915_CONTEXT_IMAGE_FLAG_ENGINE_INDEX (1u << 0) 807 __u32 size; 808 __u32 mbz; 809 __u64 image; 810 } __attribute__((packed)); 811 struct drm_i915_gem_context_create_ext_setparam { 812 struct i915_user_extension base; 813 struct drm_i915_gem_context_param param; 814 }; 815 struct drm_i915_gem_context_destroy { 816 __u32 ctx_id; 817 __u32 pad; 818 }; 819 struct drm_i915_gem_vm_control { 820 __u64 extensions; 821 __u32 flags; 822 __u32 vm_id; 823 }; 824 struct drm_i915_reg_read { 825 __u64 offset; 826 #define I915_REG_READ_8B_WA (1ul << 0) 827 __u64 val; 828 }; 829 struct drm_i915_reset_stats { 830 __u32 ctx_id; 831 __u32 flags; 832 __u32 reset_count; 833 __u32 batch_active; 834 __u32 batch_pending; 835 __u32 pad; 836 }; 837 struct drm_i915_gem_userptr { 838 __u64 user_ptr; 839 __u64 user_size; 840 __u32 flags; 841 #define I915_USERPTR_READ_ONLY 0x1 842 #define I915_USERPTR_PROBE 0x2 843 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 844 __u32 handle; 845 }; 846 enum drm_i915_oa_format { 847 I915_OA_FORMAT_A13 = 1, 848 I915_OA_FORMAT_A29, 849 I915_OA_FORMAT_A13_B8_C8, 850 I915_OA_FORMAT_B4_C8, 851 I915_OA_FORMAT_A45_B8_C8, 852 I915_OA_FORMAT_B4_C8_A16, 853 I915_OA_FORMAT_C4_B8, 854 I915_OA_FORMAT_A12, 855 I915_OA_FORMAT_A12_B8_C8, 856 I915_OA_FORMAT_A32u40_A4u32_B8_C8, 857 I915_OAR_FORMAT_A32u40_A4u32_B8_C8, 858 I915_OA_FORMAT_A24u40_A14u32_B8_C8, 859 I915_OAM_FORMAT_MPEC8u64_B8_C8, 860 I915_OAM_FORMAT_MPEC8u32_B8_C8, 861 I915_OA_FORMAT_MAX 862 }; 863 enum drm_i915_perf_property_id { 864 DRM_I915_PERF_PROP_CTX_HANDLE = 1, 865 DRM_I915_PERF_PROP_SAMPLE_OA, 866 DRM_I915_PERF_PROP_OA_METRICS_SET, 867 DRM_I915_PERF_PROP_OA_FORMAT, 868 DRM_I915_PERF_PROP_OA_EXPONENT, 869 DRM_I915_PERF_PROP_HOLD_PREEMPTION, 870 DRM_I915_PERF_PROP_GLOBAL_SSEU, 871 DRM_I915_PERF_PROP_POLL_OA_PERIOD, 872 DRM_I915_PERF_PROP_OA_ENGINE_CLASS, 873 DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE, 874 DRM_I915_PERF_PROP_MAX 875 }; 876 struct drm_i915_perf_open_param { 877 __u32 flags; 878 #define I915_PERF_FLAG_FD_CLOEXEC (1 << 0) 879 #define I915_PERF_FLAG_FD_NONBLOCK (1 << 1) 880 #define I915_PERF_FLAG_DISABLED (1 << 2) 881 __u32 num_properties; 882 __u64 properties_ptr; 883 }; 884 #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 885 #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 886 #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2) 887 struct drm_i915_perf_record_header { 888 __u32 type; 889 __u16 pad; 890 __u16 size; 891 }; 892 enum drm_i915_perf_record_type { 893 DRM_I915_PERF_RECORD_SAMPLE = 1, 894 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 895 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 896 DRM_I915_PERF_RECORD_MAX 897 }; 898 struct drm_i915_perf_oa_config { 899 char uuid[36]; 900 __u32 n_mux_regs; 901 __u32 n_boolean_regs; 902 __u32 n_flex_regs; 903 __u64 mux_regs_ptr; 904 __u64 boolean_regs_ptr; 905 __u64 flex_regs_ptr; 906 }; 907 struct drm_i915_query_item { 908 __u64 query_id; 909 #define DRM_I915_QUERY_TOPOLOGY_INFO 1 910 #define DRM_I915_QUERY_ENGINE_INFO 2 911 #define DRM_I915_QUERY_PERF_CONFIG 3 912 #define DRM_I915_QUERY_MEMORY_REGIONS 4 913 #define DRM_I915_QUERY_HWCONFIG_BLOB 5 914 #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6 915 #define DRM_I915_QUERY_GUC_SUBMISSION_VERSION 7 916 __s32 length; 917 __u32 flags; 918 #define DRM_I915_QUERY_PERF_CONFIG_LIST 1 919 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2 920 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3 921 __u64 data_ptr; 922 }; 923 struct drm_i915_query { 924 __u32 num_items; 925 __u32 flags; 926 __u64 items_ptr; 927 }; 928 struct drm_i915_query_topology_info { 929 __u16 flags; 930 __u16 max_slices; 931 __u16 max_subslices; 932 __u16 max_eus_per_subslice; 933 __u16 subslice_offset; 934 __u16 subslice_stride; 935 __u16 eu_offset; 936 __u16 eu_stride; 937 __u8 data[]; 938 }; 939 struct drm_i915_engine_info { 940 struct i915_engine_class_instance engine; 941 __u32 rsvd0; 942 __u64 flags; 943 #define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0) 944 __u64 capabilities; 945 #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) 946 #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) 947 __u16 logical_instance; 948 __u16 rsvd1[3]; 949 __u64 rsvd2[3]; 950 }; 951 struct drm_i915_query_engine_info { 952 __u32 num_engines; 953 __u32 rsvd[3]; 954 struct drm_i915_engine_info engines[]; 955 }; 956 struct drm_i915_query_perf_config { 957 union { 958 __u64 n_configs; 959 __u64 config; 960 char uuid[36]; 961 }; 962 __u32 flags; 963 __u8 data[]; 964 }; 965 enum drm_i915_gem_memory_class { 966 I915_MEMORY_CLASS_SYSTEM = 0, 967 I915_MEMORY_CLASS_DEVICE, 968 }; 969 struct drm_i915_gem_memory_class_instance { 970 __u16 memory_class; 971 __u16 memory_instance; 972 }; 973 struct drm_i915_memory_region_info { 974 struct drm_i915_gem_memory_class_instance region; 975 __u32 rsvd0; 976 __u64 probed_size; 977 __u64 unallocated_size; 978 union { 979 __u64 rsvd1[8]; 980 struct { 981 __u64 probed_cpu_visible_size; 982 __u64 unallocated_cpu_visible_size; 983 }; 984 }; 985 }; 986 struct drm_i915_query_memory_regions { 987 __u32 num_regions; 988 __u32 rsvd[3]; 989 struct drm_i915_memory_region_info regions[]; 990 }; 991 struct drm_i915_query_guc_submission_version { 992 __u32 branch; 993 __u32 major; 994 __u32 minor; 995 __u32 patch; 996 }; 997 struct drm_i915_gem_create_ext { 998 __u64 size; 999 __u32 handle; 1000 #define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0) 1001 __u32 flags; 1002 #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0 1003 #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1 1004 #define I915_GEM_CREATE_EXT_SET_PAT 2 1005 __u64 extensions; 1006 }; 1007 struct drm_i915_gem_create_ext_memory_regions { 1008 struct i915_user_extension base; 1009 __u32 pad; 1010 __u32 num_regions; 1011 __u64 regions; 1012 }; 1013 struct drm_i915_gem_create_ext_protected_content { 1014 struct i915_user_extension base; 1015 __u32 flags; 1016 }; 1017 struct drm_i915_gem_create_ext_set_pat { 1018 struct i915_user_extension base; 1019 __u32 pat_index; 1020 __u32 rsvd; 1021 }; 1022 #define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf 1023 #ifdef __cplusplus 1024 } 1025 #endif 1026 #endif 1027