1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __RADEON_DRM_H__ 8 #define __RADEON_DRM_H__ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #ifndef __RADEON_SAREA_DEFINES__ 14 #define __RADEON_SAREA_DEFINES__ 15 #define RADEON_UPLOAD_CONTEXT 0x00000001 16 #define RADEON_UPLOAD_VERTFMT 0x00000002 17 #define RADEON_UPLOAD_LINE 0x00000004 18 #define RADEON_UPLOAD_BUMPMAP 0x00000008 19 #define RADEON_UPLOAD_MASKS 0x00000010 20 #define RADEON_UPLOAD_VIEWPORT 0x00000020 21 #define RADEON_UPLOAD_SETUP 0x00000040 22 #define RADEON_UPLOAD_TCL 0x00000080 23 #define RADEON_UPLOAD_MISC 0x00000100 24 #define RADEON_UPLOAD_TEX0 0x00000200 25 #define RADEON_UPLOAD_TEX1 0x00000400 26 #define RADEON_UPLOAD_TEX2 0x00000800 27 #define RADEON_UPLOAD_TEX0IMAGES 0x00001000 28 #define RADEON_UPLOAD_TEX1IMAGES 0x00002000 29 #define RADEON_UPLOAD_TEX2IMAGES 0x00004000 30 #define RADEON_UPLOAD_CLIPRECTS 0x00008000 31 #define RADEON_REQUIRE_QUIESCENCE 0x00010000 32 #define RADEON_UPLOAD_ZBIAS 0x00020000 33 #define RADEON_UPLOAD_ALL 0x003effff 34 #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 35 #define RADEON_EMIT_PP_MISC 0 36 #define RADEON_EMIT_PP_CNTL 1 37 #define RADEON_EMIT_RB3D_COLORPITCH 2 38 #define RADEON_EMIT_RE_LINE_PATTERN 3 39 #define RADEON_EMIT_SE_LINE_WIDTH 4 40 #define RADEON_EMIT_PP_LUM_MATRIX 5 41 #define RADEON_EMIT_PP_ROT_MATRIX_0 6 42 #define RADEON_EMIT_RB3D_STENCILREFMASK 7 43 #define RADEON_EMIT_SE_VPORT_XSCALE 8 44 #define RADEON_EMIT_SE_CNTL 9 45 #define RADEON_EMIT_SE_CNTL_STATUS 10 46 #define RADEON_EMIT_RE_MISC 11 47 #define RADEON_EMIT_PP_TXFILTER_0 12 48 #define RADEON_EMIT_PP_BORDER_COLOR_0 13 49 #define RADEON_EMIT_PP_TXFILTER_1 14 50 #define RADEON_EMIT_PP_BORDER_COLOR_1 15 51 #define RADEON_EMIT_PP_TXFILTER_2 16 52 #define RADEON_EMIT_PP_BORDER_COLOR_2 17 53 #define RADEON_EMIT_SE_ZBIAS_FACTOR 18 54 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 55 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 56 #define R200_EMIT_PP_TXCBLEND_0 21 57 #define R200_EMIT_PP_TXCBLEND_1 22 58 #define R200_EMIT_PP_TXCBLEND_2 23 59 #define R200_EMIT_PP_TXCBLEND_3 24 60 #define R200_EMIT_PP_TXCBLEND_4 25 61 #define R200_EMIT_PP_TXCBLEND_5 26 62 #define R200_EMIT_PP_TXCBLEND_6 27 63 #define R200_EMIT_PP_TXCBLEND_7 28 64 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 65 #define R200_EMIT_TFACTOR_0 30 66 #define R200_EMIT_VTX_FMT_0 31 67 #define R200_EMIT_VAP_CTL 32 68 #define R200_EMIT_MATRIX_SELECT_0 33 69 #define R200_EMIT_TEX_PROC_CTL_2 34 70 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 71 #define R200_EMIT_PP_TXFILTER_0 36 72 #define R200_EMIT_PP_TXFILTER_1 37 73 #define R200_EMIT_PP_TXFILTER_2 38 74 #define R200_EMIT_PP_TXFILTER_3 39 75 #define R200_EMIT_PP_TXFILTER_4 40 76 #define R200_EMIT_PP_TXFILTER_5 41 77 #define R200_EMIT_PP_TXOFFSET_0 42 78 #define R200_EMIT_PP_TXOFFSET_1 43 79 #define R200_EMIT_PP_TXOFFSET_2 44 80 #define R200_EMIT_PP_TXOFFSET_3 45 81 #define R200_EMIT_PP_TXOFFSET_4 46 82 #define R200_EMIT_PP_TXOFFSET_5 47 83 #define R200_EMIT_VTE_CNTL 48 84 #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 85 #define R200_EMIT_PP_TAM_DEBUG3 50 86 #define R200_EMIT_PP_CNTL_X 51 87 #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 88 #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 89 #define R200_EMIT_RE_SCISSOR_TL_0 54 90 #define R200_EMIT_RE_SCISSOR_TL_1 55 91 #define R200_EMIT_RE_SCISSOR_TL_2 56 92 #define R200_EMIT_SE_VAP_CNTL_STATUS 57 93 #define R200_EMIT_SE_VTX_STATE_CNTL 58 94 #define R200_EMIT_RE_POINTSIZE 59 95 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 96 #define R200_EMIT_PP_CUBIC_FACES_0 61 97 #define R200_EMIT_PP_CUBIC_OFFSETS_0 62 98 #define R200_EMIT_PP_CUBIC_FACES_1 63 99 #define R200_EMIT_PP_CUBIC_OFFSETS_1 64 100 #define R200_EMIT_PP_CUBIC_FACES_2 65 101 #define R200_EMIT_PP_CUBIC_OFFSETS_2 66 102 #define R200_EMIT_PP_CUBIC_FACES_3 67 103 #define R200_EMIT_PP_CUBIC_OFFSETS_3 68 104 #define R200_EMIT_PP_CUBIC_FACES_4 69 105 #define R200_EMIT_PP_CUBIC_OFFSETS_4 70 106 #define R200_EMIT_PP_CUBIC_FACES_5 71 107 #define R200_EMIT_PP_CUBIC_OFFSETS_5 72 108 #define RADEON_EMIT_PP_TEX_SIZE_0 73 109 #define RADEON_EMIT_PP_TEX_SIZE_1 74 110 #define RADEON_EMIT_PP_TEX_SIZE_2 75 111 #define R200_EMIT_RB3D_BLENDCOLOR 76 112 #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 113 #define RADEON_EMIT_PP_CUBIC_FACES_0 78 114 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 115 #define RADEON_EMIT_PP_CUBIC_FACES_1 80 116 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 117 #define RADEON_EMIT_PP_CUBIC_FACES_2 82 118 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 119 #define R200_EMIT_PP_TRI_PERF_CNTL 84 120 #define R200_EMIT_PP_AFS_0 85 121 #define R200_EMIT_PP_AFS_1 86 122 #define R200_EMIT_ATF_TFACTOR 87 123 #define R200_EMIT_PP_TXCTLALL_0 88 124 #define R200_EMIT_PP_TXCTLALL_1 89 125 #define R200_EMIT_PP_TXCTLALL_2 90 126 #define R200_EMIT_PP_TXCTLALL_3 91 127 #define R200_EMIT_PP_TXCTLALL_4 92 128 #define R200_EMIT_PP_TXCTLALL_5 93 129 #define R200_EMIT_VAP_PVS_CNTL 94 130 #define RADEON_MAX_STATE_PACKETS 95 131 #define RADEON_CMD_PACKET 1 132 #define RADEON_CMD_SCALARS 2 133 #define RADEON_CMD_VECTORS 3 134 #define RADEON_CMD_DMA_DISCARD 4 135 #define RADEON_CMD_PACKET3 5 136 #define RADEON_CMD_PACKET3_CLIP 6 137 #define RADEON_CMD_SCALARS2 7 138 #define RADEON_CMD_WAIT 8 139 #define RADEON_CMD_VECLINEAR 9 140 typedef union { 141 int i; 142 struct { 143 unsigned char cmd_type, pad0, pad1, pad2; 144 } header; 145 struct { 146 unsigned char cmd_type, packet_id, pad0, pad1; 147 } packet; 148 struct { 149 unsigned char cmd_type, offset, stride, count; 150 } scalars; 151 struct { 152 unsigned char cmd_type, offset, stride, count; 153 } vectors; 154 struct { 155 unsigned char cmd_type, addr_lo, addr_hi, count; 156 } veclinear; 157 struct { 158 unsigned char cmd_type, buf_idx, pad0, pad1; 159 } dma; 160 struct { 161 unsigned char cmd_type, flags, pad0, pad1; 162 } wait; 163 } drm_radeon_cmd_header_t; 164 #define RADEON_WAIT_2D 0x1 165 #define RADEON_WAIT_3D 0x2 166 #define R300_CMD_PACKET3_CLEAR 0 167 #define R300_CMD_PACKET3_RAW 1 168 #define R300_CMD_PACKET0 1 169 #define R300_CMD_VPU 2 170 #define R300_CMD_PACKET3 3 171 #define R300_CMD_END3D 4 172 #define R300_CMD_CP_DELAY 5 173 #define R300_CMD_DMA_DISCARD 6 174 #define R300_CMD_WAIT 7 175 #define R300_WAIT_2D 0x1 176 #define R300_WAIT_3D 0x2 177 #define R300_WAIT_2D_CLEAN 0x3 178 #define R300_WAIT_3D_CLEAN 0x4 179 #define R300_NEW_WAIT_2D_3D 0x3 180 #define R300_NEW_WAIT_2D_2D_CLEAN 0x4 181 #define R300_NEW_WAIT_3D_3D_CLEAN 0x6 182 #define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 183 #define R300_CMD_SCRATCH 8 184 #define R300_CMD_R500FP 9 185 typedef union { 186 unsigned int u; 187 struct { 188 unsigned char cmd_type, pad0, pad1, pad2; 189 } header; 190 struct { 191 unsigned char cmd_type, count, reglo, reghi; 192 } packet0; 193 struct { 194 unsigned char cmd_type, count, adrlo, adrhi; 195 } vpu; 196 struct { 197 unsigned char cmd_type, packet, pad0, pad1; 198 } packet3; 199 struct { 200 unsigned char cmd_type, packet; 201 unsigned short count; 202 } delay; 203 struct { 204 unsigned char cmd_type, buf_idx, pad0, pad1; 205 } dma; 206 struct { 207 unsigned char cmd_type, flags, pad0, pad1; 208 } wait; 209 struct { 210 unsigned char cmd_type, reg, n_bufs, flags; 211 } scratch; 212 struct { 213 unsigned char cmd_type, count, adrlo, adrhi_flags; 214 } r500fp; 215 } drm_r300_cmd_header_t; 216 #define RADEON_FRONT 0x1 217 #define RADEON_BACK 0x2 218 #define RADEON_DEPTH 0x4 219 #define RADEON_STENCIL 0x8 220 #define RADEON_CLEAR_FASTZ 0x80000000 221 #define RADEON_USE_HIERZ 0x40000000 222 #define RADEON_USE_COMP_ZBUF 0x20000000 223 #define R500FP_CONSTANT_TYPE (1 << 1) 224 #define R500FP_CONSTANT_CLAMP (1 << 2) 225 #define RADEON_POINTS 0x1 226 #define RADEON_LINES 0x2 227 #define RADEON_LINE_STRIP 0x3 228 #define RADEON_TRIANGLES 0x4 229 #define RADEON_TRIANGLE_FAN 0x5 230 #define RADEON_TRIANGLE_STRIP 0x6 231 #define RADEON_BUFFER_SIZE 65536 232 #define RADEON_INDEX_PRIM_OFFSET 20 233 #define RADEON_SCRATCH_REG_OFFSET 32 234 #define R600_SCRATCH_REG_OFFSET 256 235 #define RADEON_NR_SAREA_CLIPRECTS 12 236 #define RADEON_LOCAL_TEX_HEAP 0 237 #define RADEON_GART_TEX_HEAP 1 238 #define RADEON_NR_TEX_HEAPS 2 239 #define RADEON_NR_TEX_REGIONS 64 240 #define RADEON_LOG_TEX_GRANULARITY 16 241 #define RADEON_MAX_TEXTURE_LEVELS 12 242 #define RADEON_MAX_TEXTURE_UNITS 3 243 #define RADEON_MAX_SURFACES 8 244 #define RADEON_OFFSET_SHIFT 10 245 #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 246 #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 247 #endif 248 typedef struct { 249 unsigned int red; 250 unsigned int green; 251 unsigned int blue; 252 unsigned int alpha; 253 } radeon_color_regs_t; 254 typedef struct { 255 unsigned int pp_misc; 256 unsigned int pp_fog_color; 257 unsigned int re_solid_color; 258 unsigned int rb3d_blendcntl; 259 unsigned int rb3d_depthoffset; 260 unsigned int rb3d_depthpitch; 261 unsigned int rb3d_zstencilcntl; 262 unsigned int pp_cntl; 263 unsigned int rb3d_cntl; 264 unsigned int rb3d_coloroffset; 265 unsigned int re_width_height; 266 unsigned int rb3d_colorpitch; 267 unsigned int se_cntl; 268 unsigned int se_coord_fmt; 269 unsigned int re_line_pattern; 270 unsigned int re_line_state; 271 unsigned int se_line_width; 272 unsigned int pp_lum_matrix; 273 unsigned int pp_rot_matrix_0; 274 unsigned int pp_rot_matrix_1; 275 unsigned int rb3d_stencilrefmask; 276 unsigned int rb3d_ropcntl; 277 unsigned int rb3d_planemask; 278 unsigned int se_vport_xscale; 279 unsigned int se_vport_xoffset; 280 unsigned int se_vport_yscale; 281 unsigned int se_vport_yoffset; 282 unsigned int se_vport_zscale; 283 unsigned int se_vport_zoffset; 284 unsigned int se_cntl_status; 285 unsigned int re_top_left; 286 unsigned int re_misc; 287 } drm_radeon_context_regs_t; 288 typedef struct { 289 unsigned int se_zbias_factor; 290 unsigned int se_zbias_constant; 291 } drm_radeon_context2_regs_t; 292 typedef struct { 293 unsigned int pp_txfilter; 294 unsigned int pp_txformat; 295 unsigned int pp_txoffset; 296 unsigned int pp_txcblend; 297 unsigned int pp_txablend; 298 unsigned int pp_tfactor; 299 unsigned int pp_border_color; 300 } drm_radeon_texture_regs_t; 301 typedef struct { 302 unsigned int start; 303 unsigned int finish; 304 unsigned int prim : 8; 305 unsigned int stateidx : 8; 306 unsigned int numverts : 16; 307 unsigned int vc_format; 308 } drm_radeon_prim_t; 309 typedef struct { 310 drm_radeon_context_regs_t context; 311 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 312 drm_radeon_context2_regs_t context2; 313 unsigned int dirty; 314 } drm_radeon_state_t; 315 typedef struct { 316 drm_radeon_context_regs_t context_state; 317 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 318 unsigned int dirty; 319 unsigned int vertsize; 320 unsigned int vc_format; 321 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; 322 unsigned int nbox; 323 unsigned int last_frame; 324 unsigned int last_dispatch; 325 unsigned int last_clear; 326 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 1]; 327 unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 328 int ctx_owner; 329 int pfState; 330 int pfCurrentPage; 331 int crtc2_base; 332 int tiling_enabled; 333 } drm_radeon_sarea_t; 334 #define DRM_RADEON_CP_INIT 0x00 335 #define DRM_RADEON_CP_START 0x01 336 #define DRM_RADEON_CP_STOP 0x02 337 #define DRM_RADEON_CP_RESET 0x03 338 #define DRM_RADEON_CP_IDLE 0x04 339 #define DRM_RADEON_RESET 0x05 340 #define DRM_RADEON_FULLSCREEN 0x06 341 #define DRM_RADEON_SWAP 0x07 342 #define DRM_RADEON_CLEAR 0x08 343 #define DRM_RADEON_VERTEX 0x09 344 #define DRM_RADEON_INDICES 0x0A 345 #define DRM_RADEON_NOT_USED 346 #define DRM_RADEON_STIPPLE 0x0C 347 #define DRM_RADEON_INDIRECT 0x0D 348 #define DRM_RADEON_TEXTURE 0x0E 349 #define DRM_RADEON_VERTEX2 0x0F 350 #define DRM_RADEON_CMDBUF 0x10 351 #define DRM_RADEON_GETPARAM 0x11 352 #define DRM_RADEON_FLIP 0x12 353 #define DRM_RADEON_ALLOC 0x13 354 #define DRM_RADEON_FREE 0x14 355 #define DRM_RADEON_INIT_HEAP 0x15 356 #define DRM_RADEON_IRQ_EMIT 0x16 357 #define DRM_RADEON_IRQ_WAIT 0x17 358 #define DRM_RADEON_CP_RESUME 0x18 359 #define DRM_RADEON_SETPARAM 0x19 360 #define DRM_RADEON_SURF_ALLOC 0x1a 361 #define DRM_RADEON_SURF_FREE 0x1b 362 #define DRM_RADEON_GEM_INFO 0x1c 363 #define DRM_RADEON_GEM_CREATE 0x1d 364 #define DRM_RADEON_GEM_MMAP 0x1e 365 #define DRM_RADEON_GEM_PREAD 0x21 366 #define DRM_RADEON_GEM_PWRITE 0x22 367 #define DRM_RADEON_GEM_SET_DOMAIN 0x23 368 #define DRM_RADEON_GEM_WAIT_IDLE 0x24 369 #define DRM_RADEON_CS 0x26 370 #define DRM_RADEON_INFO 0x27 371 #define DRM_RADEON_GEM_SET_TILING 0x28 372 #define DRM_RADEON_GEM_GET_TILING 0x29 373 #define DRM_RADEON_GEM_BUSY 0x2a 374 #define DRM_RADEON_GEM_VA 0x2b 375 #define DRM_RADEON_GEM_OP 0x2c 376 #define DRM_RADEON_GEM_USERPTR 0x2d 377 #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 378 #define DRM_IOCTL_RADEON_CP_START DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_START) 379 #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 380 #define DRM_IOCTL_RADEON_CP_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 381 #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 382 #define DRM_IOCTL_RADEON_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_RESET) 383 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 384 #define DRM_IOCTL_RADEON_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_SWAP) 385 #define DRM_IOCTL_RADEON_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) 386 #define DRM_IOCTL_RADEON_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) 387 #define DRM_IOCTL_RADEON_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) 388 #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) 389 #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) 390 #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) 391 #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) 392 #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) 393 #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) 394 #define DRM_IOCTL_RADEON_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_FLIP) 395 #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) 396 #define DRM_IOCTL_RADEON_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 397 #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 398 #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 399 #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 400 #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 401 #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 402 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 403 #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) 404 #define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) 405 #define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) 406 #define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) 407 #define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) 408 #define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) 409 #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) 410 #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) 411 #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) 412 #define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) 413 #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) 414 #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) 415 #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) 416 #define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) 417 #define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op) 418 #define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr) 419 typedef struct drm_radeon_init { 420 enum { 421 RADEON_INIT_CP = 0x01, 422 RADEON_CLEANUP_CP = 0x02, 423 RADEON_INIT_R200_CP = 0x03, 424 RADEON_INIT_R300_CP = 0x04, 425 RADEON_INIT_R600_CP = 0x05 426 } func; 427 unsigned long sarea_priv_offset; 428 int is_pci; 429 int cp_mode; 430 int gart_size; 431 int ring_size; 432 int usec_timeout; 433 unsigned int fb_bpp; 434 unsigned int front_offset, front_pitch; 435 unsigned int back_offset, back_pitch; 436 unsigned int depth_bpp; 437 unsigned int depth_offset, depth_pitch; 438 unsigned long fb_offset; 439 unsigned long mmio_offset; 440 unsigned long ring_offset; 441 unsigned long ring_rptr_offset; 442 unsigned long buffers_offset; 443 unsigned long gart_textures_offset; 444 } drm_radeon_init_t; 445 typedef struct drm_radeon_cp_stop { 446 int flush; 447 int idle; 448 } drm_radeon_cp_stop_t; 449 typedef struct drm_radeon_fullscreen { 450 enum { 451 RADEON_INIT_FULLSCREEN = 0x01, 452 RADEON_CLEANUP_FULLSCREEN = 0x02 453 } func; 454 } drm_radeon_fullscreen_t; 455 #define CLEAR_X1 0 456 #define CLEAR_Y1 1 457 #define CLEAR_X2 2 458 #define CLEAR_Y2 3 459 #define CLEAR_DEPTH 4 460 typedef union drm_radeon_clear_rect { 461 float f[5]; 462 unsigned int ui[5]; 463 } drm_radeon_clear_rect_t; 464 typedef struct drm_radeon_clear { 465 unsigned int flags; 466 unsigned int clear_color; 467 unsigned int clear_depth; 468 unsigned int color_mask; 469 unsigned int depth_mask; 470 drm_radeon_clear_rect_t * depth_boxes; 471 } drm_radeon_clear_t; 472 typedef struct drm_radeon_vertex { 473 int prim; 474 int idx; 475 int count; 476 int discard; 477 } drm_radeon_vertex_t; 478 typedef struct drm_radeon_indices { 479 int prim; 480 int idx; 481 int start; 482 int end; 483 int discard; 484 } drm_radeon_indices_t; 485 typedef struct drm_radeon_vertex2 { 486 int idx; 487 int discard; 488 int nr_states; 489 drm_radeon_state_t * state; 490 int nr_prims; 491 drm_radeon_prim_t * prim; 492 } drm_radeon_vertex2_t; 493 typedef struct drm_radeon_cmd_buffer { 494 int bufsz; 495 char * buf; 496 int nbox; 497 struct drm_clip_rect * boxes; 498 } drm_radeon_cmd_buffer_t; 499 typedef struct drm_radeon_tex_image { 500 unsigned int x, y; 501 unsigned int width, height; 502 const void * data; 503 } drm_radeon_tex_image_t; 504 typedef struct drm_radeon_texture { 505 unsigned int offset; 506 int pitch; 507 int format; 508 int width; 509 int height; 510 drm_radeon_tex_image_t * image; 511 } drm_radeon_texture_t; 512 typedef struct drm_radeon_stipple { 513 unsigned int * mask; 514 } drm_radeon_stipple_t; 515 typedef struct drm_radeon_indirect { 516 int idx; 517 int start; 518 int end; 519 int discard; 520 } drm_radeon_indirect_t; 521 #define RADEON_CARD_PCI 0 522 #define RADEON_CARD_AGP 1 523 #define RADEON_CARD_PCIE 2 524 #define RADEON_PARAM_GART_BUFFER_OFFSET 1 525 #define RADEON_PARAM_LAST_FRAME 2 526 #define RADEON_PARAM_LAST_DISPATCH 3 527 #define RADEON_PARAM_LAST_CLEAR 4 528 #define RADEON_PARAM_IRQ_NR 5 529 #define RADEON_PARAM_GART_BASE 6 530 #define RADEON_PARAM_REGISTER_HANDLE 7 531 #define RADEON_PARAM_STATUS_HANDLE 8 532 #define RADEON_PARAM_SAREA_HANDLE 9 533 #define RADEON_PARAM_GART_TEX_HANDLE 10 534 #define RADEON_PARAM_SCRATCH_OFFSET 11 535 #define RADEON_PARAM_CARD_TYPE 12 536 #define RADEON_PARAM_VBLANK_CRTC 13 537 #define RADEON_PARAM_FB_LOCATION 14 538 #define RADEON_PARAM_NUM_GB_PIPES 15 539 #define RADEON_PARAM_DEVICE_ID 16 540 #define RADEON_PARAM_NUM_Z_PIPES 17 541 typedef struct drm_radeon_getparam { 542 int param; 543 void * value; 544 } drm_radeon_getparam_t; 545 #define RADEON_MEM_REGION_GART 1 546 #define RADEON_MEM_REGION_FB 2 547 typedef struct drm_radeon_mem_alloc { 548 int region; 549 int alignment; 550 int size; 551 int * region_offset; 552 } drm_radeon_mem_alloc_t; 553 typedef struct drm_radeon_mem_free { 554 int region; 555 int region_offset; 556 } drm_radeon_mem_free_t; 557 typedef struct drm_radeon_mem_init_heap { 558 int region; 559 int size; 560 int start; 561 } drm_radeon_mem_init_heap_t; 562 typedef struct drm_radeon_irq_emit { 563 int * irq_seq; 564 } drm_radeon_irq_emit_t; 565 typedef struct drm_radeon_irq_wait { 566 int irq_seq; 567 } drm_radeon_irq_wait_t; 568 typedef struct drm_radeon_setparam { 569 unsigned int param; 570 __s64 value; 571 } drm_radeon_setparam_t; 572 #define RADEON_SETPARAM_FB_LOCATION 1 573 #define RADEON_SETPARAM_SWITCH_TILING 2 574 #define RADEON_SETPARAM_PCIGART_LOCATION 3 575 #define RADEON_SETPARAM_NEW_MEMMAP 4 576 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 577 #define RADEON_SETPARAM_VBLANK_CRTC 6 578 typedef struct drm_radeon_surface_alloc { 579 unsigned int address; 580 unsigned int size; 581 unsigned int flags; 582 } drm_radeon_surface_alloc_t; 583 typedef struct drm_radeon_surface_free { 584 unsigned int address; 585 } drm_radeon_surface_free_t; 586 #define DRM_RADEON_VBLANK_CRTC1 1 587 #define DRM_RADEON_VBLANK_CRTC2 2 588 #define RADEON_GEM_DOMAIN_CPU 0x1 589 #define RADEON_GEM_DOMAIN_GTT 0x2 590 #define RADEON_GEM_DOMAIN_VRAM 0x4 591 struct drm_radeon_gem_info { 592 __u64 gart_size; 593 __u64 vram_size; 594 __u64 vram_visible; 595 }; 596 #define RADEON_GEM_NO_BACKING_STORE (1 << 0) 597 #define RADEON_GEM_GTT_UC (1 << 1) 598 #define RADEON_GEM_GTT_WC (1 << 2) 599 #define RADEON_GEM_CPU_ACCESS (1 << 3) 600 #define RADEON_GEM_NO_CPU_ACCESS (1 << 4) 601 struct drm_radeon_gem_create { 602 __u64 size; 603 __u64 alignment; 604 __u32 handle; 605 __u32 initial_domain; 606 __u32 flags; 607 }; 608 #define RADEON_GEM_USERPTR_READONLY (1 << 0) 609 #define RADEON_GEM_USERPTR_ANONONLY (1 << 1) 610 #define RADEON_GEM_USERPTR_VALIDATE (1 << 2) 611 #define RADEON_GEM_USERPTR_REGISTER (1 << 3) 612 struct drm_radeon_gem_userptr { 613 __u64 addr; 614 __u64 size; 615 __u32 flags; 616 __u32 handle; 617 }; 618 #define RADEON_TILING_MACRO 0x1 619 #define RADEON_TILING_MICRO 0x2 620 #define RADEON_TILING_SWAP_16BIT 0x4 621 #define RADEON_TILING_SWAP_32BIT 0x8 622 #define RADEON_TILING_SURFACE 0x10 623 #define RADEON_TILING_MICRO_SQUARE 0x20 624 #define RADEON_TILING_EG_BANKW_SHIFT 8 625 #define RADEON_TILING_EG_BANKW_MASK 0xf 626 #define RADEON_TILING_EG_BANKH_SHIFT 12 627 #define RADEON_TILING_EG_BANKH_MASK 0xf 628 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 629 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf 630 #define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 631 #define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf 632 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 633 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf 634 struct drm_radeon_gem_set_tiling { 635 __u32 handle; 636 __u32 tiling_flags; 637 __u32 pitch; 638 }; 639 struct drm_radeon_gem_get_tiling { 640 __u32 handle; 641 __u32 tiling_flags; 642 __u32 pitch; 643 }; 644 struct drm_radeon_gem_mmap { 645 __u32 handle; 646 __u32 pad; 647 __u64 offset; 648 __u64 size; 649 __u64 addr_ptr; 650 }; 651 struct drm_radeon_gem_set_domain { 652 __u32 handle; 653 __u32 read_domains; 654 __u32 write_domain; 655 }; 656 struct drm_radeon_gem_wait_idle { 657 __u32 handle; 658 __u32 pad; 659 }; 660 struct drm_radeon_gem_busy { 661 __u32 handle; 662 __u32 domain; 663 }; 664 struct drm_radeon_gem_pread { 665 __u32 handle; 666 __u32 pad; 667 __u64 offset; 668 __u64 size; 669 __u64 data_ptr; 670 }; 671 struct drm_radeon_gem_pwrite { 672 __u32 handle; 673 __u32 pad; 674 __u64 offset; 675 __u64 size; 676 __u64 data_ptr; 677 }; 678 struct drm_radeon_gem_op { 679 __u32 handle; 680 __u32 op; 681 __u64 value; 682 }; 683 #define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0 684 #define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1 685 #define RADEON_VA_MAP 1 686 #define RADEON_VA_UNMAP 2 687 #define RADEON_VA_RESULT_OK 0 688 #define RADEON_VA_RESULT_ERROR 1 689 #define RADEON_VA_RESULT_VA_EXIST 2 690 #define RADEON_VM_PAGE_VALID (1 << 0) 691 #define RADEON_VM_PAGE_READABLE (1 << 1) 692 #define RADEON_VM_PAGE_WRITEABLE (1 << 2) 693 #define RADEON_VM_PAGE_SYSTEM (1 << 3) 694 #define RADEON_VM_PAGE_SNOOPED (1 << 4) 695 struct drm_radeon_gem_va { 696 __u32 handle; 697 __u32 operation; 698 __u32 vm_id; 699 __u32 flags; 700 __u64 offset; 701 }; 702 #define RADEON_CHUNK_ID_RELOCS 0x01 703 #define RADEON_CHUNK_ID_IB 0x02 704 #define RADEON_CHUNK_ID_FLAGS 0x03 705 #define RADEON_CHUNK_ID_CONST_IB 0x04 706 #define RADEON_CS_KEEP_TILING_FLAGS 0x01 707 #define RADEON_CS_USE_VM 0x02 708 #define RADEON_CS_END_OF_FRAME 0x04 709 #define RADEON_CS_RING_GFX 0 710 #define RADEON_CS_RING_COMPUTE 1 711 #define RADEON_CS_RING_DMA 2 712 #define RADEON_CS_RING_UVD 3 713 #define RADEON_CS_RING_VCE 4 714 struct drm_radeon_cs_chunk { 715 __u32 chunk_id; 716 __u32 length_dw; 717 __u64 chunk_data; 718 }; 719 #define RADEON_RELOC_PRIO_MASK (0xf << 0) 720 struct drm_radeon_cs_reloc { 721 __u32 handle; 722 __u32 read_domains; 723 __u32 write_domain; 724 __u32 flags; 725 }; 726 struct drm_radeon_cs { 727 __u32 num_chunks; 728 __u32 cs_id; 729 __u64 chunks; 730 __u64 gart_limit; 731 __u64 vram_limit; 732 }; 733 #define RADEON_INFO_DEVICE_ID 0x00 734 #define RADEON_INFO_NUM_GB_PIPES 0x01 735 #define RADEON_INFO_NUM_Z_PIPES 0x02 736 #define RADEON_INFO_ACCEL_WORKING 0x03 737 #define RADEON_INFO_CRTC_FROM_ID 0x04 738 #define RADEON_INFO_ACCEL_WORKING2 0x05 739 #define RADEON_INFO_TILING_CONFIG 0x06 740 #define RADEON_INFO_WANT_HYPERZ 0x07 741 #define RADEON_INFO_WANT_CMASK 0x08 742 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 743 #define RADEON_INFO_NUM_BACKENDS 0x0a 744 #define RADEON_INFO_NUM_TILE_PIPES 0x0b 745 #define RADEON_INFO_FUSION_GART_WORKING 0x0c 746 #define RADEON_INFO_BACKEND_MAP 0x0d 747 #define RADEON_INFO_VA_START 0x0e 748 #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f 749 #define RADEON_INFO_MAX_PIPES 0x10 750 #define RADEON_INFO_TIMESTAMP 0x11 751 #define RADEON_INFO_MAX_SE 0x12 752 #define RADEON_INFO_MAX_SH_PER_SE 0x13 753 #define RADEON_INFO_FASTFB_WORKING 0x14 754 #define RADEON_INFO_RING_WORKING 0x15 755 #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 756 #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 757 #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 758 #define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19 759 #define RADEON_INFO_MAX_SCLK 0x1a 760 #define RADEON_INFO_VCE_FW_VERSION 0x1b 761 #define RADEON_INFO_VCE_FB_VERSION 0x1c 762 #define RADEON_INFO_NUM_BYTES_MOVED 0x1d 763 #define RADEON_INFO_VRAM_USAGE 0x1e 764 #define RADEON_INFO_GTT_USAGE 0x1f 765 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20 766 #define RADEON_INFO_CURRENT_GPU_TEMP 0x21 767 #define RADEON_INFO_CURRENT_GPU_SCLK 0x22 768 #define RADEON_INFO_CURRENT_GPU_MCLK 0x23 769 #define RADEON_INFO_READ_REG 0x24 770 #define RADEON_INFO_VA_UNMAP_WORKING 0x25 771 #define RADEON_INFO_GPU_RESET_COUNTER 0x26 772 struct drm_radeon_info { 773 __u32 request; 774 __u32 pad; 775 __u64 value; 776 }; 777 #define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8 778 #define SI_TILE_MODE_COLOR_1D 13 779 #define SI_TILE_MODE_COLOR_1D_SCANOUT 9 780 #define SI_TILE_MODE_COLOR_2D_8BPP 14 781 #define SI_TILE_MODE_COLOR_2D_16BPP 15 782 #define SI_TILE_MODE_COLOR_2D_32BPP 16 783 #define SI_TILE_MODE_COLOR_2D_64BPP 17 784 #define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11 785 #define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12 786 #define SI_TILE_MODE_DEPTH_STENCIL_1D 4 787 #define SI_TILE_MODE_DEPTH_STENCIL_2D 0 788 #define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3 789 #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 790 #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 791 #define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 792 #ifdef __cplusplus 793 } 794 #endif 795 #endif 796