1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __VMWGFX_DRM_H__ 8 #define __VMWGFX_DRM_H__ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #define DRM_VMW_MAX_SURFACE_FACES 6 14 #define DRM_VMW_MAX_MIP_LEVELS 24 15 #define DRM_VMW_GET_PARAM 0 16 #define DRM_VMW_ALLOC_DMABUF 1 17 #define DRM_VMW_ALLOC_BO 1 18 #define DRM_VMW_UNREF_DMABUF 2 19 #define DRM_VMW_HANDLE_CLOSE 2 20 #define DRM_VMW_CURSOR_BYPASS 3 21 #define DRM_VMW_CONTROL_STREAM 4 22 #define DRM_VMW_CLAIM_STREAM 5 23 #define DRM_VMW_UNREF_STREAM 6 24 #define DRM_VMW_CREATE_CONTEXT 7 25 #define DRM_VMW_UNREF_CONTEXT 8 26 #define DRM_VMW_CREATE_SURFACE 9 27 #define DRM_VMW_UNREF_SURFACE 10 28 #define DRM_VMW_REF_SURFACE 11 29 #define DRM_VMW_EXECBUF 12 30 #define DRM_VMW_GET_3D_CAP 13 31 #define DRM_VMW_FENCE_WAIT 14 32 #define DRM_VMW_FENCE_SIGNALED 15 33 #define DRM_VMW_FENCE_UNREF 16 34 #define DRM_VMW_FENCE_EVENT 17 35 #define DRM_VMW_PRESENT 18 36 #define DRM_VMW_PRESENT_READBACK 19 37 #define DRM_VMW_UPDATE_LAYOUT 20 38 #define DRM_VMW_CREATE_SHADER 21 39 #define DRM_VMW_UNREF_SHADER 22 40 #define DRM_VMW_GB_SURFACE_CREATE 23 41 #define DRM_VMW_GB_SURFACE_REF 24 42 #define DRM_VMW_SYNCCPU 25 43 #define DRM_VMW_CREATE_EXTENDED_CONTEXT 26 44 #define DRM_VMW_GB_SURFACE_CREATE_EXT 27 45 #define DRM_VMW_GB_SURFACE_REF_EXT 28 46 #define DRM_VMW_MSG 29 47 #define DRM_VMW_MKSSTAT_RESET 30 48 #define DRM_VMW_MKSSTAT_ADD 31 49 #define DRM_VMW_MKSSTAT_REMOVE 32 50 #define DRM_VMW_PARAM_NUM_STREAMS 0 51 #define DRM_VMW_PARAM_NUM_FREE_STREAMS 1 52 #define DRM_VMW_PARAM_3D 2 53 #define DRM_VMW_PARAM_HW_CAPS 3 54 #define DRM_VMW_PARAM_FIFO_CAPS 4 55 #define DRM_VMW_PARAM_MAX_FB_SIZE 5 56 #define DRM_VMW_PARAM_FIFO_HW_VERSION 6 57 #define DRM_VMW_PARAM_MAX_SURF_MEMORY 7 58 #define DRM_VMW_PARAM_3D_CAPS_SIZE 8 59 #define DRM_VMW_PARAM_MAX_MOB_MEMORY 9 60 #define DRM_VMW_PARAM_MAX_MOB_SIZE 10 61 #define DRM_VMW_PARAM_SCREEN_TARGET 11 62 #define DRM_VMW_PARAM_DX 12 63 #define DRM_VMW_PARAM_HW_CAPS2 13 64 #define DRM_VMW_PARAM_SM4_1 14 65 #define DRM_VMW_PARAM_SM5 15 66 #define DRM_VMW_PARAM_GL43 16 67 #define DRM_VMW_PARAM_DEVICE_ID 17 68 enum drm_vmw_handle_type { 69 DRM_VMW_HANDLE_LEGACY = 0, 70 DRM_VMW_HANDLE_PRIME = 1 71 }; 72 struct drm_vmw_getparam_arg { 73 __u64 value; 74 __u32 param; 75 __u32 pad64; 76 }; 77 struct drm_vmw_context_arg { 78 __s32 cid; 79 __u32 pad64; 80 }; 81 struct drm_vmw_surface_create_req { 82 __u32 flags; 83 __u32 format; 84 __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES]; 85 __u64 size_addr; 86 __s32 shareable; 87 __s32 scanout; 88 }; 89 struct drm_vmw_surface_arg { 90 __s32 sid; 91 enum drm_vmw_handle_type handle_type; 92 }; 93 struct drm_vmw_size { 94 __u32 width; 95 __u32 height; 96 __u32 depth; 97 __u32 pad64; 98 }; 99 union drm_vmw_surface_create_arg { 100 struct drm_vmw_surface_arg rep; 101 struct drm_vmw_surface_create_req req; 102 }; 103 union drm_vmw_surface_reference_arg { 104 struct drm_vmw_surface_create_req rep; 105 struct drm_vmw_surface_arg req; 106 }; 107 #define DRM_VMW_EXECBUF_VERSION 2 108 #define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0) 109 #define DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1) 110 struct drm_vmw_execbuf_arg { 111 __u64 commands; 112 __u32 command_size; 113 __u32 throttle_us; 114 __u64 fence_rep; 115 __u32 version; 116 __u32 flags; 117 __u32 context_handle; 118 __s32 imported_fence_fd; 119 }; 120 struct drm_vmw_fence_rep { 121 __u32 handle; 122 __u32 mask; 123 __u32 seqno; 124 __u32 passed_seqno; 125 __s32 fd; 126 __s32 error; 127 }; 128 struct drm_vmw_alloc_bo_req { 129 __u32 size; 130 __u32 pad64; 131 }; 132 #define drm_vmw_alloc_dmabuf_req drm_vmw_alloc_bo_req 133 struct drm_vmw_bo_rep { 134 __u64 map_handle; 135 __u32 handle; 136 __u32 cur_gmr_id; 137 __u32 cur_gmr_offset; 138 __u32 pad64; 139 }; 140 #define drm_vmw_dmabuf_rep drm_vmw_bo_rep 141 union drm_vmw_alloc_bo_arg { 142 struct drm_vmw_alloc_bo_req req; 143 struct drm_vmw_bo_rep rep; 144 }; 145 #define drm_vmw_alloc_dmabuf_arg drm_vmw_alloc_bo_arg 146 struct drm_vmw_rect { 147 __s32 x; 148 __s32 y; 149 __u32 w; 150 __u32 h; 151 }; 152 struct drm_vmw_control_stream_arg { 153 __u32 stream_id; 154 __u32 enabled; 155 __u32 flags; 156 __u32 color_key; 157 __u32 handle; 158 __u32 offset; 159 __s32 format; 160 __u32 size; 161 __u32 width; 162 __u32 height; 163 __u32 pitch[3]; 164 __u32 pad64; 165 struct drm_vmw_rect src; 166 struct drm_vmw_rect dst; 167 }; 168 #define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0) 169 #define DRM_VMW_CURSOR_BYPASS_FLAGS (1) 170 struct drm_vmw_cursor_bypass_arg { 171 __u32 flags; 172 __u32 crtc_id; 173 __s32 xpos; 174 __s32 ypos; 175 __s32 xhot; 176 __s32 yhot; 177 }; 178 struct drm_vmw_stream_arg { 179 __u32 stream_id; 180 __u32 pad64; 181 }; 182 struct drm_vmw_get_3d_cap_arg { 183 __u64 buffer; 184 __u32 max_size; 185 __u32 pad64; 186 }; 187 #define DRM_VMW_FENCE_FLAG_EXEC (1 << 0) 188 #define DRM_VMW_FENCE_FLAG_QUERY (1 << 1) 189 #define DRM_VMW_WAIT_OPTION_UNREF (1 << 0) 190 struct drm_vmw_fence_wait_arg { 191 __u32 handle; 192 __s32 cookie_valid; 193 __u64 kernel_cookie; 194 __u64 timeout_us; 195 __s32 lazy; 196 __s32 flags; 197 __s32 wait_options; 198 __s32 pad64; 199 }; 200 struct drm_vmw_fence_signaled_arg { 201 __u32 handle; 202 __u32 flags; 203 __s32 signaled; 204 __u32 passed_seqno; 205 __u32 signaled_flags; 206 __u32 pad64; 207 }; 208 struct drm_vmw_fence_arg { 209 __u32 handle; 210 __u32 pad64; 211 }; 212 #define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000 213 struct drm_vmw_event_fence { 214 struct drm_event base; 215 __u64 user_data; 216 __u32 tv_sec; 217 __u32 tv_usec; 218 }; 219 #define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0) 220 struct drm_vmw_fence_event_arg { 221 __u64 fence_rep; 222 __u64 user_data; 223 __u32 handle; 224 __u32 flags; 225 }; 226 struct drm_vmw_present_arg { 227 __u32 fb_id; 228 __u32 sid; 229 __s32 dest_x; 230 __s32 dest_y; 231 __u64 clips_ptr; 232 __u32 num_clips; 233 __u32 pad64; 234 }; 235 struct drm_vmw_present_readback_arg { 236 __u32 fb_id; 237 __u32 num_clips; 238 __u64 clips_ptr; 239 __u64 fence_rep; 240 }; 241 struct drm_vmw_update_layout_arg { 242 __u32 num_outputs; 243 __u32 pad64; 244 __u64 rects; 245 }; 246 enum drm_vmw_shader_type { 247 drm_vmw_shader_type_vs = 0, 248 drm_vmw_shader_type_ps, 249 }; 250 struct drm_vmw_shader_create_arg { 251 enum drm_vmw_shader_type shader_type; 252 __u32 size; 253 __u32 buffer_handle; 254 __u32 shader_handle; 255 __u64 offset; 256 }; 257 struct drm_vmw_shader_arg { 258 __u32 handle; 259 __u32 pad64; 260 }; 261 enum drm_vmw_surface_flags { 262 drm_vmw_surface_flag_shareable = (1 << 0), 263 drm_vmw_surface_flag_scanout = (1 << 1), 264 drm_vmw_surface_flag_create_buffer = (1 << 2), 265 drm_vmw_surface_flag_coherent = (1 << 3), 266 }; 267 struct drm_vmw_gb_surface_create_req { 268 __u32 svga3d_flags; 269 __u32 format; 270 __u32 mip_levels; 271 enum drm_vmw_surface_flags drm_surface_flags; 272 __u32 multisample_count; 273 __u32 autogen_filter; 274 __u32 buffer_handle; 275 __u32 array_size; 276 struct drm_vmw_size base_size; 277 }; 278 struct drm_vmw_gb_surface_create_rep { 279 __u32 handle; 280 __u32 backup_size; 281 __u32 buffer_handle; 282 __u32 buffer_size; 283 __u64 buffer_map_handle; 284 }; 285 union drm_vmw_gb_surface_create_arg { 286 struct drm_vmw_gb_surface_create_rep rep; 287 struct drm_vmw_gb_surface_create_req req; 288 }; 289 struct drm_vmw_gb_surface_ref_rep { 290 struct drm_vmw_gb_surface_create_req creq; 291 struct drm_vmw_gb_surface_create_rep crep; 292 }; 293 union drm_vmw_gb_surface_reference_arg { 294 struct drm_vmw_gb_surface_ref_rep rep; 295 struct drm_vmw_surface_arg req; 296 }; 297 enum drm_vmw_synccpu_flags { 298 drm_vmw_synccpu_read = (1 << 0), 299 drm_vmw_synccpu_write = (1 << 1), 300 drm_vmw_synccpu_dontblock = (1 << 2), 301 drm_vmw_synccpu_allow_cs = (1 << 3) 302 }; 303 enum drm_vmw_synccpu_op { 304 drm_vmw_synccpu_grab, 305 drm_vmw_synccpu_release 306 }; 307 struct drm_vmw_synccpu_arg { 308 enum drm_vmw_synccpu_op op; 309 enum drm_vmw_synccpu_flags flags; 310 __u32 handle; 311 __u32 pad64; 312 }; 313 enum drm_vmw_extended_context { 314 drm_vmw_context_legacy, 315 drm_vmw_context_dx 316 }; 317 union drm_vmw_extended_context_arg { 318 enum drm_vmw_extended_context req; 319 struct drm_vmw_context_arg rep; 320 }; 321 struct drm_vmw_handle_close_arg { 322 __u32 handle; 323 __u32 pad64; 324 }; 325 #define drm_vmw_unref_dmabuf_arg drm_vmw_handle_close_arg 326 enum drm_vmw_surface_version { 327 drm_vmw_gb_surface_v1, 328 }; 329 struct drm_vmw_gb_surface_create_ext_req { 330 struct drm_vmw_gb_surface_create_req base; 331 enum drm_vmw_surface_version version; 332 __u32 svga3d_flags_upper_32_bits; 333 __u32 multisample_pattern; 334 __u32 quality_level; 335 __u32 buffer_byte_stride; 336 __u32 must_be_zero; 337 }; 338 union drm_vmw_gb_surface_create_ext_arg { 339 struct drm_vmw_gb_surface_create_rep rep; 340 struct drm_vmw_gb_surface_create_ext_req req; 341 }; 342 struct drm_vmw_gb_surface_ref_ext_rep { 343 struct drm_vmw_gb_surface_create_ext_req creq; 344 struct drm_vmw_gb_surface_create_rep crep; 345 }; 346 union drm_vmw_gb_surface_reference_ext_arg { 347 struct drm_vmw_gb_surface_ref_ext_rep rep; 348 struct drm_vmw_surface_arg req; 349 }; 350 struct drm_vmw_msg_arg { 351 __u64 send; 352 __u64 receive; 353 __s32 send_only; 354 __u32 receive_len; 355 }; 356 struct drm_vmw_mksstat_add_arg { 357 __u64 stat; 358 __u64 info; 359 __u64 strs; 360 __u64 stat_len; 361 __u64 info_len; 362 __u64 strs_len; 363 __u64 description; 364 __u64 id; 365 }; 366 struct drm_vmw_mksstat_remove_arg { 367 __u64 id; 368 }; 369 #ifdef __cplusplus 370 } 371 #endif 372 #endif 373