1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _UAPI_XE_DRM_H_ 8 #define _UAPI_XE_DRM_H_ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #define DRM_XE_DEVICE_QUERY 0x00 14 #define DRM_XE_GEM_CREATE 0x01 15 #define DRM_XE_GEM_MMAP_OFFSET 0x02 16 #define DRM_XE_VM_CREATE 0x03 17 #define DRM_XE_VM_DESTROY 0x04 18 #define DRM_XE_VM_BIND 0x05 19 #define DRM_XE_EXEC_QUEUE_CREATE 0x06 20 #define DRM_XE_EXEC_QUEUE_DESTROY 0x07 21 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x08 22 #define DRM_XE_EXEC 0x09 23 #define DRM_XE_WAIT_USER_FENCE 0x0a 24 #define DRM_XE_OBSERVATION 0x0b 25 #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) 26 #define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create) 27 #define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset) 28 #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) 29 #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) 30 #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) 31 #define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) 32 #define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) 33 #define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) 34 #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) 35 #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) 36 #define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param) 37 struct drm_xe_user_extension { 38 __u64 next_extension; 39 __u32 name; 40 __u32 pad; 41 }; 42 struct drm_xe_ext_set_property { 43 struct drm_xe_user_extension base; 44 __u32 property; 45 __u32 pad; 46 __u64 value; 47 __u64 reserved[2]; 48 }; 49 struct drm_xe_engine_class_instance { 50 #define DRM_XE_ENGINE_CLASS_RENDER 0 51 #define DRM_XE_ENGINE_CLASS_COPY 1 52 #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2 53 #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3 54 #define DRM_XE_ENGINE_CLASS_COMPUTE 4 55 #define DRM_XE_ENGINE_CLASS_VM_BIND 5 56 __u16 engine_class; 57 __u16 engine_instance; 58 __u16 gt_id; 59 __u16 pad; 60 }; 61 struct drm_xe_engine { 62 struct drm_xe_engine_class_instance instance; 63 __u64 reserved[3]; 64 }; 65 struct drm_xe_query_engines { 66 __u32 num_engines; 67 __u32 pad; 68 struct drm_xe_engine engines[]; 69 }; 70 enum drm_xe_memory_class { 71 DRM_XE_MEM_REGION_CLASS_SYSMEM = 0, 72 DRM_XE_MEM_REGION_CLASS_VRAM 73 }; 74 struct drm_xe_mem_region { 75 __u16 mem_class; 76 __u16 instance; 77 __u32 min_page_size; 78 __u64 total_size; 79 __u64 used; 80 __u64 cpu_visible_size; 81 __u64 cpu_visible_used; 82 __u64 reserved[6]; 83 }; 84 struct drm_xe_query_mem_regions { 85 __u32 num_mem_regions; 86 __u32 pad; 87 struct drm_xe_mem_region mem_regions[]; 88 }; 89 struct drm_xe_query_config { 90 __u32 num_params; 91 __u32 pad; 92 #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0 93 #define DRM_XE_QUERY_CONFIG_FLAGS 1 94 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0) 95 #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2 96 #define DRM_XE_QUERY_CONFIG_VA_BITS 3 97 #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4 98 __u64 info[]; 99 }; 100 struct drm_xe_gt { 101 #define DRM_XE_QUERY_GT_TYPE_MAIN 0 102 #define DRM_XE_QUERY_GT_TYPE_MEDIA 1 103 __u16 type; 104 __u16 tile_id; 105 __u16 gt_id; 106 __u16 pad[3]; 107 __u32 reference_clock; 108 __u64 near_mem_regions; 109 __u64 far_mem_regions; 110 __u16 ip_ver_major; 111 __u16 ip_ver_minor; 112 __u16 ip_ver_rev; 113 __u16 pad2; 114 __u64 reserved[7]; 115 }; 116 struct drm_xe_query_gt_list { 117 __u32 num_gt; 118 __u32 pad; 119 struct drm_xe_gt gt_list[]; 120 }; 121 struct drm_xe_query_topology_mask { 122 __u16 gt_id; 123 #define DRM_XE_TOPO_DSS_GEOMETRY 1 124 #define DRM_XE_TOPO_DSS_COMPUTE 2 125 #define DRM_XE_TOPO_L3_BANK 3 126 #define DRM_XE_TOPO_EU_PER_DSS 4 127 __u16 type; 128 __u32 num_bytes; 129 __u8 mask[]; 130 }; 131 struct drm_xe_query_engine_cycles { 132 struct drm_xe_engine_class_instance eci; 133 __s32 clockid; 134 __u32 width; 135 __u64 engine_cycles; 136 __u64 cpu_timestamp; 137 __u64 cpu_delta; 138 }; 139 struct drm_xe_query_uc_fw_version { 140 #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0 141 #define XE_QUERY_UC_TYPE_HUC 1 142 __u16 uc_type; 143 __u16 pad; 144 __u32 branch_ver; 145 __u32 major_ver; 146 __u32 minor_ver; 147 __u32 patch_ver; 148 __u32 pad2; 149 __u64 reserved; 150 }; 151 struct drm_xe_device_query { 152 __u64 extensions; 153 #define DRM_XE_DEVICE_QUERY_ENGINES 0 154 #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1 155 #define DRM_XE_DEVICE_QUERY_CONFIG 2 156 #define DRM_XE_DEVICE_QUERY_GT_LIST 3 157 #define DRM_XE_DEVICE_QUERY_HWCONFIG 4 158 #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5 159 #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6 160 #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7 161 #define DRM_XE_DEVICE_QUERY_OA_UNITS 8 162 __u32 query; 163 __u32 size; 164 __u64 data; 165 __u64 reserved[2]; 166 }; 167 struct drm_xe_gem_create { 168 __u64 extensions; 169 __u64 size; 170 __u32 placement; 171 #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0) 172 #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1) 173 #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2) 174 __u32 flags; 175 __u32 vm_id; 176 __u32 handle; 177 #define DRM_XE_GEM_CPU_CACHING_WB 1 178 #define DRM_XE_GEM_CPU_CACHING_WC 2 179 __u16 cpu_caching; 180 __u16 pad[3]; 181 __u64 reserved[2]; 182 }; 183 struct drm_xe_gem_mmap_offset { 184 __u64 extensions; 185 __u32 handle; 186 __u32 flags; 187 __u64 offset; 188 __u64 reserved[2]; 189 }; 190 struct drm_xe_vm_create { 191 __u64 extensions; 192 #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0) 193 #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1) 194 #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2) 195 __u32 flags; 196 __u32 vm_id; 197 __u64 reserved[2]; 198 }; 199 struct drm_xe_vm_destroy { 200 __u32 vm_id; 201 __u32 pad; 202 __u64 reserved[2]; 203 }; 204 struct drm_xe_vm_bind_op { 205 __u64 extensions; 206 __u32 obj; 207 __u16 pat_index; 208 __u16 pad; 209 union { 210 __u64 obj_offset; 211 __u64 userptr; 212 }; 213 __u64 range; 214 __u64 addr; 215 #define DRM_XE_VM_BIND_OP_MAP 0x0 216 #define DRM_XE_VM_BIND_OP_UNMAP 0x1 217 #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2 218 #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3 219 #define DRM_XE_VM_BIND_OP_PREFETCH 0x4 220 __u32 op; 221 #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0) 222 #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1) 223 #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2) 224 #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3) 225 __u32 flags; 226 __u32 prefetch_mem_region_instance; 227 __u32 pad2; 228 __u64 reserved[3]; 229 }; 230 struct drm_xe_vm_bind { 231 __u64 extensions; 232 __u32 vm_id; 233 __u32 exec_queue_id; 234 __u32 pad; 235 __u32 num_binds; 236 union { 237 struct drm_xe_vm_bind_op bind; 238 __u64 vector_of_binds; 239 }; 240 __u32 pad2; 241 __u32 num_syncs; 242 __u64 syncs; 243 __u64 reserved[2]; 244 }; 245 struct drm_xe_exec_queue_create { 246 #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 247 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0 248 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1 249 __u64 extensions; 250 __u16 width; 251 __u16 num_placements; 252 __u32 vm_id; 253 __u32 flags; 254 __u32 exec_queue_id; 255 __u64 instances; 256 __u64 reserved[2]; 257 }; 258 struct drm_xe_exec_queue_destroy { 259 __u32 exec_queue_id; 260 __u32 pad; 261 __u64 reserved[2]; 262 }; 263 struct drm_xe_exec_queue_get_property { 264 __u64 extensions; 265 __u32 exec_queue_id; 266 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0 267 __u32 property; 268 __u64 value; 269 __u64 reserved[2]; 270 }; 271 struct drm_xe_sync { 272 __u64 extensions; 273 #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0 274 #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1 275 #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2 276 __u32 type; 277 #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0) 278 __u32 flags; 279 union { 280 __u32 handle; 281 __u64 addr; 282 }; 283 __u64 timeline_value; 284 __u64 reserved[2]; 285 }; 286 struct drm_xe_exec { 287 __u64 extensions; 288 __u32 exec_queue_id; 289 __u32 num_syncs; 290 __u64 syncs; 291 __u64 address; 292 __u16 num_batch_buffer; 293 __u16 pad[3]; 294 __u64 reserved[2]; 295 }; 296 struct drm_xe_wait_user_fence { 297 __u64 extensions; 298 __u64 addr; 299 #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0 300 #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1 301 #define DRM_XE_UFENCE_WAIT_OP_GT 0x2 302 #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3 303 #define DRM_XE_UFENCE_WAIT_OP_LT 0x4 304 #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5 305 __u16 op; 306 #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0) 307 __u16 flags; 308 __u32 pad; 309 __u64 value; 310 __u64 mask; 311 __s64 timeout; 312 __u32 exec_queue_id; 313 __u32 pad2; 314 __u64 reserved[2]; 315 }; 316 enum drm_xe_observation_type { 317 DRM_XE_OBSERVATION_TYPE_OA, 318 }; 319 enum drm_xe_observation_op { 320 DRM_XE_OBSERVATION_OP_STREAM_OPEN, 321 DRM_XE_OBSERVATION_OP_ADD_CONFIG, 322 DRM_XE_OBSERVATION_OP_REMOVE_CONFIG, 323 }; 324 struct drm_xe_observation_param { 325 __u64 extensions; 326 __u64 observation_type; 327 __u64 observation_op; 328 __u64 param; 329 }; 330 enum drm_xe_observation_ioctls { 331 DRM_XE_OBSERVATION_IOCTL_ENABLE = _IO('i', 0x0), 332 DRM_XE_OBSERVATION_IOCTL_DISABLE = _IO('i', 0x1), 333 DRM_XE_OBSERVATION_IOCTL_CONFIG = _IO('i', 0x2), 334 DRM_XE_OBSERVATION_IOCTL_STATUS = _IO('i', 0x3), 335 DRM_XE_OBSERVATION_IOCTL_INFO = _IO('i', 0x4), 336 }; 337 enum drm_xe_oa_unit_type { 338 DRM_XE_OA_UNIT_TYPE_OAG, 339 DRM_XE_OA_UNIT_TYPE_OAM, 340 }; 341 struct drm_xe_oa_unit { 342 __u64 extensions; 343 __u32 oa_unit_id; 344 __u32 oa_unit_type; 345 __u64 capabilities; 346 #define DRM_XE_OA_CAPS_BASE (1 << 0) 347 __u64 oa_timestamp_freq; 348 __u64 reserved[4]; 349 __u64 num_engines; 350 struct drm_xe_engine_class_instance eci[]; 351 }; 352 struct drm_xe_query_oa_units { 353 __u64 extensions; 354 __u32 num_oa_units; 355 __u32 pad; 356 __u64 oa_units[]; 357 }; 358 enum drm_xe_oa_format_type { 359 DRM_XE_OA_FMT_TYPE_OAG, 360 DRM_XE_OA_FMT_TYPE_OAR, 361 DRM_XE_OA_FMT_TYPE_OAM, 362 DRM_XE_OA_FMT_TYPE_OAC, 363 DRM_XE_OA_FMT_TYPE_OAM_MPEC, 364 DRM_XE_OA_FMT_TYPE_PEC, 365 }; 366 enum drm_xe_oa_property_id { 367 #define DRM_XE_OA_EXTENSION_SET_PROPERTY 0 368 DRM_XE_OA_PROPERTY_OA_UNIT_ID = 1, 369 DRM_XE_OA_PROPERTY_SAMPLE_OA, 370 DRM_XE_OA_PROPERTY_OA_METRIC_SET, 371 DRM_XE_OA_PROPERTY_OA_FORMAT, 372 #define DRM_XE_OA_FORMAT_MASK_FMT_TYPE (0xffu << 0) 373 #define DRM_XE_OA_FORMAT_MASK_COUNTER_SEL (0xffu << 8) 374 #define DRM_XE_OA_FORMAT_MASK_COUNTER_SIZE (0xffu << 16) 375 #define DRM_XE_OA_FORMAT_MASK_BC_REPORT (0xffu << 24) 376 DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, 377 DRM_XE_OA_PROPERTY_OA_DISABLED, 378 DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID, 379 DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, 380 DRM_XE_OA_PROPERTY_NO_PREEMPT, 381 }; 382 struct drm_xe_oa_config { 383 __u64 extensions; 384 char uuid[36]; 385 __u32 n_regs; 386 __u64 regs_ptr; 387 }; 388 struct drm_xe_oa_stream_status { 389 __u64 extensions; 390 __u64 oa_status; 391 #define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL (1 << 3) 392 #define DRM_XE_OASTATUS_COUNTER_OVERFLOW (1 << 2) 393 #define DRM_XE_OASTATUS_BUFFER_OVERFLOW (1 << 1) 394 #define DRM_XE_OASTATUS_REPORT_LOST (1 << 0) 395 __u64 reserved[3]; 396 }; 397 struct drm_xe_oa_stream_info { 398 __u64 extensions; 399 __u64 oa_buf_size; 400 __u64 reserved[3]; 401 }; 402 #ifdef __cplusplus 403 } 404 #endif 405 #endif 406