1 //===-- ArchSpec.h ----------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_UTILITY_ARCHSPEC_H 10 #define LLDB_UTILITY_ARCHSPEC_H 11 12 #include "lldb/Utility/CompletionRequest.h" 13 #include "lldb/lldb-enumerations.h" 14 #include "lldb/lldb-forward.h" 15 #include "lldb/lldb-private-enumerations.h" 16 #include "llvm/ADT/StringRef.h" 17 #include "llvm/TargetParser/Triple.h" 18 #include <cstddef> 19 #include <cstdint> 20 #include <string> 21 22 namespace lldb_private { 23 24 /// \class ArchSpec ArchSpec.h "lldb/Utility/ArchSpec.h" An architecture 25 /// specification class. 26 /// 27 /// A class designed to be created from a cpu type and subtype, a 28 /// string representation, or an llvm::Triple. Keeping all of the conversions 29 /// of strings to architecture enumeration values confined to this class 30 /// allows new architecture support to be added easily. 31 class ArchSpec { 32 public: 33 enum MIPSSubType { 34 eMIPSSubType_unknown, 35 eMIPSSubType_mips32, 36 eMIPSSubType_mips32r2, 37 eMIPSSubType_mips32r6, 38 eMIPSSubType_mips32el, 39 eMIPSSubType_mips32r2el, 40 eMIPSSubType_mips32r6el, 41 eMIPSSubType_mips64, 42 eMIPSSubType_mips64r2, 43 eMIPSSubType_mips64r6, 44 eMIPSSubType_mips64el, 45 eMIPSSubType_mips64r2el, 46 eMIPSSubType_mips64r6el, 47 }; 48 49 // Masks for the ases word of an ABI flags structure. 50 enum MIPSASE { 51 eMIPSAse_dsp = 0x00000001, // DSP ASE 52 eMIPSAse_dspr2 = 0x00000002, // DSP R2 ASE 53 eMIPSAse_eva = 0x00000004, // Enhanced VA Scheme 54 eMIPSAse_mcu = 0x00000008, // MCU (MicroController) ASE 55 eMIPSAse_mdmx = 0x00000010, // MDMX ASE 56 eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE 57 eMIPSAse_mt = 0x00000040, // MT ASE 58 eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE 59 eMIPSAse_virt = 0x00000100, // VZ ASE 60 eMIPSAse_msa = 0x00000200, // MSA ASE 61 eMIPSAse_mips16 = 0x00000400, // MIPS16 ASE 62 eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE 63 eMIPSAse_xpa = 0x00001000, // XPA ASE 64 eMIPSAse_mask = 0x00001fff, 65 eMIPSABI_O32 = 0x00002000, 66 eMIPSABI_N32 = 0x00004000, 67 eMIPSABI_N64 = 0x00008000, 68 eMIPSABI_O64 = 0x00020000, 69 eMIPSABI_EABI32 = 0x00040000, 70 eMIPSABI_EABI64 = 0x00080000, 71 eMIPSABI_mask = 0x000ff000 72 }; 73 74 // MIPS Floating point ABI Values 75 enum MIPS_ABI_FP { 76 eMIPS_ABI_FP_ANY = 0x00000000, 77 eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float 78 eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float 79 eMIPS_ABI_FP_SOFT = 0x00300000, // soft float 80 eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64 81 eMIPS_ABI_FP_XX = 0x00500000, // -mfpxx 82 eMIPS_ABI_FP_64 = 0x00600000, // -mips32r2 -mfp64 83 eMIPS_ABI_FP_64A = 0x00700000, // -mips32r2 -mfp64 -mno-odd-spreg 84 eMIPS_ABI_FP_mask = 0x00700000 85 }; 86 87 // ARM specific e_flags 88 enum ARMeflags { 89 eARM_abi_soft_float = 0x00000200, 90 eARM_abi_hard_float = 0x00000400 91 }; 92 93 enum RISCVeflags { 94 eRISCV_rvc = 0x00000001, /// RVC, +c 95 eRISCV_float_abi_soft = 0x00000000, /// soft float 96 eRISCV_float_abi_single = 0x00000002, /// single precision floating point, +f 97 eRISCV_float_abi_double = 0x00000004, /// double precision floating point, +d 98 eRISCV_float_abi_quad = 0x00000006, /// quad precision floating point, +q 99 eRISCV_float_abi_mask = 0x00000006, 100 eRISCV_rve = 0x00000008, /// RVE, +e 101 eRISCV_tso = 0x00000010, /// RVTSO (total store ordering) 102 }; 103 104 enum RISCVSubType { 105 eRISCVSubType_unknown, 106 eRISCVSubType_riscv32, 107 eRISCVSubType_riscv64, 108 }; 109 110 enum LoongArchSubType { 111 eLoongArchSubType_unknown, 112 eLoongArchSubType_loongarch32, 113 eLoongArchSubType_loongarch64, 114 }; 115 116 enum Core { 117 eCore_arm_generic, 118 eCore_arm_armv4, 119 eCore_arm_armv4t, 120 eCore_arm_armv5, 121 eCore_arm_armv5e, 122 eCore_arm_armv5t, 123 eCore_arm_armv6, 124 eCore_arm_armv6m, 125 eCore_arm_armv7, 126 eCore_arm_armv7a, 127 eCore_arm_armv7l, 128 eCore_arm_armv7f, 129 eCore_arm_armv7s, 130 eCore_arm_armv7k, 131 eCore_arm_armv7m, 132 eCore_arm_armv7em, 133 eCore_arm_xscale, 134 135 eCore_thumb, 136 eCore_thumbv4t, 137 eCore_thumbv5, 138 eCore_thumbv5e, 139 eCore_thumbv6, 140 eCore_thumbv6m, 141 eCore_thumbv7, 142 eCore_thumbv7s, 143 eCore_thumbv7k, 144 eCore_thumbv7f, 145 eCore_thumbv7m, 146 eCore_thumbv7em, 147 eCore_arm_arm64, 148 eCore_arm_armv8, 149 eCore_arm_armv8a, 150 eCore_arm_armv8l, 151 eCore_arm_arm64e, 152 eCore_arm_arm64_32, 153 eCore_arm_aarch64, 154 155 eCore_mips32, 156 eCore_mips32r2, 157 eCore_mips32r3, 158 eCore_mips32r5, 159 eCore_mips32r6, 160 eCore_mips32el, 161 eCore_mips32r2el, 162 eCore_mips32r3el, 163 eCore_mips32r5el, 164 eCore_mips32r6el, 165 eCore_mips64, 166 eCore_mips64r2, 167 eCore_mips64r3, 168 eCore_mips64r5, 169 eCore_mips64r6, 170 eCore_mips64el, 171 eCore_mips64r2el, 172 eCore_mips64r3el, 173 eCore_mips64r5el, 174 eCore_mips64r6el, 175 176 eCore_msp430, 177 178 eCore_ppc_generic, 179 eCore_ppc_ppc601, 180 eCore_ppc_ppc602, 181 eCore_ppc_ppc603, 182 eCore_ppc_ppc603e, 183 eCore_ppc_ppc603ev, 184 eCore_ppc_ppc604, 185 eCore_ppc_ppc604e, 186 eCore_ppc_ppc620, 187 eCore_ppc_ppc750, 188 eCore_ppc_ppc7400, 189 eCore_ppc_ppc7450, 190 eCore_ppc_ppc970, 191 192 eCore_ppc64le_generic, 193 eCore_ppc64_generic, 194 eCore_ppc64_ppc970_64, 195 196 eCore_s390x_generic, 197 198 eCore_sparc_generic, 199 200 eCore_sparc9_generic, 201 202 eCore_x86_32_i386, 203 eCore_x86_32_i486, 204 eCore_x86_32_i486sx, 205 eCore_x86_32_i686, 206 207 eCore_x86_64_x86_64, 208 eCore_x86_64_x86_64h, // Haswell enabled x86_64 209 eCore_hexagon_generic, 210 eCore_hexagon_hexagonv4, 211 eCore_hexagon_hexagonv5, 212 213 eCore_riscv32, 214 eCore_riscv64, 215 216 eCore_loongarch32, 217 eCore_loongarch64, 218 219 eCore_uknownMach32, 220 eCore_uknownMach64, 221 222 eCore_arc, // little endian ARC 223 224 eCore_avr, 225 226 eCore_wasm32, 227 228 kNumCores, 229 230 kCore_invalid, 231 // The following constants are used for wildcard matching only 232 kCore_any, 233 kCore_arm_any, 234 kCore_ppc_any, 235 kCore_ppc64_any, 236 kCore_x86_32_any, 237 kCore_x86_64_any, 238 kCore_hexagon_any, 239 240 kCore_arm_first = eCore_arm_generic, 241 kCore_arm_last = eCore_arm_xscale, 242 243 kCore_thumb_first = eCore_thumb, 244 kCore_thumb_last = eCore_thumbv7em, 245 246 kCore_ppc_first = eCore_ppc_generic, 247 kCore_ppc_last = eCore_ppc_ppc970, 248 249 kCore_ppc64_first = eCore_ppc64_generic, 250 kCore_ppc64_last = eCore_ppc64_ppc970_64, 251 252 kCore_x86_32_first = eCore_x86_32_i386, 253 kCore_x86_32_last = eCore_x86_32_i686, 254 255 kCore_x86_64_first = eCore_x86_64_x86_64, 256 kCore_x86_64_last = eCore_x86_64_x86_64h, 257 258 kCore_hexagon_first = eCore_hexagon_generic, 259 kCore_hexagon_last = eCore_hexagon_hexagonv5, 260 261 kCore_mips32_first = eCore_mips32, 262 kCore_mips32_last = eCore_mips32r6, 263 264 kCore_mips32el_first = eCore_mips32el, 265 kCore_mips32el_last = eCore_mips32r6el, 266 267 kCore_mips64_first = eCore_mips64, 268 kCore_mips64_last = eCore_mips64r6, 269 270 kCore_mips64el_first = eCore_mips64el, 271 kCore_mips64el_last = eCore_mips64r6el, 272 273 kCore_mips_first = eCore_mips32, 274 kCore_mips_last = eCore_mips64r6el 275 276 }; 277 278 /// Default constructor. 279 /// 280 /// Default constructor that initializes the object with invalid cpu type 281 /// and subtype values. 282 ArchSpec(); 283 284 /// Constructor over triple. 285 /// 286 /// Constructs an ArchSpec with properties consistent with the given Triple. 287 explicit ArchSpec(const llvm::Triple &triple); 288 explicit ArchSpec(const char *triple_cstr); 289 explicit ArchSpec(llvm::StringRef triple_str); 290 /// Constructor over architecture name. 291 /// 292 /// Constructs an ArchSpec with properties consistent with the given object 293 /// type and architecture name. 294 explicit ArchSpec(ArchitectureType arch_type, uint32_t cpu_type, 295 uint32_t cpu_subtype); 296 297 /// Destructor. 298 ~ArchSpec(); 299 300 /// Returns true if the OS, vendor and environment fields of the triple are 301 /// unset. The triple is expected to be normalized 302 /// (llvm::Triple::normalize). 303 static bool ContainsOnlyArch(const llvm::Triple &normalized_triple); 304 305 static void ListSupportedArchNames(StringList &list); 306 static void AutoComplete(CompletionRequest &request); 307 308 /// Returns a static string representing the current architecture. 309 /// 310 /// \return A static string corresponding to the current 311 /// architecture. 312 const char *GetArchitectureName() const; 313 314 /// if MIPS architecture return true. 315 /// 316 /// \return a boolean value. 317 bool IsMIPS() const; 318 319 /// Returns a string representing current architecture as a target CPU for 320 /// tools like compiler, disassembler etc. 321 /// 322 /// \return A string representing target CPU for the current 323 /// architecture. 324 std::string GetClangTargetCPU() const; 325 326 /// Return a string representing target application ABI. 327 /// 328 /// \return A string representing target application ABI. 329 std::string GetTargetABI() const; 330 331 /// Clears the object state. 332 /// 333 /// Clears the object state back to a default invalid state. 334 void Clear(); 335 336 /// Returns the size in bytes of an address of the current architecture. 337 /// 338 /// \return The byte size of an address of the current architecture. 339 uint32_t GetAddressByteSize() const; 340 341 /// Returns a machine family for the current architecture. 342 /// 343 /// \return An LLVM arch type. 344 llvm::Triple::ArchType GetMachine() const; 345 346 /// Tests if this ArchSpec is valid. 347 /// 348 /// \return True if the current architecture is valid, false 349 /// otherwise. IsValid()350 bool IsValid() const { 351 return m_core >= eCore_arm_generic && m_core < kNumCores; 352 } 353 explicit operator bool() const { return IsValid(); } 354 TripleVendorWasSpecified()355 bool TripleVendorWasSpecified() const { 356 return !m_triple.getVendorName().empty(); 357 } 358 TripleOSWasSpecified()359 bool TripleOSWasSpecified() const { return !m_triple.getOSName().empty(); } 360 TripleEnvironmentWasSpecified()361 bool TripleEnvironmentWasSpecified() const { 362 return m_triple.hasEnvironment(); 363 } 364 365 /// Merges fields from another ArchSpec into this ArchSpec. 366 /// 367 /// This will use the supplied ArchSpec to fill in any fields of the triple 368 /// in this ArchSpec which were unspecified. This can be used to refine a 369 /// generic ArchSpec with a more specific one. For example, if this 370 /// ArchSpec's triple is something like i386-unknown-unknown-unknown, and we 371 /// have a triple which is x64-pc-windows-msvc, then merging that triple 372 /// into this one will result in the triple i386-pc-windows-msvc. 373 /// 374 void MergeFrom(const ArchSpec &other); 375 376 /// Change the architecture object type, CPU type and OS type. 377 /// 378 /// \param[in] arch_type The object type of this ArchSpec. 379 /// 380 /// \param[in] cpu The required CPU type. 381 /// 382 /// \param[in] os The optional OS type 383 /// The default value of 0 was chosen to from the ELF spec value 384 /// ELFOSABI_NONE. ELF is the only one using this parameter. If another 385 /// format uses this parameter and 0 does not work, use a value over 386 /// 255 because in the ELF header this is value is only a byte. 387 /// 388 /// \return True if the object, and CPU were successfully set. 389 /// 390 /// As a side effect, the vendor value is usually set to unknown. The 391 /// exceptions are 392 /// aarch64-apple-ios 393 /// arm-apple-ios 394 /// thumb-apple-ios 395 /// x86-apple- 396 /// x86_64-apple- 397 /// 398 /// As a side effect, the os value is usually set to unknown The exceptions 399 /// are 400 /// *-*-aix 401 /// aarch64-apple-ios 402 /// arm-apple-ios 403 /// thumb-apple-ios 404 /// powerpc-apple-darwin 405 /// *-*-freebsd 406 /// *-*-linux 407 /// *-*-netbsd 408 /// *-*-openbsd 409 /// *-*-solaris 410 bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, 411 uint32_t os = 0); 412 413 /// Returns the byte order for the architecture specification. 414 /// 415 /// \return The endian enumeration for the current endianness of 416 /// the architecture specification 417 lldb::ByteOrder GetByteOrder() const; 418 419 /// Sets this ArchSpec's byte order. 420 /// 421 /// In the common case there is no need to call this method as the byte 422 /// order can almost always be determined by the architecture. However, many 423 /// CPU's are bi-endian (ARM, Alpha, PowerPC, etc) and the default/assumed 424 /// byte order may be incorrect. SetByteOrder(lldb::ByteOrder byte_order)425 void SetByteOrder(lldb::ByteOrder byte_order) { m_byte_order = byte_order; } 426 427 uint32_t GetMinimumOpcodeByteSize() const; 428 429 uint32_t GetMaximumOpcodeByteSize() const; 430 GetCore()431 Core GetCore() const { return m_core; } 432 433 uint32_t GetMachOCPUType() const; 434 435 uint32_t GetMachOCPUSubType() const; 436 437 /// Architecture data byte width accessor 438 /// 439 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 440 /// from the Architecture's data bus 441 uint32_t GetDataByteSize() const; 442 443 /// Architecture code byte width accessor 444 /// 445 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 446 /// from the Architecture's code bus 447 uint32_t GetCodeByteSize() const; 448 449 /// Architecture triple accessor. 450 /// 451 /// \return A triple describing this ArchSpec. GetTriple()452 llvm::Triple &GetTriple() { return m_triple; } 453 454 /// Architecture triple accessor. 455 /// 456 /// \return A triple describing this ArchSpec. GetTriple()457 const llvm::Triple &GetTriple() const { return m_triple; } 458 459 void DumpTriple(llvm::raw_ostream &s) const; 460 461 /// Architecture triple setter. 462 /// 463 /// Configures this ArchSpec according to the given triple. If the triple 464 /// has unknown components in all of the vendor, OS, and the optional 465 /// environment field (i.e. "i386-unknown-unknown") then default values are 466 /// taken from the host. Architecture and environment components are used 467 /// to further resolve the CPU type and subtype, endian characteristics, 468 /// etc. 469 /// 470 /// \return A triple describing this ArchSpec. 471 bool SetTriple(const llvm::Triple &triple); 472 473 bool SetTriple(llvm::StringRef triple_str); 474 475 /// Returns the default endianness of the architecture. 476 /// 477 /// \return The endian enumeration for the default endianness of 478 /// the architecture. 479 lldb::ByteOrder GetDefaultEndian() const; 480 481 /// Returns true if 'char' is a signed type by default in the architecture 482 /// false otherwise 483 /// 484 /// \return True if 'char' is a signed type by default on the 485 /// architecture and false otherwise. 486 bool CharIsSignedByDefault() const; 487 488 enum MatchType : bool { CompatibleMatch, ExactMatch }; 489 490 /// Compare this ArchSpec to another ArchSpec. \a match specifies the kind of 491 /// matching that is to be done. CompatibleMatch requires only a compatible 492 /// cpu type (e.g., armv7s is compatible with armv7). ExactMatch requires an 493 /// exact match (armv7s is not an exact match with armv7). 494 /// 495 /// \return true if the two ArchSpecs match. 496 bool IsMatch(const ArchSpec &rhs, MatchType match) const; 497 498 /// Shorthand for IsMatch(rhs, ExactMatch). IsExactMatch(const ArchSpec & rhs)499 bool IsExactMatch(const ArchSpec &rhs) const { 500 return IsMatch(rhs, ExactMatch); 501 } 502 503 /// Shorthand for IsMatch(rhs, CompatibleMatch). IsCompatibleMatch(const ArchSpec & rhs)504 bool IsCompatibleMatch(const ArchSpec &rhs) const { 505 return IsMatch(rhs, CompatibleMatch); 506 } 507 508 bool IsFullySpecifiedTriple() const; 509 510 /// Detect whether this architecture uses thumb code exclusively 511 /// 512 /// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can only execute 513 /// the Thumb instructions, never Arm. We should normally pick up 514 /// arm/thumbness from their the processor status bits (cpsr/xpsr) or hints 515 /// on each function - but when doing bare-boards low level debugging 516 /// (especially common with these embedded processors), we may not have 517 /// those things easily accessible. 518 /// 519 /// \return true if this is an arm ArchSpec which can only execute Thumb 520 /// instructions 521 bool IsAlwaysThumbInstructions() const; 522 GetFlags()523 uint32_t GetFlags() const { return m_flags; } 524 SetFlags(uint32_t flags)525 void SetFlags(uint32_t flags) { m_flags = flags; } 526 527 void SetFlags(const std::string &elf_abi); 528 529 protected: 530 void UpdateCore(); 531 532 llvm::Triple m_triple; 533 Core m_core = kCore_invalid; 534 lldb::ByteOrder m_byte_order = lldb::eByteOrderInvalid; 535 536 // Additional arch flags which we cannot get from triple and core For MIPS 537 // these are application specific extensions like micromips, mips16 etc. 538 uint32_t m_flags = 0; 539 540 // Called when m_def or m_entry are changed. Fills in all remaining members 541 // with default values. 542 void CoreUpdated(bool update_triple); 543 }; 544 545 /// \fn bool operator< (const ArchSpec& lhs, const ArchSpec& rhs) Less than 546 /// operator. 547 /// 548 /// Tests two ArchSpec objects to see if \a lhs is less than \a rhs. 549 /// 550 /// \param[in] lhs The Left Hand Side ArchSpec object to compare. \param[in] 551 /// rhs The Left Hand Side ArchSpec object to compare. 552 /// 553 /// \return true if \a lhs is less than \a rhs 554 bool operator<(const ArchSpec &lhs, const ArchSpec &rhs); 555 bool operator==(const ArchSpec &lhs, const ArchSpec &rhs); 556 557 bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch); 558 559 } // namespace lldb_private 560 561 #endif // LLDB_UTILITY_ARCHSPEC_H 562