1// cmd/7c/7.out.h from Vita Nuova. 2// https://bitbucket.org/plan9-from-bell-labs/9-cc/src/master/src/cmd/7c/7.out.h 3// 4// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 5// Portions Copyright © 1995-1997 C H Forsyth ([email protected]) 6// Portions Copyright © 1997-1999 Vita Nuova Limited 7// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com) 8// Portions Copyright © 2004,2006 Bruce Ellis 9// Portions Copyright © 2005-2007 C H Forsyth ([email protected]) 10// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others 11// Portions Copyright © 2009 The Go Authors. All rights reserved. 12// 13// Permission is hereby granted, free of charge, to any person obtaining a copy 14// of this software and associated documentation files (the "Software"), to deal 15// in the Software without restriction, including without limitation the rights 16// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17// copies of the Software, and to permit persons to whom the Software is 18// furnished to do so, subject to the following conditions: 19// 20// The above copyright notice and this permission notice shall be included in 21// all copies or substantial portions of the Software. 22// 23// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 26// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29// THE SOFTWARE. 30 31package arm64 32 33import "cmd/internal/obj" 34 35const ( 36 NSNAME = 8 37 NSYM = 50 38 NREG = 32 /* number of general registers */ 39 NFREG = 32 /* number of floating point registers */ 40) 41 42// General purpose registers, kept in the low bits of Prog.Reg. 43const ( 44 // integer 45 REG_R0 = obj.RBaseARM64 + iota 46 REG_R1 47 REG_R2 48 REG_R3 49 REG_R4 50 REG_R5 51 REG_R6 52 REG_R7 53 REG_R8 54 REG_R9 55 REG_R10 56 REG_R11 57 REG_R12 58 REG_R13 59 REG_R14 60 REG_R15 61 REG_R16 62 REG_R17 63 REG_R18 64 REG_R19 65 REG_R20 66 REG_R21 67 REG_R22 68 REG_R23 69 REG_R24 70 REG_R25 71 REG_R26 72 REG_R27 73 REG_R28 74 REG_R29 75 REG_R30 76 REG_R31 77 78 // scalar floating point 79 REG_F0 80 REG_F1 81 REG_F2 82 REG_F3 83 REG_F4 84 REG_F5 85 REG_F6 86 REG_F7 87 REG_F8 88 REG_F9 89 REG_F10 90 REG_F11 91 REG_F12 92 REG_F13 93 REG_F14 94 REG_F15 95 REG_F16 96 REG_F17 97 REG_F18 98 REG_F19 99 REG_F20 100 REG_F21 101 REG_F22 102 REG_F23 103 REG_F24 104 REG_F25 105 REG_F26 106 REG_F27 107 REG_F28 108 REG_F29 109 REG_F30 110 REG_F31 111 112 // SIMD 113 REG_V0 114 REG_V1 115 REG_V2 116 REG_V3 117 REG_V4 118 REG_V5 119 REG_V6 120 REG_V7 121 REG_V8 122 REG_V9 123 REG_V10 124 REG_V11 125 REG_V12 126 REG_V13 127 REG_V14 128 REG_V15 129 REG_V16 130 REG_V17 131 REG_V18 132 REG_V19 133 REG_V20 134 REG_V21 135 REG_V22 136 REG_V23 137 REG_V24 138 REG_V25 139 REG_V26 140 REG_V27 141 REG_V28 142 REG_V29 143 REG_V30 144 REG_V31 145 146 REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31 147) 148 149// bits 0-4 indicates register: Vn 150// bits 5-8 indicates arrangement: <T> 151const ( 152 REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T> 153 REG_ELEM // Vn.<T>[index] 154 REG_ELEM_END 155) 156 157// Not registers, but flags that can be combined with regular register 158// constants to indicate extended register conversion. When checking, 159// you should subtract obj.RBaseARM64 first. From this difference, bit 11 160// indicates extended register, bits 8-10 select the conversion mode. 161// REG_LSL is the index shift specifier, bit 9 indicates shifted offset register. 162const REG_LSL = obj.RBaseARM64 + 1<<9 163const REG_EXT = obj.RBaseARM64 + 1<<11 164 165const ( 166 REG_UXTB = REG_EXT + iota<<8 167 REG_UXTH 168 REG_UXTW 169 REG_UXTX 170 REG_SXTB 171 REG_SXTH 172 REG_SXTW 173 REG_SXTX 174) 175 176// Special registers, after subtracting obj.RBaseARM64, bit 12 indicates 177// a special register and the low bits select the register. 178// SYSREG_END is the last item in the automatically generated system register 179// declaration, and it is defined in the sysRegEnc.go file. 180// Define the special register after REG_SPECIAL, the first value of it should be 181// REG_{name} = SYSREG_END + iota. 182const ( 183 REG_SPECIAL = obj.RBaseARM64 + 1<<12 184) 185 186// Register assignments: 187// 188// compiler allocates R0 up as temps 189// compiler allocates register variables R7-R25 190// compiler allocates external registers R26 down 191// 192// compiler allocates register variables F7-F26 193// compiler allocates external registers F26 down 194const ( 195 REGMIN = REG_R7 // register variables allocated from here to REGMAX 196 REGRT1 = REG_R16 // ARM64 IP0, external linker may use as a scratch register in trampoline 197 REGRT2 = REG_R17 // ARM64 IP1, external linker may use as a scratch register in trampoline 198 REGPR = REG_R18 // ARM64 platform register, unused in the Go toolchain 199 REGMAX = REG_R25 200 201 REGCTXT = REG_R26 // environment for closures 202 REGTMP = REG_R27 // reserved for liblink 203 REGG = REG_R28 // G 204 REGFP = REG_R29 // frame pointer 205 REGLINK = REG_R30 206 207 // ARM64 uses R31 as both stack pointer and zero register, 208 // depending on the instruction. To differentiate RSP from ZR, 209 // we use a different numeric value for REGZERO and REGSP. 210 REGZERO = REG_R31 211 REGSP = REG_RSP 212 213 FREGRET = REG_F0 214 FREGMIN = REG_F7 // first register variable 215 FREGMAX = REG_F26 // last register variable for 7g only 216 FREGEXT = REG_F26 // first external register 217) 218 219// http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf 220var ARM64DWARFRegisters = map[int16]int16{ 221 REG_R0: 0, 222 REG_R1: 1, 223 REG_R2: 2, 224 REG_R3: 3, 225 REG_R4: 4, 226 REG_R5: 5, 227 REG_R6: 6, 228 REG_R7: 7, 229 REG_R8: 8, 230 REG_R9: 9, 231 REG_R10: 10, 232 REG_R11: 11, 233 REG_R12: 12, 234 REG_R13: 13, 235 REG_R14: 14, 236 REG_R15: 15, 237 REG_R16: 16, 238 REG_R17: 17, 239 REG_R18: 18, 240 REG_R19: 19, 241 REG_R20: 20, 242 REG_R21: 21, 243 REG_R22: 22, 244 REG_R23: 23, 245 REG_R24: 24, 246 REG_R25: 25, 247 REG_R26: 26, 248 REG_R27: 27, 249 REG_R28: 28, 250 REG_R29: 29, 251 REG_R30: 30, 252 253 // floating point 254 REG_F0: 64, 255 REG_F1: 65, 256 REG_F2: 66, 257 REG_F3: 67, 258 REG_F4: 68, 259 REG_F5: 69, 260 REG_F6: 70, 261 REG_F7: 71, 262 REG_F8: 72, 263 REG_F9: 73, 264 REG_F10: 74, 265 REG_F11: 75, 266 REG_F12: 76, 267 REG_F13: 77, 268 REG_F14: 78, 269 REG_F15: 79, 270 REG_F16: 80, 271 REG_F17: 81, 272 REG_F18: 82, 273 REG_F19: 83, 274 REG_F20: 84, 275 REG_F21: 85, 276 REG_F22: 86, 277 REG_F23: 87, 278 REG_F24: 88, 279 REG_F25: 89, 280 REG_F26: 90, 281 REG_F27: 91, 282 REG_F28: 92, 283 REG_F29: 93, 284 REG_F30: 94, 285 REG_F31: 95, 286 287 // SIMD 288 REG_V0: 64, 289 REG_V1: 65, 290 REG_V2: 66, 291 REG_V3: 67, 292 REG_V4: 68, 293 REG_V5: 69, 294 REG_V6: 70, 295 REG_V7: 71, 296 REG_V8: 72, 297 REG_V9: 73, 298 REG_V10: 74, 299 REG_V11: 75, 300 REG_V12: 76, 301 REG_V13: 77, 302 REG_V14: 78, 303 REG_V15: 79, 304 REG_V16: 80, 305 REG_V17: 81, 306 REG_V18: 82, 307 REG_V19: 83, 308 REG_V20: 84, 309 REG_V21: 85, 310 REG_V22: 86, 311 REG_V23: 87, 312 REG_V24: 88, 313 REG_V25: 89, 314 REG_V26: 90, 315 REG_V27: 91, 316 REG_V28: 92, 317 REG_V29: 93, 318 REG_V30: 94, 319 REG_V31: 95, 320} 321 322const ( 323 BIG = 2048 - 8 324) 325 326const ( 327 /* mark flags */ 328 LABEL = 1 << iota 329 LEAF 330 FLOAT 331 BRANCH 332 LOAD 333 FCMP 334 SYNC 335 LIST 336 FOLL 337 NOSCHED 338) 339 340const ( 341 // optab is sorted based on the order of these constants 342 // and the first match is chosen. 343 // The more specific class needs to come earlier. 344 C_NONE = iota + 1 // starting from 1, leave unclassified Addr's class as 0 345 C_REG // R0..R30 346 C_ZREG // R0..R30, ZR 347 C_RSP // R0..R30, RSP 348 C_FREG // F0..F31 349 C_VREG // V0..V31 350 C_PAIR // (Rn, Rm) 351 C_SHIFT // Rn<<2 352 C_EXTREG // Rn.UXTB[<<3] 353 C_SPR // REG_NZCV 354 C_COND // condition code, EQ, NE, etc. 355 C_SPOP // special operand, PLDL1KEEP, VMALLE1IS, etc. 356 C_ARNG // Vn.<T> 357 C_ELEM // Vn.<T>[index] 358 C_LIST // [V1, V2, V3] 359 360 C_ZCON // $0 361 C_ABCON0 // could be C_ADDCON0 or C_BITCON 362 C_ADDCON0 // 12-bit unsigned, unshifted 363 C_ABCON // could be C_ADDCON or C_BITCON 364 C_AMCON // could be C_ADDCON or C_MOVCON 365 C_ADDCON // 12-bit unsigned, shifted left by 0 or 12 366 C_MBCON // could be C_MOVCON or C_BITCON 367 C_MOVCON // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16 368 C_BITCON // bitfield and logical immediate masks 369 C_ADDCON2 // 24-bit constant 370 C_LCON // 32-bit constant 371 C_MOVCON2 // a constant that can be loaded with one MOVZ/MOVN and one MOVK 372 C_MOVCON3 // a constant that can be loaded with one MOVZ/MOVN and two MOVKs 373 C_VCON // 64-bit constant 374 C_FCON // floating-point constant 375 C_VCONADDR // 64-bit memory address 376 377 C_AACON // ADDCON offset in auto constant $a(FP) 378 C_AACON2 // 24-bit offset in auto constant $a(FP) 379 C_LACON // 32-bit offset in auto constant $a(FP) 380 C_AECON // ADDCON offset in extern constant $e(SB) 381 382 // TODO(aram): only one branch class should be enough 383 C_SBRA // for TYPE_BRANCH 384 C_LBRA 385 386 C_ZAUTO // 0(RSP) 387 C_NSAUTO_16 // -256 <= x < 0, 0 mod 16 388 C_NSAUTO_8 // -256 <= x < 0, 0 mod 8 389 C_NSAUTO_4 // -256 <= x < 0, 0 mod 4 390 C_NSAUTO // -256 <= x < 0 391 C_NPAUTO_16 // -512 <= x < 0, 0 mod 16 392 C_NPAUTO // -512 <= x < 0, 0 mod 8 393 C_NQAUTO_16 // -1024 <= x < 0, 0 mod 16 394 C_NAUTO4K // -4095 <= x < 0 395 C_PSAUTO_16 // 0 to 255, 0 mod 16 396 C_PSAUTO_8 // 0 to 255, 0 mod 8 397 C_PSAUTO_4 // 0 to 255, 0 mod 4 398 C_PSAUTO // 0 to 255 399 C_PPAUTO_16 // 0 to 504, 0 mod 16 400 C_PPAUTO // 0 to 504, 0 mod 8 401 C_PQAUTO_16 // 0 to 1008, 0 mod 16 402 C_UAUTO4K_16 // 0 to 4095, 0 mod 16 403 C_UAUTO4K_8 // 0 to 4095, 0 mod 8 404 C_UAUTO4K_4 // 0 to 4095, 0 mod 4 405 C_UAUTO4K_2 // 0 to 4095, 0 mod 2 406 C_UAUTO4K // 0 to 4095 407 C_UAUTO8K_16 // 0 to 8190, 0 mod 16 408 C_UAUTO8K_8 // 0 to 8190, 0 mod 8 409 C_UAUTO8K_4 // 0 to 8190, 0 mod 4 410 C_UAUTO8K // 0 to 8190, 0 mod 2 + C_PSAUTO 411 C_UAUTO16K_16 // 0 to 16380, 0 mod 16 412 C_UAUTO16K_8 // 0 to 16380, 0 mod 8 413 C_UAUTO16K // 0 to 16380, 0 mod 4 + C_PSAUTO 414 C_UAUTO32K_16 // 0 to 32760, 0 mod 16 + C_PSAUTO 415 C_UAUTO32K // 0 to 32760, 0 mod 8 + C_PSAUTO 416 C_UAUTO64K // 0 to 65520, 0 mod 16 + C_PSAUTO 417 C_LAUTOPOOL // any other constant up to 64 bits (needs pool literal) 418 C_LAUTO // any other constant up to 64 bits 419 420 C_SEXT1 // 0 to 4095, direct 421 C_SEXT2 // 0 to 8190 422 C_SEXT4 // 0 to 16380 423 C_SEXT8 // 0 to 32760 424 C_SEXT16 // 0 to 65520 425 C_LEXT 426 427 C_ZOREG // 0(R) 428 C_NSOREG_16 // must mirror C_NSAUTO_16, etc 429 C_NSOREG_8 430 C_NSOREG_4 431 C_NSOREG 432 C_NPOREG_16 433 C_NPOREG 434 C_NQOREG_16 435 C_NOREG4K 436 C_PSOREG_16 437 C_PSOREG_8 438 C_PSOREG_4 439 C_PSOREG 440 C_PPOREG_16 441 C_PPOREG 442 C_PQOREG_16 443 C_UOREG4K_16 444 C_UOREG4K_8 445 C_UOREG4K_4 446 C_UOREG4K_2 447 C_UOREG4K 448 C_UOREG8K_16 449 C_UOREG8K_8 450 C_UOREG8K_4 451 C_UOREG8K 452 C_UOREG16K_16 453 C_UOREG16K_8 454 C_UOREG16K 455 C_UOREG32K_16 456 C_UOREG32K 457 C_UOREG64K 458 C_LOREGPOOL 459 C_LOREG 460 461 C_ADDR // TODO(aram): explain difference from C_VCONADDR 462 463 // The GOT slot for a symbol in -dynlink mode. 464 C_GOTADDR 465 466 // TLS "var" in local exec mode: will become a constant offset from 467 // thread local base that is ultimately chosen by the program linker. 468 C_TLS_LE 469 470 // TLS "var" in initial exec mode: will become a memory address (chosen 471 // by the program linker) that the dynamic linker will fill with the 472 // offset from the thread local base. 473 C_TLS_IE 474 475 C_ROFF // register offset (including register extended) 476 477 C_GOK 478 C_TEXTSIZE 479 C_NCLASS // must be last 480) 481 482const ( 483 C_XPRE = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it 484 C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it 485) 486 487//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64 488 489const ( 490 AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota 491 AADCS 492 AADCSW 493 AADCW 494 AADD 495 AADDS 496 AADDSW 497 AADDW 498 AADR 499 AADRP 500 AAESD 501 AAESE 502 AAESIMC 503 AAESMC 504 AAND 505 AANDS 506 AANDSW 507 AANDW 508 AASR 509 AASRW 510 AAT 511 ABCC 512 ABCS 513 ABEQ 514 ABFI 515 ABFIW 516 ABFM 517 ABFMW 518 ABFXIL 519 ABFXILW 520 ABGE 521 ABGT 522 ABHI 523 ABHS 524 ABIC 525 ABICS 526 ABICSW 527 ABICW 528 ABLE 529 ABLO 530 ABLS 531 ABLT 532 ABMI 533 ABNE 534 ABPL 535 ABRK 536 ABVC 537 ABVS 538 ACASAD 539 ACASALB 540 ACASALD 541 ACASALH 542 ACASALW 543 ACASAW 544 ACASB 545 ACASD 546 ACASH 547 ACASLD 548 ACASLW 549 ACASPD 550 ACASPW 551 ACASW 552 ACBNZ 553 ACBNZW 554 ACBZ 555 ACBZW 556 ACCMN 557 ACCMNW 558 ACCMP 559 ACCMPW 560 ACINC 561 ACINCW 562 ACINV 563 ACINVW 564 ACLREX 565 ACLS 566 ACLSW 567 ACLZ 568 ACLZW 569 ACMN 570 ACMNW 571 ACMP 572 ACMPW 573 ACNEG 574 ACNEGW 575 ACRC32B 576 ACRC32CB 577 ACRC32CH 578 ACRC32CW 579 ACRC32CX 580 ACRC32H 581 ACRC32W 582 ACRC32X 583 ACSEL 584 ACSELW 585 ACSET 586 ACSETM 587 ACSETMW 588 ACSETW 589 ACSINC 590 ACSINCW 591 ACSINV 592 ACSINVW 593 ACSNEG 594 ACSNEGW 595 ADC 596 ADCPS1 597 ADCPS2 598 ADCPS3 599 ADMB 600 ADRPS 601 ADSB 602 ADWORD 603 AEON 604 AEONW 605 AEOR 606 AEORW 607 AERET 608 AEXTR 609 AEXTRW 610 AFABSD 611 AFABSS 612 AFADDD 613 AFADDS 614 AFCCMPD 615 AFCCMPED 616 AFCCMPES 617 AFCCMPS 618 AFCMPD 619 AFCMPED 620 AFCMPES 621 AFCMPS 622 AFCSELD 623 AFCSELS 624 AFCVTDH 625 AFCVTDS 626 AFCVTHD 627 AFCVTHS 628 AFCVTSD 629 AFCVTSH 630 AFCVTZSD 631 AFCVTZSDW 632 AFCVTZSS 633 AFCVTZSSW 634 AFCVTZUD 635 AFCVTZUDW 636 AFCVTZUS 637 AFCVTZUSW 638 AFDIVD 639 AFDIVS 640 AFLDPD 641 AFLDPQ 642 AFLDPS 643 AFMADDD 644 AFMADDS 645 AFMAXD 646 AFMAXNMD 647 AFMAXNMS 648 AFMAXS 649 AFMIND 650 AFMINNMD 651 AFMINNMS 652 AFMINS 653 AFMOVD 654 AFMOVQ 655 AFMOVS 656 AFMSUBD 657 AFMSUBS 658 AFMULD 659 AFMULS 660 AFNEGD 661 AFNEGS 662 AFNMADDD 663 AFNMADDS 664 AFNMSUBD 665 AFNMSUBS 666 AFNMULD 667 AFNMULS 668 AFRINTAD 669 AFRINTAS 670 AFRINTID 671 AFRINTIS 672 AFRINTMD 673 AFRINTMS 674 AFRINTND 675 AFRINTNS 676 AFRINTPD 677 AFRINTPS 678 AFRINTXD 679 AFRINTXS 680 AFRINTZD 681 AFRINTZS 682 AFSQRTD 683 AFSQRTS 684 AFSTPD 685 AFSTPQ 686 AFSTPS 687 AFSUBD 688 AFSUBS 689 AHINT 690 AHLT 691 AHVC 692 AIC 693 AISB 694 ALDADDAB 695 ALDADDAD 696 ALDADDAH 697 ALDADDALB 698 ALDADDALD 699 ALDADDALH 700 ALDADDALW 701 ALDADDAW 702 ALDADDB 703 ALDADDD 704 ALDADDH 705 ALDADDLB 706 ALDADDLD 707 ALDADDLH 708 ALDADDLW 709 ALDADDW 710 ALDAR 711 ALDARB 712 ALDARH 713 ALDARW 714 ALDAXP 715 ALDAXPW 716 ALDAXR 717 ALDAXRB 718 ALDAXRH 719 ALDAXRW 720 ALDCLRAB 721 ALDCLRAD 722 ALDCLRAH 723 ALDCLRALB 724 ALDCLRALD 725 ALDCLRALH 726 ALDCLRALW 727 ALDCLRAW 728 ALDCLRB 729 ALDCLRD 730 ALDCLRH 731 ALDCLRLB 732 ALDCLRLD 733 ALDCLRLH 734 ALDCLRLW 735 ALDCLRW 736 ALDEORAB 737 ALDEORAD 738 ALDEORAH 739 ALDEORALB 740 ALDEORALD 741 ALDEORALH 742 ALDEORALW 743 ALDEORAW 744 ALDEORB 745 ALDEORD 746 ALDEORH 747 ALDEORLB 748 ALDEORLD 749 ALDEORLH 750 ALDEORLW 751 ALDEORW 752 ALDORAB 753 ALDORAD 754 ALDORAH 755 ALDORALB 756 ALDORALD 757 ALDORALH 758 ALDORALW 759 ALDORAW 760 ALDORB 761 ALDORD 762 ALDORH 763 ALDORLB 764 ALDORLD 765 ALDORLH 766 ALDORLW 767 ALDORW 768 ALDP 769 ALDPSW 770 ALDPW 771 ALDXP 772 ALDXPW 773 ALDXR 774 ALDXRB 775 ALDXRH 776 ALDXRW 777 ALSL 778 ALSLW 779 ALSR 780 ALSRW 781 AMADD 782 AMADDW 783 AMNEG 784 AMNEGW 785 AMOVB 786 AMOVBU 787 AMOVD 788 AMOVH 789 AMOVHU 790 AMOVK 791 AMOVKW 792 AMOVN 793 AMOVNW 794 AMOVP 795 AMOVPD 796 AMOVPQ 797 AMOVPS 798 AMOVPSW 799 AMOVPW 800 AMOVW 801 AMOVWU 802 AMOVZ 803 AMOVZW 804 AMRS 805 AMSR 806 AMSUB 807 AMSUBW 808 AMUL 809 AMULW 810 AMVN 811 AMVNW 812 ANEG 813 ANEGS 814 ANEGSW 815 ANEGW 816 ANGC 817 ANGCS 818 ANGCSW 819 ANGCW 820 ANOOP 821 AORN 822 AORNW 823 AORR 824 AORRW 825 APRFM 826 APRFUM 827 ARBIT 828 ARBITW 829 AREM 830 AREMW 831 AREV 832 AREV16 833 AREV16W 834 AREV32 835 AREVW 836 AROR 837 ARORW 838 ASBC 839 ASBCS 840 ASBCSW 841 ASBCW 842 ASBFIZ 843 ASBFIZW 844 ASBFM 845 ASBFMW 846 ASBFX 847 ASBFXW 848 ASCVTFD 849 ASCVTFS 850 ASCVTFWD 851 ASCVTFWS 852 ASDIV 853 ASDIVW 854 ASEV 855 ASEVL 856 ASHA1C 857 ASHA1H 858 ASHA1M 859 ASHA1P 860 ASHA1SU0 861 ASHA1SU1 862 ASHA256H 863 ASHA256H2 864 ASHA256SU0 865 ASHA256SU1 866 ASHA512H 867 ASHA512H2 868 ASHA512SU0 869 ASHA512SU1 870 ASMADDL 871 ASMC 872 ASMNEGL 873 ASMSUBL 874 ASMULH 875 ASMULL 876 ASTLR 877 ASTLRB 878 ASTLRH 879 ASTLRW 880 ASTLXP 881 ASTLXPW 882 ASTLXR 883 ASTLXRB 884 ASTLXRH 885 ASTLXRW 886 ASTP 887 ASTPW 888 ASTXP 889 ASTXPW 890 ASTXR 891 ASTXRB 892 ASTXRH 893 ASTXRW 894 ASUB 895 ASUBS 896 ASUBSW 897 ASUBW 898 ASVC 899 ASWPAB 900 ASWPAD 901 ASWPAH 902 ASWPALB 903 ASWPALD 904 ASWPALH 905 ASWPALW 906 ASWPAW 907 ASWPB 908 ASWPD 909 ASWPH 910 ASWPLB 911 ASWPLD 912 ASWPLH 913 ASWPLW 914 ASWPW 915 ASXTB 916 ASXTBW 917 ASXTH 918 ASXTHW 919 ASXTW 920 ASYS 921 ASYSL 922 ATBNZ 923 ATBZ 924 ATLBI 925 ATST 926 ATSTW 927 AUBFIZ 928 AUBFIZW 929 AUBFM 930 AUBFMW 931 AUBFX 932 AUBFXW 933 AUCVTFD 934 AUCVTFS 935 AUCVTFWD 936 AUCVTFWS 937 AUDIV 938 AUDIVW 939 AUMADDL 940 AUMNEGL 941 AUMSUBL 942 AUMULH 943 AUMULL 944 AUREM 945 AUREMW 946 AUXTB 947 AUXTBW 948 AUXTH 949 AUXTHW 950 AUXTW 951 AVADD 952 AVADDP 953 AVADDV 954 AVAND 955 AVBCAX 956 AVBIF 957 AVBIT 958 AVBSL 959 AVCMEQ 960 AVCMTST 961 AVCNT 962 AVDUP 963 AVEOR 964 AVEOR3 965 AVEXT 966 AVFMLA 967 AVFMLS 968 AVLD1 969 AVLD1R 970 AVLD2 971 AVLD2R 972 AVLD3 973 AVLD3R 974 AVLD4 975 AVLD4R 976 AVMOV 977 AVMOVD 978 AVMOVI 979 AVMOVQ 980 AVMOVS 981 AVORR 982 AVPMULL 983 AVPMULL2 984 AVRAX1 985 AVRBIT 986 AVREV16 987 AVREV32 988 AVREV64 989 AVSHL 990 AVSLI 991 AVSRI 992 AVST1 993 AVST2 994 AVST3 995 AVST4 996 AVSUB 997 AVTBL 998 AVTBX 999 AVTRN1 1000 AVTRN2 1001 AVUADDLV 1002 AVUADDW 1003 AVUADDW2 1004 AVUMAX 1005 AVUMIN 1006 AVUSHLL 1007 AVUSHLL2 1008 AVUSHR 1009 AVUSRA 1010 AVUXTL 1011 AVUXTL2 1012 AVUZP1 1013 AVUZP2 1014 AVXAR 1015 AVZIP1 1016 AVZIP2 1017 AWFE 1018 AWFI 1019 AWORD 1020 AYIELD 1021 ALAST 1022 AB = obj.AJMP 1023 ABL = obj.ACALL 1024) 1025 1026const ( 1027 // shift types 1028 SHIFT_LL = 0 << 22 1029 SHIFT_LR = 1 << 22 1030 SHIFT_AR = 2 << 22 1031 SHIFT_ROR = 3 << 22 1032) 1033 1034// Arrangement for ARM64 SIMD instructions 1035const ( 1036 // arrangement types 1037 ARNG_8B = iota 1038 ARNG_16B 1039 ARNG_1D 1040 ARNG_4H 1041 ARNG_8H 1042 ARNG_2S 1043 ARNG_4S 1044 ARNG_2D 1045 ARNG_1Q 1046 ARNG_B 1047 ARNG_H 1048 ARNG_S 1049 ARNG_D 1050) 1051 1052//go:generate stringer -type SpecialOperand -trimprefix SPOP_ 1053type SpecialOperand int 1054 1055const ( 1056 // PRFM 1057 SPOP_PLDL1KEEP SpecialOperand = iota // must be the first one 1058 SPOP_BEGIN SpecialOperand = iota - 1 // set as the lower bound 1059 SPOP_PLDL1STRM 1060 SPOP_PLDL2KEEP 1061 SPOP_PLDL2STRM 1062 SPOP_PLDL3KEEP 1063 SPOP_PLDL3STRM 1064 SPOP_PLIL1KEEP 1065 SPOP_PLIL1STRM 1066 SPOP_PLIL2KEEP 1067 SPOP_PLIL2STRM 1068 SPOP_PLIL3KEEP 1069 SPOP_PLIL3STRM 1070 SPOP_PSTL1KEEP 1071 SPOP_PSTL1STRM 1072 SPOP_PSTL2KEEP 1073 SPOP_PSTL2STRM 1074 SPOP_PSTL3KEEP 1075 SPOP_PSTL3STRM 1076 1077 // TLBI 1078 SPOP_VMALLE1IS 1079 SPOP_VAE1IS 1080 SPOP_ASIDE1IS 1081 SPOP_VAAE1IS 1082 SPOP_VALE1IS 1083 SPOP_VAALE1IS 1084 SPOP_VMALLE1 1085 SPOP_VAE1 1086 SPOP_ASIDE1 1087 SPOP_VAAE1 1088 SPOP_VALE1 1089 SPOP_VAALE1 1090 SPOP_IPAS2E1IS 1091 SPOP_IPAS2LE1IS 1092 SPOP_ALLE2IS 1093 SPOP_VAE2IS 1094 SPOP_ALLE1IS 1095 SPOP_VALE2IS 1096 SPOP_VMALLS12E1IS 1097 SPOP_IPAS2E1 1098 SPOP_IPAS2LE1 1099 SPOP_ALLE2 1100 SPOP_VAE2 1101 SPOP_ALLE1 1102 SPOP_VALE2 1103 SPOP_VMALLS12E1 1104 SPOP_ALLE3IS 1105 SPOP_VAE3IS 1106 SPOP_VALE3IS 1107 SPOP_ALLE3 1108 SPOP_VAE3 1109 SPOP_VALE3 1110 SPOP_VMALLE1OS 1111 SPOP_VAE1OS 1112 SPOP_ASIDE1OS 1113 SPOP_VAAE1OS 1114 SPOP_VALE1OS 1115 SPOP_VAALE1OS 1116 SPOP_RVAE1IS 1117 SPOP_RVAAE1IS 1118 SPOP_RVALE1IS 1119 SPOP_RVAALE1IS 1120 SPOP_RVAE1OS 1121 SPOP_RVAAE1OS 1122 SPOP_RVALE1OS 1123 SPOP_RVAALE1OS 1124 SPOP_RVAE1 1125 SPOP_RVAAE1 1126 SPOP_RVALE1 1127 SPOP_RVAALE1 1128 SPOP_RIPAS2E1IS 1129 SPOP_RIPAS2LE1IS 1130 SPOP_ALLE2OS 1131 SPOP_VAE2OS 1132 SPOP_ALLE1OS 1133 SPOP_VALE2OS 1134 SPOP_VMALLS12E1OS 1135 SPOP_RVAE2IS 1136 SPOP_RVALE2IS 1137 SPOP_IPAS2E1OS 1138 SPOP_RIPAS2E1 1139 SPOP_RIPAS2E1OS 1140 SPOP_IPAS2LE1OS 1141 SPOP_RIPAS2LE1 1142 SPOP_RIPAS2LE1OS 1143 SPOP_RVAE2OS 1144 SPOP_RVALE2OS 1145 SPOP_RVAE2 1146 SPOP_RVALE2 1147 SPOP_ALLE3OS 1148 SPOP_VAE3OS 1149 SPOP_VALE3OS 1150 SPOP_RVAE3IS 1151 SPOP_RVALE3IS 1152 SPOP_RVAE3OS 1153 SPOP_RVALE3OS 1154 SPOP_RVAE3 1155 SPOP_RVALE3 1156 1157 // DC 1158 SPOP_IVAC 1159 SPOP_ISW 1160 SPOP_CSW 1161 SPOP_CISW 1162 SPOP_ZVA 1163 SPOP_CVAC 1164 SPOP_CVAU 1165 SPOP_CIVAC 1166 SPOP_IGVAC 1167 SPOP_IGSW 1168 SPOP_IGDVAC 1169 SPOP_IGDSW 1170 SPOP_CGSW 1171 SPOP_CGDSW 1172 SPOP_CIGSW 1173 SPOP_CIGDSW 1174 SPOP_GVA 1175 SPOP_GZVA 1176 SPOP_CGVAC 1177 SPOP_CGDVAC 1178 SPOP_CGVAP 1179 SPOP_CGDVAP 1180 SPOP_CGVADP 1181 SPOP_CGDVADP 1182 SPOP_CIGVAC 1183 SPOP_CIGDVAC 1184 SPOP_CVAP 1185 SPOP_CVADP 1186 1187 // PSTATE fields 1188 SPOP_DAIFSet 1189 SPOP_DAIFClr 1190 1191 // Condition code, EQ, NE, etc. Their relative order to EQ is matter. 1192 SPOP_EQ 1193 SPOP_NE 1194 SPOP_HS 1195 SPOP_LO 1196 SPOP_MI 1197 SPOP_PL 1198 SPOP_VS 1199 SPOP_VC 1200 SPOP_HI 1201 SPOP_LS 1202 SPOP_GE 1203 SPOP_LT 1204 SPOP_GT 1205 SPOP_LE 1206 SPOP_AL 1207 SPOP_NV 1208 // Condition code end. 1209 1210 SPOP_END 1211) 1212