1// Copyright 2017 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5package cpu
6
7// CacheLinePadSize is used to prevent false sharing of cache lines.
8// We choose 128 because Apple Silicon, a.k.a. M1, has 128-byte cache line size.
9// It doesn't cost much and is much more future-proof.
10const CacheLinePadSize = 128
11
12func doinit() {
13	options = []option{
14		{Name: "aes", Feature: &ARM64.HasAES},
15		{Name: "pmull", Feature: &ARM64.HasPMULL},
16		{Name: "sha1", Feature: &ARM64.HasSHA1},
17		{Name: "sha2", Feature: &ARM64.HasSHA2},
18		{Name: "sha512", Feature: &ARM64.HasSHA512},
19		{Name: "crc32", Feature: &ARM64.HasCRC32},
20		{Name: "atomics", Feature: &ARM64.HasATOMICS},
21		{Name: "cpuid", Feature: &ARM64.HasCPUID},
22		{Name: "isNeoverse", Feature: &ARM64.IsNeoverse},
23	}
24
25	// arm64 uses different ways to detect CPU features at runtime depending on the operating system.
26	osInit()
27}
28
29func getisar0() uint64
30
31func getMIDR() uint64
32
33func extractBits(data uint64, start, end uint) uint {
34	return (uint)(data>>start) & ((1 << (end - start + 1)) - 1)
35}
36
37func parseARM64SystemRegisters(isar0 uint64) {
38	// ID_AA64ISAR0_EL1
39	switch extractBits(isar0, 4, 7) {
40	case 1:
41		ARM64.HasAES = true
42	case 2:
43		ARM64.HasAES = true
44		ARM64.HasPMULL = true
45	}
46
47	switch extractBits(isar0, 8, 11) {
48	case 1:
49		ARM64.HasSHA1 = true
50	}
51
52	switch extractBits(isar0, 12, 15) {
53	case 1:
54		ARM64.HasSHA2 = true
55	case 2:
56		ARM64.HasSHA2 = true
57		ARM64.HasSHA512 = true
58	}
59
60	switch extractBits(isar0, 16, 19) {
61	case 1:
62		ARM64.HasCRC32 = true
63	}
64
65	switch extractBits(isar0, 20, 23) {
66	case 2:
67		ARM64.HasATOMICS = true
68	}
69}
70