1 /*
2 * Copyright (c) 2015 Google Inc. All rights reserved
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <debug.h>
25 #include <dev/timer/arm_generic.h>
26 #include <err.h>
27 #include <inttypes.h>
28 #include <kernel/vm.h>
29 #include <lib/device_tree/libfdt_helpers.h>
30 #include <lk/init.h>
31 #include <platform/gic.h>
32 #include <string.h>
33 #include <sys/types.h>
34 #include <vsock/vsock.h>
35
36 #include "debug.h"
37
38 #if ARM64_BOOT_PROTOCOL_X0_MEMSIZE || ARCH_ARM
39 #include "smc.h"
40 #endif
41
42 #ifdef GIC_VERSION
43 #include <dev/interrupt/arm_gic.h>
44
45 #define ARM_GENERIC_TIMER_INT_CNTV 27
46 #define ARM_GENERIC_TIMER_INT_CNTPS 29
47 #define ARM_GENERIC_TIMER_INT_CNTP 30
48
49 #define ARM_GENERIC_TIMER_INT_SELECTED(timer) ARM_GENERIC_TIMER_INT_##timer
50 #define XARM_GENERIC_TIMER_INT_SELECTED(timer) \
51 ARM_GENERIC_TIMER_INT_SELECTED(timer)
52 #define ARM_GENERIC_TIMER_INT \
53 XARM_GENERIC_TIMER_INT_SELECTED(TIMER_ARM_GENERIC_SELECTED)
54
55 #if GIC_VERSION <= 2
56 #define GICC_SIZE (0x1000)
57 #define GICD_SIZE (0x1000)
58 #define GICR_SIZE (0)
59 #else
60 #define GICC_SIZE (0x10000)
61 #define GICD_SIZE (0x10000)
62 #if GIC_VERSION < 4
63 #define GICR_SIZE (0x20000 * SMP_MAX_CPUS)
64 #else
65 #define GICR_SIZE (0x40000 * SMP_MAX_CPUS)
66 #endif
67 #endif
68 #elif HAFNIUM
69 #include <hf/types.h>
70 #define ARM_GENERIC_TIMER_INT HF_VIRTUAL_TIMER_INTID
71 #else
72 #error "Unknown interrupt library"
73 #endif
74
75 extern ulong lk_boot_args[4];
76
77 #if ARM64_BOOT_PROTOCOL_X0_DTB
generic_arm64_reserve_device_tree(paddr_t ram_base,size_t ram_size)78 static void generic_arm64_reserve_device_tree(paddr_t ram_base,
79 size_t ram_size) {
80 struct list_node list;
81 list_initialize(&list);
82
83 paddr_t fdt_paddr = lk_boot_args[0];
84 if (fdt_paddr < ram_base || fdt_paddr - ram_base >= ram_size) {
85 /* fdt address is outside ram_arena, no need to reserve it */
86 return;
87 }
88 const void* fdt = paddr_to_kvaddr(fdt_paddr);
89 if (fdt_check_header(fdt)) {
90 return;
91 }
92 size_t fdt_size = fdt_totalsize(fdt);
93 /* if fdt_paddr is not page aligned add offset in first page to size */
94 fdt_size += fdt_paddr & (PAGE_SIZE - 1);
95 uint fdt_page_count = DIV_ROUND_UP(fdt_size, PAGE_SIZE);
96 uint fdt_reserved_page_count =
97 pmm_alloc_range(fdt_paddr, fdt_page_count, &list);
98 if (fdt_page_count != fdt_reserved_page_count) {
99 panic("failed to reserve memory for device tree");
100 }
101 }
102 #endif
103
104 /* initial memory mappings. parsed by start.S */
105 struct mmu_initial_mapping mmu_initial_mappings[] = {
106 /* Mark next entry as dynamic as it might be updated
107 by platform_reset code to specify actual size and
108 location of RAM to use */
109 {.phys = MEMBASE + KERNEL_LOAD_OFFSET,
110 .virt = KERNEL_BASE + KERNEL_LOAD_OFFSET,
111 .size = MEMSIZE,
112 .flags = MMU_INITIAL_MAPPING_FLAG_DYNAMIC,
113 .name = "ram"},
114
115 /* null entry to terminate the list */
116 {0, 0, 0, 0, 0}};
117
118 static pmm_arena_t ram_arena = {.name = "ram",
119 .base = MEMBASE + KERNEL_LOAD_OFFSET,
120 .size = MEMSIZE,
121 .flags = PMM_ARENA_FLAG_KMAP};
122
platform_init_mmu_mappings(void)123 void platform_init_mmu_mappings(void) {
124 /* go through mmu_initial_mapping to find dynamic entry
125 * matching ram_arena (by name) and adjust it.
126 */
127 struct mmu_initial_mapping* m = mmu_initial_mappings;
128 for (uint i = 0; i < countof(mmu_initial_mappings); i++, m++) {
129 if (!(m->flags & MMU_INITIAL_MAPPING_FLAG_DYNAMIC))
130 continue;
131
132 if (strcmp(m->name, ram_arena.name) == 0) {
133 /* update ram_arena */
134 ram_arena.base = m->phys;
135 ram_arena.size = m->size;
136 ram_arena.flags = PMM_ARENA_FLAG_KMAP;
137
138 break;
139 }
140 }
141 pmm_add_arena(&ram_arena);
142 #if ARM64_BOOT_PROTOCOL_X0_DTB
143 generic_arm64_reserve_device_tree(ram_arena.base, ram_arena.size);
144 #endif
145 }
146
147 #if ARM64_BOOT_PROTOCOL_X0_MEMSIZE || ARCH_ARM
148
generic_arm64_get_reg_base(int reg)149 static paddr_t generic_arm64_get_reg_base(int reg) {
150 #if ARCH_ARM64
151 return generic_arm64_smc(SMC_FC64_GET_REG_BASE, reg, 0, 0);
152 #else
153 return generic_arm64_smc(SMC_FC_GET_REG_BASE, reg, 0, 0);
154 #endif
155 }
156
157 #endif
158
pci_init_fdt(const void * fdt)159 int static pci_init_fdt(const void* fdt) {
160 int fdt_pci_offset =
161 fdt_node_offset_by_compatible(fdt, 0, "pci-host-cam-generic");
162 if (fdt_pci_offset < 0) {
163 dprintf(CRITICAL, "failed to find pci device tree node\n");
164 return ERR_NOT_FOUND;
165 }
166
167 paddr_t pci_paddr;
168 size_t pci_size;
169 int ret = fdt_helper_get_reg(fdt, fdt_pci_offset, 0, &pci_paddr, &pci_size);
170 if (ret) {
171 dprintf(CRITICAL, "failed to find get reg, err %d\n", ret);
172 return ERR_NOT_VALID;
173 }
174
175 return pci_init_mmio(pci_paddr, pci_size, 1 << 11);
176 }
177
platform_after_vm_init(uint level)178 static void platform_after_vm_init(uint level) {
179 #ifdef GIC_VERSION
180 #if ARM64_BOOT_PROTOCOL_X0_MEMSIZE || ARCH_ARM
181 paddr_t gicc = generic_arm64_get_reg_base(SMC_GET_GIC_BASE_GICC);
182 paddr_t gicd = generic_arm64_get_reg_base(SMC_GET_GIC_BASE_GICD);
183 paddr_t gicr = generic_arm64_get_reg_base(SMC_GET_GIC_BASE_GICR);
184 #elif ARM64_BOOT_PROTOCOL_X0_DTB
185 int ret;
186 void* fdt;
187 size_t fdt_size;
188 paddr_t fdt_paddr = lk_boot_args[0];
189 ret = vmm_alloc_physical(
190 vmm_get_kernel_aspace(), "device_tree_probe", PAGE_SIZE, &fdt, 0,
191 fdt_paddr, 0, ARCH_MMU_FLAG_PERM_NO_EXECUTE | ARCH_MMU_FLAG_CACHED);
192 if (ret) {
193 dprintf(CRITICAL,
194 "failed to map device tree page at 0x%" PRIxPADDR ": %d\n",
195 fdt_paddr, ret);
196 return;
197 }
198 if (fdt_check_header(fdt)) {
199 dprintf(CRITICAL, "invalid device tree at 0x%" PRIxPADDR ": %d\n",
200 fdt_paddr, ret);
201 return;
202 }
203 fdt_size = fdt_totalsize(fdt);
204 if (fdt_size > PAGE_SIZE) {
205 fdt_size = page_align(fdt_size);
206 dprintf(INFO, "remapping device tree with size 0x%zx\n", fdt_size);
207 vmm_free_region(vmm_get_kernel_aspace(), (vaddr_t)fdt);
208 ret = vmm_alloc_physical(
209 vmm_get_kernel_aspace(), "device_tree_full", fdt_size, &fdt, 0,
210 fdt_paddr, 0,
211 ARCH_MMU_FLAG_PERM_NO_EXECUTE | ARCH_MMU_FLAG_CACHED);
212 if (ret) {
213 dprintf(CRITICAL,
214 "failed to map device tree at 0x%" PRIxPADDR
215 " sz 0x%zx: %d\n",
216 fdt_paddr, fdt_size, ret);
217 return;
218 }
219 }
220
221 generic_arm64_setup_uart(fdt);
222
223 int fdt_gic_offset = fdt_node_offset_by_compatible(fdt, 0, "arm,gic-v3");
224 paddr_t gicc = 0; /* gic-v3 does not need a memory mapped gicc */
225 paddr_t gicd, gicr;
226 size_t gicd_size, gicr_size;
227 if (fdt_helper_get_reg(fdt, fdt_gic_offset, 0, &gicd, &gicd_size)) {
228 dprintf(CRITICAL, "failed get gicd regs, offset %d\n", fdt_gic_offset);
229 return;
230 }
231 if (fdt_helper_get_reg(fdt, fdt_gic_offset, 1, &gicr, &gicr_size)) {
232 dprintf(CRITICAL, "failed get gicr regs, offset %d\n", fdt_gic_offset);
233 return;
234 }
235 if (gicd_size != GICD_SIZE) {
236 dprintf(CRITICAL, "unexpected gicd_size %zd != %d\n", gicd_size,
237 GICD_SIZE);
238 return;
239 }
240 if (gicr_size < GICR_SIZE) {
241 dprintf(CRITICAL, "unexpected gicr_size %zd < %d\n", gicr_size,
242 GICR_SIZE);
243 return;
244 }
245 #else
246 #error "Unknown ARM64_BOOT_PROTOCOL"
247 #endif
248 dprintf(SPEW,
249 "gicc 0x%" PRIxPADDR ", gicd 0x%" PRIxPADDR ", gicr 0x%" PRIxPADDR
250 "\n",
251 gicc, gicd, gicr);
252
253 /* initialize the interrupt controller */
254 struct arm_gic_init_info init_info = {
255 .gicc_paddr = gicc,
256 .gicc_size = GICC_SIZE,
257 .gicd_paddr = gicd,
258 .gicd_size = GICD_SIZE,
259 .gicr_paddr = gicr,
260 .gicr_size = GICR_SIZE,
261 };
262 arm_gic_init_map(&init_info);
263 #endif /* GIC_VERSION */
264
265 /* initialize the timer block */
266 arm_generic_timer_init(ARM_GENERIC_TIMER_INT, 0);
267
268 #if ARM64_BOOT_PROTOCOL_X0_DTB
269 pci_init_fdt(fdt); /* ignore pci init errors */
270 #endif
271 }
272
273 LK_INIT_HOOK(platform_after_vm, platform_after_vm_init, LK_INIT_LEVEL_VM + 1);
274