1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State, Mode and Error functions
11 *
12 @verbatim
13 ==============================================================================
14 ##### How to use this driver #####
15 ==============================================================================
16 [..]
17 The I2C HAL driver can be used as follows:
18
19 (#) Declare a I2C_HandleTypeDef handle structure, for example:
20 I2C_HandleTypeDef hi2c;
21
22 (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
23 (##) Enable the I2Cx interface clock
24 (##) I2C pins configuration
25 (+++) Enable the clock for the I2C GPIOs
26 (+++) Configure I2C pins as alternate function open-drain
27 (##) NVIC configuration if you need to use interrupt process
28 (+++) Configure the I2Cx interrupt priority
29 (+++) Enable the NVIC I2C IRQ Channel
30 (##) DMA Configuration if you need to use DMA process
31 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
32 (+++) Enable the DMAx interface clock using
33 (+++) Configure the DMA handle parameters
34 (+++) Configure the DMA Tx or Rx stream
35 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
36 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
37 the DMA Tx or Rx stream
38
39 (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
40 Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
41
42 (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
43 (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit() API.
44
45 (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
46
47 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
48
49 *** Polling mode IO operation ***
50 =================================
51 [..]
52 (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
53 (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
54 (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
55 (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
56
57 *** Polling mode IO MEM operation ***
58 =====================================
59 [..]
60 (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
61 (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
62
63
64 *** Interrupt mode IO operation ***
65 ===================================
66 [..]
67 (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
68 (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
69 add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
70 (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
71 (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
72 add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
73 (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
74 (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
75 add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
76 (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
77 (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
78 add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
79 (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
80 add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
81 (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
82 (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
83 add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
84
85 *** Interrupt mode or DMA mode IO sequential operation ***
86 ==========================================================
87 [..]
88 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
89 when a direction change during transfer
90 [..]
91 (+) A specific option field manage the different steps of a sequential transfer
92 (+) Option field values are defined through @ref I2C_XferOptions_definition and are listed below:
93 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
94 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
95 and data to transfer without a final stop condition
96 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
97 and data to transfer without a final stop condition, an then permit a call the same master sequential interface
98 several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
99 or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
100 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
101 and with new data to transfer if the direction change or manage only the new data to transfer
102 if no direction change and without a final stop condition in both cases
103 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
104 and with new data to transfer if the direction change or manage only the new data to transfer
105 if no direction change and with a final stop condition in both cases
106 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
107 interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
108 Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
109 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
110 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
111 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
112 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
113 without stopping the communication and so generate a restart condition.
114 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
115 interface.
116 Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
117 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
118 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
119 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
120 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
121
122 (+) Differents sequential I2C interfaces are listed below:
123 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
124 or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
125 (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
126 add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
127 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
128 or using @ref HAL_I2C_Master_Seq_Receive_DMA()
129 (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
130 add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
131 (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
132 (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
133 add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
134 (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
135 (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
136 add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
137 (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
138 add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
139 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
140 or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
141 (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
142 add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
143 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
144 or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
145 (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
146 add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
147 (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
148 add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
149
150 *** Interrupt mode IO MEM operation ***
151 =======================================
152 [..]
153 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
154 @ref HAL_I2C_Mem_Write_IT()
155 (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
156 add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
157 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
158 @ref HAL_I2C_Mem_Read_IT()
159 (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
160 add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
161 (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
162 add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
163
164 *** DMA mode IO operation ***
165 ==============================
166 [..]
167 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
168 @ref HAL_I2C_Master_Transmit_DMA()
169 (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
170 add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
171 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
172 @ref HAL_I2C_Master_Receive_DMA()
173 (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
174 add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
175 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
176 @ref HAL_I2C_Slave_Transmit_DMA()
177 (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
178 add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
179 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
180 @ref HAL_I2C_Slave_Receive_DMA()
181 (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
182 add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
183 (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
184 add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
185 (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
186 (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
187 add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
188
189 *** DMA mode IO MEM operation ***
190 =================================
191 [..]
192 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
193 @ref HAL_I2C_Mem_Write_DMA()
194 (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
195 add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
196 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
197 @ref HAL_I2C_Mem_Read_DMA()
198 (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
199 add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
200 (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
201 add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
202
203
204 *** I2C HAL driver macros list ***
205 ==================================
206 [..]
207 Below the list of most used macros in I2C HAL driver.
208
209 (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
210 (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
211 (+) @ref __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not
212 (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
213 (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
214 (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
215
216 *** Callback registration ***
217 =============================================
218
219 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
220 allows the user to configure dynamically the driver callbacks.
221 Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
222 to register an interrupt callback.
223
224 Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
225 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
226 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
227 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
228 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
229 (+) ListenCpltCallback : callback for end of listen mode.
230 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
231 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
232 (+) ErrorCallback : callback for error detection.
233 (+) AbortCpltCallback : callback for abort completion process.
234 (+) MspInitCallback : callback for Msp Init.
235 (+) MspDeInitCallback : callback for Msp DeInit.
236 This function takes as parameters the HAL peripheral handle, the Callback ID
237 and a pointer to the user callback function.
238
239 For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
240
241 Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
242 weak function.
243 @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
244 and the Callback ID.
245 This function allows to reset following callbacks:
246 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
247 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
248 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
249 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
250 (+) ListenCpltCallback : callback for end of listen mode.
251 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
252 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
253 (+) ErrorCallback : callback for error detection.
254 (+) AbortCpltCallback : callback for abort completion process.
255 (+) MspInitCallback : callback for Msp Init.
256 (+) MspDeInitCallback : callback for Msp DeInit.
257
258 For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
259
260 By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
261 all callbacks are set to the corresponding weak functions:
262 examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
263 Exception done for MspInit and MspDeInit functions that are
264 reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
265 these callbacks are null (not registered beforehand).
266 If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
267 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
268
269 Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
270 Exception done MspInit/MspDeInit functions that can be registered/unregistered
271 in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
272 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
273 Then, the user first registers the MspInit/MspDeInit user callbacks
274 using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
275 or @ref HAL_I2C_Init() function.
276
277 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
278 not defined, the callback registration feature is not available and all callbacks
279 are set to the corresponding weak functions.
280
281
282
283 [..]
284 (@) You can refer to the I2C HAL driver header file for more useful macros
285
286 @endverbatim
287 ******************************************************************************
288 * @attention
289 *
290 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
291 * All rights reserved.</center></h2>
292 *
293 * This software component is licensed by ST under BSD 3-Clause license,
294 * the "License"; You may not use this file except in compliance with the
295 * License. You may obtain a copy of the License at:
296 * opensource.org/licenses/BSD-3-Clause
297 *
298 ******************************************************************************
299 */
300
301 /* Includes ------------------------------------------------------------------*/
302 #include "stm32f4xx_hal.h"
303
304 /** @addtogroup STM32F4xx_HAL_Driver
305 * @{
306 */
307
308 /** @defgroup I2C I2C
309 * @brief I2C HAL module driver
310 * @{
311 */
312
313 #ifdef HAL_I2C_MODULE_ENABLED
314
315 /* Private typedef -----------------------------------------------------------*/
316 /* Private define ------------------------------------------------------------*/
317 /** @addtogroup I2C_Private_Define
318 * @{
319 */
320 #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
321 #define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
322 #define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
323
324 /* Private define for @ref PreviousState usage */
325 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
326 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
327 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
328 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
329 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
330 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
331
332 /**
333 * @}
334 */
335
336 /* Private macro -------------------------------------------------------------*/
337 /* Private variables ---------------------------------------------------------*/
338 /* Private function prototypes -----------------------------------------------*/
339
340 /** @defgroup I2C_Private_Functions I2C Private Functions
341 * @{
342 */
343 /* Private functions to handle DMA transfer */
344 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
345 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
346 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
347
348 static void I2C_ITError(I2C_HandleTypeDef *hi2c);
349
350 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
351 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
352 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
353 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
354
355 /* Private functions to handle flags during polling transfer */
356 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
357 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
358 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
359 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
360 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
361 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
362 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
363
364 /* Private functions for I2C transfer IRQ handler */
365 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
366 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
367 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
368 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
369 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c);
370 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
371 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
372
373 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
374 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
375 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
376 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
377 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags);
378 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
379 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
380
381 /* Private function to Convert Specific options */
382 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
383 /**
384 * @}
385 */
386
387 /* Exported functions --------------------------------------------------------*/
388
389 /** @defgroup I2C_Exported_Functions I2C Exported Functions
390 * @{
391 */
392
393 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
394 * @brief Initialization and Configuration functions
395 *
396 @verbatim
397 ===============================================================================
398 ##### Initialization and de-initialization functions #####
399 ===============================================================================
400 [..] This subsection provides a set of functions allowing to initialize and
401 deinitialize the I2Cx peripheral:
402
403 (+) User must Implement HAL_I2C_MspInit() function in which he configures
404 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
405
406 (+) Call the function HAL_I2C_Init() to configure the selected device with
407 the selected configuration:
408 (++) Communication Speed
409 (++) Duty cycle
410 (++) Addressing mode
411 (++) Own Address 1
412 (++) Dual Addressing mode
413 (++) Own Address 2
414 (++) General call mode
415 (++) Nostretch mode
416
417 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
418 of the selected I2Cx peripheral.
419
420 @endverbatim
421 * @{
422 */
423
424 /**
425 * @brief Initializes the I2C according to the specified parameters
426 * in the I2C_InitTypeDef and initialize the associated handle.
427 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
428 * the configuration information for the specified I2C.
429 * @retval HAL status
430 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)431 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
432 {
433 uint32_t freqrange;
434 uint32_t pclk1;
435
436 /* Check the I2C handle allocation */
437 if (hi2c == NULL)
438 {
439 return HAL_ERROR;
440 }
441
442 /* Check the parameters */
443 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
444 assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
445 assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
446 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
447 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
448 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
449 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
450 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
451 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
452
453 if (hi2c->State == HAL_I2C_STATE_RESET)
454 {
455 /* Allocate lock resource and initialize it */
456 hi2c->Lock = HAL_UNLOCKED;
457
458 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
459 /* Init the I2C Callback settings */
460 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
461 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
462 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
463 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
464 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
465 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
466 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
467 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
468 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
469 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
470
471 if (hi2c->MspInitCallback == NULL)
472 {
473 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
474 }
475
476 /* Init the low level hardware : GPIO, CLOCK, NVIC */
477 hi2c->MspInitCallback(hi2c);
478 #else
479 /* Init the low level hardware : GPIO, CLOCK, NVIC */
480 HAL_I2C_MspInit(hi2c);
481 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
482 }
483
484 hi2c->State = HAL_I2C_STATE_BUSY;
485
486 /* Disable the selected I2C peripheral */
487 __HAL_I2C_DISABLE(hi2c);
488
489 /* Get PCLK1 frequency */
490 pclk1 = HAL_RCC_GetPCLK1Freq();
491
492 /* Check the minimum allowed PCLK1 frequency */
493 if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
494 {
495 return HAL_ERROR;
496 }
497
498 /* Calculate frequency range */
499 freqrange = I2C_FREQRANGE(pclk1);
500
501 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
502 /* Configure I2Cx: Frequency range */
503 MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
504
505 /*---------------------------- I2Cx TRISE Configuration --------------------*/
506 /* Configure I2Cx: Rise Time */
507 MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
508
509 /*---------------------------- I2Cx CCR Configuration ----------------------*/
510 /* Configure I2Cx: Speed */
511 MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
512
513 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
514 /* Configure I2Cx: Generalcall and NoStretch mode */
515 MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
516
517 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
518 /* Configure I2Cx: Own Address1 and addressing mode */
519 MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
520
521 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
522 /* Configure I2Cx: Dual mode and Own Address2 */
523 MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
524
525 /* Enable the selected I2C peripheral */
526 __HAL_I2C_ENABLE(hi2c);
527
528 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
529 hi2c->State = HAL_I2C_STATE_READY;
530 hi2c->PreviousState = I2C_STATE_NONE;
531 hi2c->Mode = HAL_I2C_MODE_NONE;
532
533 return HAL_OK;
534 }
535
536 /**
537 * @brief DeInitialize the I2C peripheral.
538 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
539 * the configuration information for the specified I2C.
540 * @retval HAL status
541 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)542 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
543 {
544 /* Check the I2C handle allocation */
545 if (hi2c == NULL)
546 {
547 return HAL_ERROR;
548 }
549
550 /* Check the parameters */
551 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
552
553 hi2c->State = HAL_I2C_STATE_BUSY;
554
555 /* Disable the I2C Peripheral Clock */
556 __HAL_I2C_DISABLE(hi2c);
557
558 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
559 if (hi2c->MspDeInitCallback == NULL)
560 {
561 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
562 }
563
564 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
565 hi2c->MspDeInitCallback(hi2c);
566 #else
567 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
568 HAL_I2C_MspDeInit(hi2c);
569 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
570
571 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
572 hi2c->State = HAL_I2C_STATE_RESET;
573 hi2c->PreviousState = I2C_STATE_NONE;
574 hi2c->Mode = HAL_I2C_MODE_NONE;
575
576 /* Release Lock */
577 __HAL_UNLOCK(hi2c);
578
579 return HAL_OK;
580 }
581
582 /**
583 * @brief Initialize the I2C MSP.
584 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
585 * the configuration information for the specified I2C.
586 * @retval None
587 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)588 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
589 {
590 /* Prevent unused argument(s) compilation warning */
591 UNUSED(hi2c);
592
593 /* NOTE : This function should not be modified, when the callback is needed,
594 the HAL_I2C_MspInit could be implemented in the user file
595 */
596 }
597
598 /**
599 * @brief DeInitialize the I2C MSP.
600 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
601 * the configuration information for the specified I2C.
602 * @retval None
603 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)604 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
605 {
606 /* Prevent unused argument(s) compilation warning */
607 UNUSED(hi2c);
608
609 /* NOTE : This function should not be modified, when the callback is needed,
610 the HAL_I2C_MspDeInit could be implemented in the user file
611 */
612 }
613
614 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
615 /**
616 * @brief Register a User I2C Callback
617 * To be used instead of the weak predefined callback
618 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
619 * the configuration information for the specified I2C.
620 * @param CallbackID ID of the callback to be registered
621 * This parameter can be one of the following values:
622 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
623 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
624 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
625 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
626 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
627 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
628 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
629 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
630 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
631 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
632 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
633 * @param pCallback pointer to the Callback function
634 * @retval HAL status
635 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)636 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
637 {
638 HAL_StatusTypeDef status = HAL_OK;
639
640 if (pCallback == NULL)
641 {
642 /* Update the error code */
643 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
644
645 return HAL_ERROR;
646 }
647 /* Process locked */
648 __HAL_LOCK(hi2c);
649
650 if (HAL_I2C_STATE_READY == hi2c->State)
651 {
652 switch (CallbackID)
653 {
654 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
655 hi2c->MasterTxCpltCallback = pCallback;
656 break;
657
658 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
659 hi2c->MasterRxCpltCallback = pCallback;
660 break;
661
662 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
663 hi2c->SlaveTxCpltCallback = pCallback;
664 break;
665
666 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
667 hi2c->SlaveRxCpltCallback = pCallback;
668 break;
669
670 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
671 hi2c->ListenCpltCallback = pCallback;
672 break;
673
674 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
675 hi2c->MemTxCpltCallback = pCallback;
676 break;
677
678 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
679 hi2c->MemRxCpltCallback = pCallback;
680 break;
681
682 case HAL_I2C_ERROR_CB_ID :
683 hi2c->ErrorCallback = pCallback;
684 break;
685
686 case HAL_I2C_ABORT_CB_ID :
687 hi2c->AbortCpltCallback = pCallback;
688 break;
689
690 case HAL_I2C_MSPINIT_CB_ID :
691 hi2c->MspInitCallback = pCallback;
692 break;
693
694 case HAL_I2C_MSPDEINIT_CB_ID :
695 hi2c->MspDeInitCallback = pCallback;
696 break;
697
698 default :
699 /* Update the error code */
700 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
701
702 /* Return error status */
703 status = HAL_ERROR;
704 break;
705 }
706 }
707 else if (HAL_I2C_STATE_RESET == hi2c->State)
708 {
709 switch (CallbackID)
710 {
711 case HAL_I2C_MSPINIT_CB_ID :
712 hi2c->MspInitCallback = pCallback;
713 break;
714
715 case HAL_I2C_MSPDEINIT_CB_ID :
716 hi2c->MspDeInitCallback = pCallback;
717 break;
718
719 default :
720 /* Update the error code */
721 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
722
723 /* Return error status */
724 status = HAL_ERROR;
725 break;
726 }
727 }
728 else
729 {
730 /* Update the error code */
731 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
732
733 /* Return error status */
734 status = HAL_ERROR;
735 }
736
737 /* Release Lock */
738 __HAL_UNLOCK(hi2c);
739 return status;
740 }
741
742 /**
743 * @brief Unregister an I2C Callback
744 * I2C callback is redirected to the weak predefined callback
745 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
746 * the configuration information for the specified I2C.
747 * @param CallbackID ID of the callback to be unregistered
748 * This parameter can be one of the following values:
749 * This parameter can be one of the following values:
750 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
751 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
752 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
753 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
754 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
755 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
756 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
757 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
758 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
759 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
760 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
761 * @retval HAL status
762 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)763 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
764 {
765 HAL_StatusTypeDef status = HAL_OK;
766
767 /* Process locked */
768 __HAL_LOCK(hi2c);
769
770 if (HAL_I2C_STATE_READY == hi2c->State)
771 {
772 switch (CallbackID)
773 {
774 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
775 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
776 break;
777
778 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
779 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
780 break;
781
782 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
783 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
784 break;
785
786 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
787 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
788 break;
789
790 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
791 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
792 break;
793
794 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
795 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
796 break;
797
798 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
799 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
800 break;
801
802 case HAL_I2C_ERROR_CB_ID :
803 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
804 break;
805
806 case HAL_I2C_ABORT_CB_ID :
807 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
808 break;
809
810 case HAL_I2C_MSPINIT_CB_ID :
811 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
812 break;
813
814 case HAL_I2C_MSPDEINIT_CB_ID :
815 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
816 break;
817
818 default :
819 /* Update the error code */
820 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
821
822 /* Return error status */
823 status = HAL_ERROR;
824 break;
825 }
826 }
827 else if (HAL_I2C_STATE_RESET == hi2c->State)
828 {
829 switch (CallbackID)
830 {
831 case HAL_I2C_MSPINIT_CB_ID :
832 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
833 break;
834
835 case HAL_I2C_MSPDEINIT_CB_ID :
836 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
837 break;
838
839 default :
840 /* Update the error code */
841 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
842
843 /* Return error status */
844 status = HAL_ERROR;
845 break;
846 }
847 }
848 else
849 {
850 /* Update the error code */
851 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
852
853 /* Return error status */
854 status = HAL_ERROR;
855 }
856
857 /* Release Lock */
858 __HAL_UNLOCK(hi2c);
859 return status;
860 }
861
862 /**
863 * @brief Register the Slave Address Match I2C Callback
864 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
865 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
866 * the configuration information for the specified I2C.
867 * @param pCallback pointer to the Address Match Callback function
868 * @retval HAL status
869 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)870 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
871 {
872 HAL_StatusTypeDef status = HAL_OK;
873
874 if (pCallback == NULL)
875 {
876 /* Update the error code */
877 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
878
879 return HAL_ERROR;
880 }
881 /* Process locked */
882 __HAL_LOCK(hi2c);
883
884 if (HAL_I2C_STATE_READY == hi2c->State)
885 {
886 hi2c->AddrCallback = pCallback;
887 }
888 else
889 {
890 /* Update the error code */
891 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
892
893 /* Return error status */
894 status = HAL_ERROR;
895 }
896
897 /* Release Lock */
898 __HAL_UNLOCK(hi2c);
899 return status;
900 }
901
902 /**
903 * @brief UnRegister the Slave Address Match I2C Callback
904 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
905 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
906 * the configuration information for the specified I2C.
907 * @retval HAL status
908 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)909 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
910 {
911 HAL_StatusTypeDef status = HAL_OK;
912
913 /* Process locked */
914 __HAL_LOCK(hi2c);
915
916 if (HAL_I2C_STATE_READY == hi2c->State)
917 {
918 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
919 }
920 else
921 {
922 /* Update the error code */
923 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
924
925 /* Return error status */
926 status = HAL_ERROR;
927 }
928
929 /* Release Lock */
930 __HAL_UNLOCK(hi2c);
931 return status;
932 }
933
934 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
935
936 /**
937 * @}
938 */
939
940 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
941 * @brief Data transfers functions
942 *
943 @verbatim
944 ===============================================================================
945 ##### IO operation functions #####
946 ===============================================================================
947 [..]
948 This subsection provides a set of functions allowing to manage the I2C data
949 transfers.
950
951 (#) There are two modes of transfer:
952 (++) Blocking mode : The communication is performed in the polling mode.
953 The status of all data processing is returned by the same function
954 after finishing transfer.
955 (++) No-Blocking mode : The communication is performed using Interrupts
956 or DMA. These functions return the status of the transfer startup.
957 The end of the data processing will be indicated through the
958 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
959 using DMA mode.
960
961 (#) Blocking mode functions are :
962 (++) HAL_I2C_Master_Transmit()
963 (++) HAL_I2C_Master_Receive()
964 (++) HAL_I2C_Slave_Transmit()
965 (++) HAL_I2C_Slave_Receive()
966 (++) HAL_I2C_Mem_Write()
967 (++) HAL_I2C_Mem_Read()
968 (++) HAL_I2C_IsDeviceReady()
969
970 (#) No-Blocking mode functions with Interrupt are :
971 (++) HAL_I2C_Master_Transmit_IT()
972 (++) HAL_I2C_Master_Receive_IT()
973 (++) HAL_I2C_Slave_Transmit_IT()
974 (++) HAL_I2C_Slave_Receive_IT()
975 (++) HAL_I2C_Mem_Write_IT()
976 (++) HAL_I2C_Mem_Read_IT()
977 (++) HAL_I2C_Master_Seq_Transmit_IT()
978 (++) HAL_I2C_Master_Seq_Receive_IT()
979 (++) HAL_I2C_Slave_Seq_Transmit_IT()
980 (++) HAL_I2C_Slave_Seq_Receive_IT()
981 (++) HAL_I2C_EnableListen_IT()
982 (++) HAL_I2C_DisableListen_IT()
983 (++) HAL_I2C_Master_Abort_IT()
984
985 (#) No-Blocking mode functions with DMA are :
986 (++) HAL_I2C_Master_Transmit_DMA()
987 (++) HAL_I2C_Master_Receive_DMA()
988 (++) HAL_I2C_Slave_Transmit_DMA()
989 (++) HAL_I2C_Slave_Receive_DMA()
990 (++) HAL_I2C_Mem_Write_DMA()
991 (++) HAL_I2C_Mem_Read_DMA()
992 (++) HAL_I2C_Master_Seq_Transmit_DMA()
993 (++) HAL_I2C_Master_Seq_Receive_DMA()
994 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
995 (++) HAL_I2C_Slave_Seq_Receive_DMA()
996
997 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
998 (++) HAL_I2C_MasterTxCpltCallback()
999 (++) HAL_I2C_MasterRxCpltCallback()
1000 (++) HAL_I2C_SlaveTxCpltCallback()
1001 (++) HAL_I2C_SlaveRxCpltCallback()
1002 (++) HAL_I2C_MemTxCpltCallback()
1003 (++) HAL_I2C_MemRxCpltCallback()
1004 (++) HAL_I2C_AddrCallback()
1005 (++) HAL_I2C_ListenCpltCallback()
1006 (++) HAL_I2C_ErrorCallback()
1007 (++) HAL_I2C_AbortCpltCallback()
1008
1009 @endverbatim
1010 * @{
1011 */
1012
1013 /**
1014 * @brief Transmits in master mode an amount of data in blocking mode.
1015 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1016 * the configuration information for the specified I2C.
1017 * @param DevAddress Target device address: The device 7 bits address value
1018 * in datasheet must be shifted to the left before calling the interface
1019 * @param pData Pointer to data buffer
1020 * @param Size Amount of data to be sent
1021 * @param Timeout Timeout duration
1022 * @retval HAL status
1023 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1024 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1025 {
1026 /* Init tickstart for timeout management*/
1027 uint32_t tickstart = HAL_GetTick();
1028
1029 if (hi2c->State == HAL_I2C_STATE_READY)
1030 {
1031 /* Wait until BUSY flag is reset */
1032 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1033 {
1034 return HAL_BUSY;
1035 }
1036
1037 /* Process Locked */
1038 __HAL_LOCK(hi2c);
1039
1040 /* Check if the I2C is already enabled */
1041 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1042 {
1043 /* Enable I2C peripheral */
1044 __HAL_I2C_ENABLE(hi2c);
1045 }
1046
1047 /* Disable Pos */
1048 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1049
1050 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1051 hi2c->Mode = HAL_I2C_MODE_MASTER;
1052 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1053
1054 /* Prepare transfer parameters */
1055 hi2c->pBuffPtr = pData;
1056 hi2c->XferCount = Size;
1057 hi2c->XferSize = hi2c->XferCount;
1058 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1059
1060 /* Send Slave Address */
1061 if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1062 {
1063 return HAL_ERROR;
1064 }
1065
1066 /* Clear ADDR flag */
1067 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1068
1069 while (hi2c->XferSize > 0U)
1070 {
1071 /* Wait until TXE flag is set */
1072 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1073 {
1074 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1075 {
1076 /* Generate Stop */
1077 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1078 }
1079 return HAL_ERROR;
1080 }
1081
1082 /* Write data to DR */
1083 hi2c->Instance->DR = *hi2c->pBuffPtr;
1084
1085 /* Increment Buffer pointer */
1086 hi2c->pBuffPtr++;
1087
1088 /* Update counter */
1089 hi2c->XferCount--;
1090 hi2c->XferSize--;
1091
1092 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1093 {
1094 /* Write data to DR */
1095 hi2c->Instance->DR = *hi2c->pBuffPtr;
1096
1097 /* Increment Buffer pointer */
1098 hi2c->pBuffPtr++;
1099
1100 /* Update counter */
1101 hi2c->XferCount--;
1102 hi2c->XferSize--;
1103 }
1104
1105 /* Wait until BTF flag is set */
1106 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1107 {
1108 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1109 {
1110 /* Generate Stop */
1111 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1112 }
1113 return HAL_ERROR;
1114 }
1115 }
1116
1117 /* Generate Stop */
1118 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1119
1120 hi2c->State = HAL_I2C_STATE_READY;
1121 hi2c->Mode = HAL_I2C_MODE_NONE;
1122
1123 /* Process Unlocked */
1124 __HAL_UNLOCK(hi2c);
1125
1126 return HAL_OK;
1127 }
1128 else
1129 {
1130 return HAL_BUSY;
1131 }
1132 }
1133
1134 /**
1135 * @brief Receives in master mode an amount of data in blocking mode.
1136 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1137 * the configuration information for the specified I2C.
1138 * @param DevAddress Target device address: The device 7 bits address value
1139 * in datasheet must be shifted to the left before calling the interface
1140 * @param pData Pointer to data buffer
1141 * @param Size Amount of data to be sent
1142 * @param Timeout Timeout duration
1143 * @retval HAL status
1144 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1145 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1146 {
1147 /* Init tickstart for timeout management*/
1148 uint32_t tickstart = HAL_GetTick();
1149
1150 if (hi2c->State == HAL_I2C_STATE_READY)
1151 {
1152 /* Wait until BUSY flag is reset */
1153 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1154 {
1155 return HAL_BUSY;
1156 }
1157
1158 /* Process Locked */
1159 __HAL_LOCK(hi2c);
1160
1161 /* Check if the I2C is already enabled */
1162 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1163 {
1164 /* Enable I2C peripheral */
1165 __HAL_I2C_ENABLE(hi2c);
1166 }
1167
1168 /* Disable Pos */
1169 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1170
1171 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1172 hi2c->Mode = HAL_I2C_MODE_MASTER;
1173 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1174
1175 /* Prepare transfer parameters */
1176 hi2c->pBuffPtr = pData;
1177 hi2c->XferCount = Size;
1178 hi2c->XferSize = hi2c->XferCount;
1179 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1180
1181 /* Send Slave Address */
1182 if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1183 {
1184 return HAL_ERROR;
1185 }
1186
1187 if (hi2c->XferSize == 0U)
1188 {
1189 /* Clear ADDR flag */
1190 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1191
1192 /* Generate Stop */
1193 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1194 }
1195 else if (hi2c->XferSize == 1U)
1196 {
1197 /* Disable Acknowledge */
1198 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1199
1200 /* Clear ADDR flag */
1201 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1202
1203 /* Generate Stop */
1204 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1205 }
1206 else if (hi2c->XferSize == 2U)
1207 {
1208 /* Disable Acknowledge */
1209 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1210
1211 /* Enable Pos */
1212 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1213
1214 /* Clear ADDR flag */
1215 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1216 }
1217 else
1218 {
1219 /* Enable Acknowledge */
1220 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1221
1222 /* Clear ADDR flag */
1223 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1224 }
1225
1226 while (hi2c->XferSize > 0U)
1227 {
1228 if (hi2c->XferSize <= 3U)
1229 {
1230 /* One byte */
1231 if (hi2c->XferSize == 1U)
1232 {
1233 /* Wait until RXNE flag is set */
1234 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1235 {
1236 return HAL_ERROR;
1237 }
1238
1239 /* Read data from DR */
1240 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1241
1242 /* Increment Buffer pointer */
1243 hi2c->pBuffPtr++;
1244
1245 /* Update counter */
1246 hi2c->XferSize--;
1247 hi2c->XferCount--;
1248 }
1249 /* Two bytes */
1250 else if (hi2c->XferSize == 2U)
1251 {
1252 /* Wait until BTF flag is set */
1253 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1254 {
1255 return HAL_ERROR;
1256 }
1257
1258 /* Generate Stop */
1259 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1260
1261 /* Read data from DR */
1262 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1263
1264 /* Increment Buffer pointer */
1265 hi2c->pBuffPtr++;
1266
1267 /* Update counter */
1268 hi2c->XferSize--;
1269 hi2c->XferCount--;
1270
1271 /* Read data from DR */
1272 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1273
1274 /* Increment Buffer pointer */
1275 hi2c->pBuffPtr++;
1276
1277 /* Update counter */
1278 hi2c->XferSize--;
1279 hi2c->XferCount--;
1280 }
1281 /* 3 Last bytes */
1282 else
1283 {
1284 /* Wait until BTF flag is set */
1285 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1286 {
1287 return HAL_ERROR;
1288 }
1289
1290 /* Disable Acknowledge */
1291 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1292
1293 /* Read data from DR */
1294 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1295
1296 /* Increment Buffer pointer */
1297 hi2c->pBuffPtr++;
1298
1299 /* Update counter */
1300 hi2c->XferSize--;
1301 hi2c->XferCount--;
1302
1303 /* Wait until BTF flag is set */
1304 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1305 {
1306 return HAL_ERROR;
1307 }
1308
1309 /* Generate Stop */
1310 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1311
1312 /* Read data from DR */
1313 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1314
1315 /* Increment Buffer pointer */
1316 hi2c->pBuffPtr++;
1317
1318 /* Update counter */
1319 hi2c->XferSize--;
1320 hi2c->XferCount--;
1321
1322 /* Read data from DR */
1323 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1324
1325 /* Increment Buffer pointer */
1326 hi2c->pBuffPtr++;
1327
1328 /* Update counter */
1329 hi2c->XferSize--;
1330 hi2c->XferCount--;
1331 }
1332 }
1333 else
1334 {
1335 /* Wait until RXNE flag is set */
1336 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1337 {
1338 return HAL_ERROR;
1339 }
1340
1341 /* Read data from DR */
1342 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1343
1344 /* Increment Buffer pointer */
1345 hi2c->pBuffPtr++;
1346
1347 /* Update counter */
1348 hi2c->XferSize--;
1349 hi2c->XferCount--;
1350
1351 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
1352 {
1353 /* Read data from DR */
1354 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1355
1356 /* Increment Buffer pointer */
1357 hi2c->pBuffPtr++;
1358
1359 /* Update counter */
1360 hi2c->XferSize--;
1361 hi2c->XferCount--;
1362 }
1363 }
1364 }
1365
1366 hi2c->State = HAL_I2C_STATE_READY;
1367 hi2c->Mode = HAL_I2C_MODE_NONE;
1368
1369 /* Process Unlocked */
1370 __HAL_UNLOCK(hi2c);
1371
1372 return HAL_OK;
1373 }
1374 else
1375 {
1376 return HAL_BUSY;
1377 }
1378 }
1379
1380 /**
1381 * @brief Transmits in slave mode an amount of data in blocking mode.
1382 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1383 * the configuration information for the specified I2C.
1384 * @param pData Pointer to data buffer
1385 * @param Size Amount of data to be sent
1386 * @param Timeout Timeout duration
1387 * @retval HAL status
1388 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1389 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1390 {
1391 /* Init tickstart for timeout management*/
1392 uint32_t tickstart = HAL_GetTick();
1393
1394 if (hi2c->State == HAL_I2C_STATE_READY)
1395 {
1396 if ((pData == NULL) || (Size == 0U))
1397 {
1398 return HAL_ERROR;
1399 }
1400
1401 /* Process Locked */
1402 __HAL_LOCK(hi2c);
1403
1404 /* Check if the I2C is already enabled */
1405 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1406 {
1407 /* Enable I2C peripheral */
1408 __HAL_I2C_ENABLE(hi2c);
1409 }
1410
1411 /* Disable Pos */
1412 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1413
1414 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1415 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1416 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1417
1418 /* Prepare transfer parameters */
1419 hi2c->pBuffPtr = pData;
1420 hi2c->XferCount = Size;
1421 hi2c->XferSize = hi2c->XferCount;
1422 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1423
1424 /* Enable Address Acknowledge */
1425 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1426
1427 /* Wait until ADDR flag is set */
1428 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1429 {
1430 return HAL_ERROR;
1431 }
1432
1433 /* Clear ADDR flag */
1434 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1435
1436 /* If 10bit addressing mode is selected */
1437 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1438 {
1439 /* Wait until ADDR flag is set */
1440 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1441 {
1442 return HAL_ERROR;
1443 }
1444
1445 /* Clear ADDR flag */
1446 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1447 }
1448
1449 while (hi2c->XferSize > 0U)
1450 {
1451 /* Wait until TXE flag is set */
1452 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1453 {
1454 /* Disable Address Acknowledge */
1455 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1456
1457 return HAL_ERROR;
1458 }
1459
1460 /* Write data to DR */
1461 hi2c->Instance->DR = *hi2c->pBuffPtr;
1462
1463 /* Increment Buffer pointer */
1464 hi2c->pBuffPtr++;
1465
1466 /* Update counter */
1467 hi2c->XferCount--;
1468 hi2c->XferSize--;
1469
1470 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1471 {
1472 /* Write data to DR */
1473 hi2c->Instance->DR = *hi2c->pBuffPtr;
1474
1475 /* Increment Buffer pointer */
1476 hi2c->pBuffPtr++;
1477
1478 /* Update counter */
1479 hi2c->XferCount--;
1480 hi2c->XferSize--;
1481 }
1482 }
1483
1484 /* Wait until AF flag is set */
1485 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1486 {
1487 return HAL_ERROR;
1488 }
1489
1490 /* Clear AF flag */
1491 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1492
1493 /* Disable Address Acknowledge */
1494 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1495
1496 hi2c->State = HAL_I2C_STATE_READY;
1497 hi2c->Mode = HAL_I2C_MODE_NONE;
1498
1499 /* Process Unlocked */
1500 __HAL_UNLOCK(hi2c);
1501
1502 return HAL_OK;
1503 }
1504 else
1505 {
1506 return HAL_BUSY;
1507 }
1508 }
1509
1510 /**
1511 * @brief Receive in slave mode an amount of data in blocking mode
1512 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1513 * the configuration information for the specified I2C.
1514 * @param pData Pointer to data buffer
1515 * @param Size Amount of data to be sent
1516 * @param Timeout Timeout duration
1517 * @retval HAL status
1518 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1519 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1520 {
1521 /* Init tickstart for timeout management*/
1522 uint32_t tickstart = HAL_GetTick();
1523
1524 if (hi2c->State == HAL_I2C_STATE_READY)
1525 {
1526 if ((pData == NULL) || (Size == (uint16_t)0))
1527 {
1528 return HAL_ERROR;
1529 }
1530
1531 /* Process Locked */
1532 __HAL_LOCK(hi2c);
1533
1534 /* Check if the I2C is already enabled */
1535 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1536 {
1537 /* Enable I2C peripheral */
1538 __HAL_I2C_ENABLE(hi2c);
1539 }
1540
1541 /* Disable Pos */
1542 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1543
1544 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1545 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1546 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1547
1548 /* Prepare transfer parameters */
1549 hi2c->pBuffPtr = pData;
1550 hi2c->XferCount = Size;
1551 hi2c->XferSize = hi2c->XferCount;
1552 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1553
1554 /* Enable Address Acknowledge */
1555 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1556
1557 /* Wait until ADDR flag is set */
1558 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1559 {
1560 return HAL_ERROR;
1561 }
1562
1563 /* Clear ADDR flag */
1564 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1565
1566 while (hi2c->XferSize > 0U)
1567 {
1568 /* Wait until RXNE flag is set */
1569 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1570 {
1571 /* Disable Address Acknowledge */
1572 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1573
1574 return HAL_ERROR;
1575 }
1576
1577 /* Read data from DR */
1578 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1579
1580 /* Increment Buffer pointer */
1581 hi2c->pBuffPtr++;
1582
1583 /* Update counter */
1584 hi2c->XferSize--;
1585 hi2c->XferCount--;
1586
1587 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1588 {
1589 /* Read data from DR */
1590 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1591
1592 /* Increment Buffer pointer */
1593 hi2c->pBuffPtr++;
1594
1595 /* Update counter */
1596 hi2c->XferSize--;
1597 hi2c->XferCount--;
1598 }
1599 }
1600
1601 /* Wait until STOP flag is set */
1602 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1603 {
1604 /* Disable Address Acknowledge */
1605 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1606
1607 return HAL_ERROR;
1608 }
1609
1610 /* Clear STOP flag */
1611 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
1612
1613 /* Disable Address Acknowledge */
1614 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1615
1616 hi2c->State = HAL_I2C_STATE_READY;
1617 hi2c->Mode = HAL_I2C_MODE_NONE;
1618
1619 /* Process Unlocked */
1620 __HAL_UNLOCK(hi2c);
1621
1622 return HAL_OK;
1623 }
1624 else
1625 {
1626 return HAL_BUSY;
1627 }
1628 }
1629
1630 /**
1631 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1632 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1633 * the configuration information for the specified I2C.
1634 * @param DevAddress Target device address: The device 7 bits address value
1635 * in datasheet must be shifted to the left before calling the interface
1636 * @param pData Pointer to data buffer
1637 * @param Size Amount of data to be sent
1638 * @retval HAL status
1639 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1640 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1641 {
1642 __IO uint32_t count = 0U;
1643
1644 if (hi2c->State == HAL_I2C_STATE_READY)
1645 {
1646 /* Wait until BUSY flag is reset */
1647 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1648 do
1649 {
1650 count--;
1651 if (count == 0U)
1652 {
1653 hi2c->PreviousState = I2C_STATE_NONE;
1654 hi2c->State = HAL_I2C_STATE_READY;
1655 hi2c->Mode = HAL_I2C_MODE_NONE;
1656 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1657
1658 /* Process Unlocked */
1659 __HAL_UNLOCK(hi2c);
1660
1661 return HAL_ERROR;
1662 }
1663 }
1664 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1665
1666 /* Process Locked */
1667 __HAL_LOCK(hi2c);
1668
1669 /* Check if the I2C is already enabled */
1670 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1671 {
1672 /* Enable I2C peripheral */
1673 __HAL_I2C_ENABLE(hi2c);
1674 }
1675
1676 /* Disable Pos */
1677 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1678
1679 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1680 hi2c->Mode = HAL_I2C_MODE_MASTER;
1681 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1682
1683 /* Prepare transfer parameters */
1684 hi2c->pBuffPtr = pData;
1685 hi2c->XferCount = Size;
1686 hi2c->XferSize = hi2c->XferCount;
1687 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1688 hi2c->Devaddress = DevAddress;
1689
1690 /* Generate Start */
1691 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1692
1693 /* Process Unlocked */
1694 __HAL_UNLOCK(hi2c);
1695
1696 /* Note : The I2C interrupts must be enabled after unlocking current process
1697 to avoid the risk of I2C interrupt handle execution before current
1698 process unlock */
1699 /* Enable EVT, BUF and ERR interrupt */
1700 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1701
1702 return HAL_OK;
1703 }
1704 else
1705 {
1706 return HAL_BUSY;
1707 }
1708 }
1709
1710 /**
1711 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1712 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1713 * the configuration information for the specified I2C.
1714 * @param DevAddress Target device address: The device 7 bits address value
1715 * in datasheet must be shifted to the left before calling the interface
1716 * @param pData Pointer to data buffer
1717 * @param Size Amount of data to be sent
1718 * @retval HAL status
1719 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1720 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1721 {
1722 __IO uint32_t count = 0U;
1723
1724 if (hi2c->State == HAL_I2C_STATE_READY)
1725 {
1726 /* Wait until BUSY flag is reset */
1727 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1728 do
1729 {
1730 count--;
1731 if (count == 0U)
1732 {
1733 hi2c->PreviousState = I2C_STATE_NONE;
1734 hi2c->State = HAL_I2C_STATE_READY;
1735 hi2c->Mode = HAL_I2C_MODE_NONE;
1736 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1737
1738 /* Process Unlocked */
1739 __HAL_UNLOCK(hi2c);
1740
1741 return HAL_ERROR;
1742 }
1743 }
1744 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1745
1746 /* Process Locked */
1747 __HAL_LOCK(hi2c);
1748
1749 /* Check if the I2C is already enabled */
1750 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1751 {
1752 /* Enable I2C peripheral */
1753 __HAL_I2C_ENABLE(hi2c);
1754 }
1755
1756 /* Disable Pos */
1757 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1758
1759 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1760 hi2c->Mode = HAL_I2C_MODE_MASTER;
1761 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1762
1763 /* Prepare transfer parameters */
1764 hi2c->pBuffPtr = pData;
1765 hi2c->XferCount = Size;
1766 hi2c->XferSize = hi2c->XferCount;
1767 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1768 hi2c->Devaddress = DevAddress;
1769
1770 /* Enable Acknowledge */
1771 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1772
1773 /* Generate Start */
1774 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1775
1776 /* Process Unlocked */
1777 __HAL_UNLOCK(hi2c);
1778
1779 /* Note : The I2C interrupts must be enabled after unlocking current process
1780 to avoid the risk of I2C interrupt handle execution before current
1781 process unlock */
1782
1783 /* Enable EVT, BUF and ERR interrupt */
1784 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1785
1786 return HAL_OK;
1787 }
1788 else
1789 {
1790 return HAL_BUSY;
1791 }
1792 }
1793
1794 /**
1795 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1796 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1797 * the configuration information for the specified I2C.
1798 * @param pData Pointer to data buffer
1799 * @param Size Amount of data to be sent
1800 * @retval HAL status
1801 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1802 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1803 {
1804
1805 if (hi2c->State == HAL_I2C_STATE_READY)
1806 {
1807 if ((pData == NULL) || (Size == 0U))
1808 {
1809 return HAL_ERROR;
1810 }
1811
1812 /* Process Locked */
1813 __HAL_LOCK(hi2c);
1814
1815 /* Check if the I2C is already enabled */
1816 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1817 {
1818 /* Enable I2C peripheral */
1819 __HAL_I2C_ENABLE(hi2c);
1820 }
1821
1822 /* Disable Pos */
1823 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1824
1825 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1826 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1827 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1828
1829 /* Prepare transfer parameters */
1830 hi2c->pBuffPtr = pData;
1831 hi2c->XferCount = Size;
1832 hi2c->XferSize = hi2c->XferCount;
1833 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1834
1835 /* Enable Address Acknowledge */
1836 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1837
1838 /* Process Unlocked */
1839 __HAL_UNLOCK(hi2c);
1840
1841 /* Note : The I2C interrupts must be enabled after unlocking current process
1842 to avoid the risk of I2C interrupt handle execution before current
1843 process unlock */
1844
1845 /* Enable EVT, BUF and ERR interrupt */
1846 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1847
1848 return HAL_OK;
1849 }
1850 else
1851 {
1852 return HAL_BUSY;
1853 }
1854 }
1855
1856 /**
1857 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1858 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1859 * the configuration information for the specified I2C.
1860 * @param pData Pointer to data buffer
1861 * @param Size Amount of data to be sent
1862 * @retval HAL status
1863 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1864 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1865 {
1866
1867 if (hi2c->State == HAL_I2C_STATE_READY)
1868 {
1869 if ((pData == NULL) || (Size == 0U))
1870 {
1871 return HAL_ERROR;
1872 }
1873
1874 /* Process Locked */
1875 __HAL_LOCK(hi2c);
1876
1877 /* Check if the I2C is already enabled */
1878 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1879 {
1880 /* Enable I2C peripheral */
1881 __HAL_I2C_ENABLE(hi2c);
1882 }
1883
1884 /* Disable Pos */
1885 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1886
1887 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1888 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1889 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1890
1891 /* Prepare transfer parameters */
1892 hi2c->pBuffPtr = pData;
1893 hi2c->XferCount = Size;
1894 hi2c->XferSize = hi2c->XferCount;
1895 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1896
1897 /* Enable Address Acknowledge */
1898 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1899
1900 /* Process Unlocked */
1901 __HAL_UNLOCK(hi2c);
1902
1903 /* Note : The I2C interrupts must be enabled after unlocking current process
1904 to avoid the risk of I2C interrupt handle execution before current
1905 process unlock */
1906
1907 /* Enable EVT, BUF and ERR interrupt */
1908 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1909
1910 return HAL_OK;
1911 }
1912 else
1913 {
1914 return HAL_BUSY;
1915 }
1916 }
1917
1918 /**
1919 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1920 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1921 * the configuration information for the specified I2C.
1922 * @param DevAddress Target device address: The device 7 bits address value
1923 * in datasheet must be shifted to the left before calling the interface
1924 * @param pData Pointer to data buffer
1925 * @param Size Amount of data to be sent
1926 * @retval HAL status
1927 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1928 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1929 {
1930 __IO uint32_t count = 0U;
1931 HAL_StatusTypeDef dmaxferstatus;
1932
1933 if (hi2c->State == HAL_I2C_STATE_READY)
1934 {
1935 /* Wait until BUSY flag is reset */
1936 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1937 do
1938 {
1939 count--;
1940 if (count == 0U)
1941 {
1942 hi2c->PreviousState = I2C_STATE_NONE;
1943 hi2c->State = HAL_I2C_STATE_READY;
1944 hi2c->Mode = HAL_I2C_MODE_NONE;
1945 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1946
1947 /* Process Unlocked */
1948 __HAL_UNLOCK(hi2c);
1949
1950 return HAL_ERROR;
1951 }
1952 }
1953 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1954
1955 /* Process Locked */
1956 __HAL_LOCK(hi2c);
1957
1958 /* Check if the I2C is already enabled */
1959 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1960 {
1961 /* Enable I2C peripheral */
1962 __HAL_I2C_ENABLE(hi2c);
1963 }
1964
1965 /* Disable Pos */
1966 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1967
1968 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1969 hi2c->Mode = HAL_I2C_MODE_MASTER;
1970 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1971
1972 /* Prepare transfer parameters */
1973 hi2c->pBuffPtr = pData;
1974 hi2c->XferCount = Size;
1975 hi2c->XferSize = hi2c->XferCount;
1976 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1977 hi2c->Devaddress = DevAddress;
1978
1979 if (hi2c->XferSize > 0U)
1980 {
1981 /* Set the I2C DMA transfer complete callback */
1982 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
1983
1984 /* Set the DMA error callback */
1985 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1986
1987 /* Set the unused DMA callbacks to NULL */
1988 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1989 hi2c->hdmatx->XferM1CpltCallback = NULL;
1990 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
1991 hi2c->hdmatx->XferAbortCallback = NULL;
1992
1993 /* Enable the DMA stream */
1994 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
1995
1996 if (dmaxferstatus == HAL_OK)
1997 {
1998 /* Enable Acknowledge */
1999 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2000
2001 /* Generate Start */
2002 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2003
2004 /* Process Unlocked */
2005 __HAL_UNLOCK(hi2c);
2006
2007 /* Note : The I2C interrupts must be enabled after unlocking current process
2008 to avoid the risk of I2C interrupt handle execution before current
2009 process unlock */
2010
2011 /* Enable EVT and ERR interrupt */
2012 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2013
2014 /* Enable DMA Request */
2015 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2016 }
2017 else
2018 {
2019 /* Update I2C state */
2020 hi2c->State = HAL_I2C_STATE_READY;
2021 hi2c->Mode = HAL_I2C_MODE_NONE;
2022
2023 /* Update I2C error code */
2024 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2025
2026 /* Process Unlocked */
2027 __HAL_UNLOCK(hi2c);
2028
2029 return HAL_ERROR;
2030 }
2031 }
2032 else
2033 {
2034 /* Enable Acknowledge */
2035 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2036
2037 /* Generate Start */
2038 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2039
2040 /* Process Unlocked */
2041 __HAL_UNLOCK(hi2c);
2042
2043 /* Note : The I2C interrupts must be enabled after unlocking current process
2044 to avoid the risk of I2C interrupt handle execution before current
2045 process unlock */
2046
2047 /* Enable EVT, BUF and ERR interrupt */
2048 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2049 }
2050
2051 return HAL_OK;
2052 }
2053 else
2054 {
2055 return HAL_BUSY;
2056 }
2057 }
2058
2059 /**
2060 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2061 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2062 * the configuration information for the specified I2C.
2063 * @param DevAddress Target device address: The device 7 bits address value
2064 * in datasheet must be shifted to the left before calling the interface
2065 * @param pData Pointer to data buffer
2066 * @param Size Amount of data to be sent
2067 * @retval HAL status
2068 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2069 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
2070 {
2071 __IO uint32_t count = 0U;
2072 HAL_StatusTypeDef dmaxferstatus;
2073
2074 if (hi2c->State == HAL_I2C_STATE_READY)
2075 {
2076 /* Wait until BUSY flag is reset */
2077 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2078 do
2079 {
2080 count--;
2081 if (count == 0U)
2082 {
2083 hi2c->PreviousState = I2C_STATE_NONE;
2084 hi2c->State = HAL_I2C_STATE_READY;
2085 hi2c->Mode = HAL_I2C_MODE_NONE;
2086 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2087
2088 /* Process Unlocked */
2089 __HAL_UNLOCK(hi2c);
2090
2091 return HAL_ERROR;
2092 }
2093 }
2094 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2095
2096 /* Process Locked */
2097 __HAL_LOCK(hi2c);
2098
2099 /* Check if the I2C is already enabled */
2100 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2101 {
2102 /* Enable I2C peripheral */
2103 __HAL_I2C_ENABLE(hi2c);
2104 }
2105
2106 /* Disable Pos */
2107 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2108
2109 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2110 hi2c->Mode = HAL_I2C_MODE_MASTER;
2111 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2112
2113 /* Prepare transfer parameters */
2114 hi2c->pBuffPtr = pData;
2115 hi2c->XferCount = Size;
2116 hi2c->XferSize = hi2c->XferCount;
2117 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2118 hi2c->Devaddress = DevAddress;
2119
2120 if (hi2c->XferSize > 0U)
2121 {
2122 /* Set the I2C DMA transfer complete callback */
2123 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2124
2125 /* Set the DMA error callback */
2126 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2127
2128 /* Set the unused DMA callbacks to NULL */
2129 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2130 hi2c->hdmarx->XferM1CpltCallback = NULL;
2131 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
2132 hi2c->hdmarx->XferAbortCallback = NULL;
2133
2134 /* Enable the DMA stream */
2135 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2136
2137 if (dmaxferstatus == HAL_OK)
2138 {
2139 /* Enable Acknowledge */
2140 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2141
2142 /* Generate Start */
2143 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2144
2145 /* Process Unlocked */
2146 __HAL_UNLOCK(hi2c);
2147
2148 /* Note : The I2C interrupts must be enabled after unlocking current process
2149 to avoid the risk of I2C interrupt handle execution before current
2150 process unlock */
2151
2152 /* Enable EVT and ERR interrupt */
2153 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2154
2155 /* Enable DMA Request */
2156 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2157 }
2158 else
2159 {
2160 /* Update I2C state */
2161 hi2c->State = HAL_I2C_STATE_READY;
2162 hi2c->Mode = HAL_I2C_MODE_NONE;
2163
2164 /* Update I2C error code */
2165 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2166
2167 /* Process Unlocked */
2168 __HAL_UNLOCK(hi2c);
2169
2170 return HAL_ERROR;
2171 }
2172 }
2173 else
2174 {
2175 /* Enable Acknowledge */
2176 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2177
2178 /* Generate Start */
2179 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2180
2181 /* Process Unlocked */
2182 __HAL_UNLOCK(hi2c);
2183
2184 /* Note : The I2C interrupts must be enabled after unlocking current process
2185 to avoid the risk of I2C interrupt handle execution before current
2186 process unlock */
2187
2188 /* Enable EVT, BUF and ERR interrupt */
2189 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2190 }
2191
2192 return HAL_OK;
2193 }
2194 else
2195 {
2196 return HAL_BUSY;
2197 }
2198 }
2199
2200 /**
2201 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2202 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2203 * the configuration information for the specified I2C.
2204 * @param pData Pointer to data buffer
2205 * @param Size Amount of data to be sent
2206 * @retval HAL status
2207 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2208 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2209 {
2210 HAL_StatusTypeDef dmaxferstatus;
2211
2212 if (hi2c->State == HAL_I2C_STATE_READY)
2213 {
2214 if ((pData == NULL) || (Size == 0U))
2215 {
2216 return HAL_ERROR;
2217 }
2218
2219 /* Process Locked */
2220 __HAL_LOCK(hi2c);
2221
2222 /* Check if the I2C is already enabled */
2223 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2224 {
2225 /* Enable I2C peripheral */
2226 __HAL_I2C_ENABLE(hi2c);
2227 }
2228
2229 /* Disable Pos */
2230 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2231
2232 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2233 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2234 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2235
2236 /* Prepare transfer parameters */
2237 hi2c->pBuffPtr = pData;
2238 hi2c->XferCount = Size;
2239 hi2c->XferSize = hi2c->XferCount;
2240 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2241
2242 /* Set the I2C DMA transfer complete callback */
2243 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
2244
2245 /* Set the DMA error callback */
2246 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2247
2248 /* Set the unused DMA callbacks to NULL */
2249 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2250 hi2c->hdmatx->XferM1CpltCallback = NULL;
2251 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
2252 hi2c->hdmatx->XferAbortCallback = NULL;
2253
2254 /* Enable the DMA stream */
2255 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2256
2257 if (dmaxferstatus == HAL_OK)
2258 {
2259 /* Enable Address Acknowledge */
2260 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2261
2262 /* Process Unlocked */
2263 __HAL_UNLOCK(hi2c);
2264
2265 /* Note : The I2C interrupts must be enabled after unlocking current process
2266 to avoid the risk of I2C interrupt handle execution before current
2267 process unlock */
2268 /* Enable EVT and ERR interrupt */
2269 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2270
2271 /* Enable DMA Request */
2272 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
2273
2274 return HAL_OK;
2275 }
2276 else
2277 {
2278 /* Update I2C state */
2279 hi2c->State = HAL_I2C_STATE_READY;
2280 hi2c->Mode = HAL_I2C_MODE_NONE;
2281
2282 /* Update I2C error code */
2283 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2284
2285 /* Process Unlocked */
2286 __HAL_UNLOCK(hi2c);
2287
2288 return HAL_ERROR;
2289 }
2290 }
2291 else
2292 {
2293 return HAL_BUSY;
2294 }
2295 }
2296
2297 /**
2298 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2299 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2300 * the configuration information for the specified I2C.
2301 * @param pData Pointer to data buffer
2302 * @param Size Amount of data to be sent
2303 * @retval HAL status
2304 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2305 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2306 {
2307 HAL_StatusTypeDef dmaxferstatus;
2308
2309 if (hi2c->State == HAL_I2C_STATE_READY)
2310 {
2311 if ((pData == NULL) || (Size == 0U))
2312 {
2313 return HAL_ERROR;
2314 }
2315
2316 /* Process Locked */
2317 __HAL_LOCK(hi2c);
2318
2319 /* Check if the I2C is already enabled */
2320 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2321 {
2322 /* Enable I2C peripheral */
2323 __HAL_I2C_ENABLE(hi2c);
2324 }
2325
2326 /* Disable Pos */
2327 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2328
2329 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2330 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2331 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2332
2333 /* Prepare transfer parameters */
2334 hi2c->pBuffPtr = pData;
2335 hi2c->XferCount = Size;
2336 hi2c->XferSize = hi2c->XferCount;
2337 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2338
2339 /* Set the I2C DMA transfer complete callback */
2340 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2341
2342 /* Set the DMA error callback */
2343 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2344
2345 /* Set the unused DMA callbacks to NULL */
2346 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2347 hi2c->hdmarx->XferM1CpltCallback = NULL;
2348 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
2349 hi2c->hdmarx->XferAbortCallback = NULL;
2350
2351 /* Enable the DMA stream */
2352 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2353
2354 if (dmaxferstatus == HAL_OK)
2355 {
2356 /* Enable Address Acknowledge */
2357 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2358
2359 /* Process Unlocked */
2360 __HAL_UNLOCK(hi2c);
2361
2362 /* Note : The I2C interrupts must be enabled after unlocking current process
2363 to avoid the risk of I2C interrupt handle execution before current
2364 process unlock */
2365 /* Enable EVT and ERR interrupt */
2366 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2367
2368 /* Enable DMA Request */
2369 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2370
2371 return HAL_OK;
2372 }
2373 else
2374 {
2375 /* Update I2C state */
2376 hi2c->State = HAL_I2C_STATE_READY;
2377 hi2c->Mode = HAL_I2C_MODE_NONE;
2378
2379 /* Update I2C error code */
2380 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2381
2382 /* Process Unlocked */
2383 __HAL_UNLOCK(hi2c);
2384
2385 return HAL_ERROR;
2386 }
2387 }
2388 else
2389 {
2390 return HAL_BUSY;
2391 }
2392 }
2393
2394 /**
2395 * @brief Write an amount of data in blocking mode to a specific memory address
2396 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2397 * the configuration information for the specified I2C.
2398 * @param DevAddress Target device address: The device 7 bits address value
2399 * in datasheet must be shifted to the left before calling the interface
2400 * @param MemAddress Internal memory address
2401 * @param MemAddSize Size of internal memory address
2402 * @param pData Pointer to data buffer
2403 * @param Size Amount of data to be sent
2404 * @param Timeout Timeout duration
2405 * @retval HAL status
2406 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2407 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2408 {
2409 /* Init tickstart for timeout management*/
2410 uint32_t tickstart = HAL_GetTick();
2411
2412 /* Check the parameters */
2413 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2414
2415 if (hi2c->State == HAL_I2C_STATE_READY)
2416 {
2417 /* Wait until BUSY flag is reset */
2418 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2419 {
2420 return HAL_BUSY;
2421 }
2422
2423 /* Process Locked */
2424 __HAL_LOCK(hi2c);
2425
2426 /* Check if the I2C is already enabled */
2427 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2428 {
2429 /* Enable I2C peripheral */
2430 __HAL_I2C_ENABLE(hi2c);
2431 }
2432
2433 /* Disable Pos */
2434 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2435
2436 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2437 hi2c->Mode = HAL_I2C_MODE_MEM;
2438 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2439
2440 /* Prepare transfer parameters */
2441 hi2c->pBuffPtr = pData;
2442 hi2c->XferCount = Size;
2443 hi2c->XferSize = hi2c->XferCount;
2444 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2445
2446 /* Send Slave Address and Memory Address */
2447 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2448 {
2449 return HAL_ERROR;
2450 }
2451
2452 while (hi2c->XferSize > 0U)
2453 {
2454 /* Wait until TXE flag is set */
2455 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2456 {
2457 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2458 {
2459 /* Generate Stop */
2460 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2461 }
2462 return HAL_ERROR;
2463 }
2464
2465 /* Write data to DR */
2466 hi2c->Instance->DR = *hi2c->pBuffPtr;
2467
2468 /* Increment Buffer pointer */
2469 hi2c->pBuffPtr++;
2470
2471 /* Update counter */
2472 hi2c->XferSize--;
2473 hi2c->XferCount--;
2474
2475 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
2476 {
2477 /* Write data to DR */
2478 hi2c->Instance->DR = *hi2c->pBuffPtr;
2479
2480 /* Increment Buffer pointer */
2481 hi2c->pBuffPtr++;
2482
2483 /* Update counter */
2484 hi2c->XferSize--;
2485 hi2c->XferCount--;
2486 }
2487 }
2488
2489 /* Wait until BTF flag is set */
2490 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2491 {
2492 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2493 {
2494 /* Generate Stop */
2495 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2496 }
2497 return HAL_ERROR;
2498 }
2499
2500 /* Generate Stop */
2501 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2502
2503 hi2c->State = HAL_I2C_STATE_READY;
2504 hi2c->Mode = HAL_I2C_MODE_NONE;
2505
2506 /* Process Unlocked */
2507 __HAL_UNLOCK(hi2c);
2508
2509 return HAL_OK;
2510 }
2511 else
2512 {
2513 return HAL_BUSY;
2514 }
2515 }
2516
2517 /**
2518 * @brief Read an amount of data in blocking mode from a specific memory address
2519 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2520 * the configuration information for the specified I2C.
2521 * @param DevAddress Target device address: The device 7 bits address value
2522 * in datasheet must be shifted to the left before calling the interface
2523 * @param MemAddress Internal memory address
2524 * @param MemAddSize Size of internal memory address
2525 * @param pData Pointer to data buffer
2526 * @param Size Amount of data to be sent
2527 * @param Timeout Timeout duration
2528 * @retval HAL status
2529 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2530 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2531 {
2532 /* Init tickstart for timeout management*/
2533 uint32_t tickstart = HAL_GetTick();
2534
2535 /* Check the parameters */
2536 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2537
2538 if (hi2c->State == HAL_I2C_STATE_READY)
2539 {
2540 /* Wait until BUSY flag is reset */
2541 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2542 {
2543 return HAL_BUSY;
2544 }
2545
2546 /* Process Locked */
2547 __HAL_LOCK(hi2c);
2548
2549 /* Check if the I2C is already enabled */
2550 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2551 {
2552 /* Enable I2C peripheral */
2553 __HAL_I2C_ENABLE(hi2c);
2554 }
2555
2556 /* Disable Pos */
2557 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2558
2559 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2560 hi2c->Mode = HAL_I2C_MODE_MEM;
2561 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2562
2563 /* Prepare transfer parameters */
2564 hi2c->pBuffPtr = pData;
2565 hi2c->XferCount = Size;
2566 hi2c->XferSize = hi2c->XferCount;
2567 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2568
2569 /* Send Slave Address and Memory Address */
2570 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2571 {
2572 return HAL_ERROR;
2573 }
2574
2575 if (hi2c->XferSize == 0U)
2576 {
2577 /* Clear ADDR flag */
2578 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2579
2580 /* Generate Stop */
2581 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2582 }
2583 else if (hi2c->XferSize == 1U)
2584 {
2585 /* Disable Acknowledge */
2586 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2587
2588 /* Clear ADDR flag */
2589 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2590
2591 /* Generate Stop */
2592 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2593 }
2594 else if (hi2c->XferSize == 2U)
2595 {
2596 /* Disable Acknowledge */
2597 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2598
2599 /* Enable Pos */
2600 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2601
2602 /* Clear ADDR flag */
2603 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2604 }
2605 else
2606 {
2607 /* Clear ADDR flag */
2608 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2609 }
2610
2611 while (hi2c->XferSize > 0U)
2612 {
2613 if (hi2c->XferSize <= 3U)
2614 {
2615 /* One byte */
2616 if (hi2c->XferSize == 1U)
2617 {
2618 /* Wait until RXNE flag is set */
2619 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2620 {
2621 return HAL_ERROR;
2622 }
2623
2624 /* Read data from DR */
2625 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2626
2627 /* Increment Buffer pointer */
2628 hi2c->pBuffPtr++;
2629
2630 /* Update counter */
2631 hi2c->XferSize--;
2632 hi2c->XferCount--;
2633 }
2634 /* Two bytes */
2635 else if (hi2c->XferSize == 2U)
2636 {
2637 /* Wait until BTF flag is set */
2638 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2639 {
2640 return HAL_ERROR;
2641 }
2642
2643 /* Generate Stop */
2644 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2645
2646 /* Read data from DR */
2647 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2648
2649 /* Increment Buffer pointer */
2650 hi2c->pBuffPtr++;
2651
2652 /* Update counter */
2653 hi2c->XferSize--;
2654 hi2c->XferCount--;
2655
2656 /* Read data from DR */
2657 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2658
2659 /* Increment Buffer pointer */
2660 hi2c->pBuffPtr++;
2661
2662 /* Update counter */
2663 hi2c->XferSize--;
2664 hi2c->XferCount--;
2665 }
2666 /* 3 Last bytes */
2667 else
2668 {
2669 /* Wait until BTF flag is set */
2670 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2671 {
2672 return HAL_ERROR;
2673 }
2674
2675 /* Disable Acknowledge */
2676 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2677
2678 /* Read data from DR */
2679 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2680
2681 /* Increment Buffer pointer */
2682 hi2c->pBuffPtr++;
2683
2684 /* Update counter */
2685 hi2c->XferSize--;
2686 hi2c->XferCount--;
2687
2688 /* Wait until BTF flag is set */
2689 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2690 {
2691 return HAL_ERROR;
2692 }
2693
2694 /* Generate Stop */
2695 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2696
2697 /* Read data from DR */
2698 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2699
2700 /* Increment Buffer pointer */
2701 hi2c->pBuffPtr++;
2702
2703 /* Update counter */
2704 hi2c->XferSize--;
2705 hi2c->XferCount--;
2706
2707 /* Read data from DR */
2708 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2709
2710 /* Increment Buffer pointer */
2711 hi2c->pBuffPtr++;
2712
2713 /* Update counter */
2714 hi2c->XferSize--;
2715 hi2c->XferCount--;
2716 }
2717 }
2718 else
2719 {
2720 /* Wait until RXNE flag is set */
2721 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2722 {
2723 return HAL_ERROR;
2724 }
2725
2726 /* Read data from DR */
2727 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2728
2729 /* Increment Buffer pointer */
2730 hi2c->pBuffPtr++;
2731
2732 /* Update counter */
2733 hi2c->XferSize--;
2734 hi2c->XferCount--;
2735
2736 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
2737 {
2738 /* Read data from DR */
2739 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2740
2741 /* Increment Buffer pointer */
2742 hi2c->pBuffPtr++;
2743
2744 /* Update counter */
2745 hi2c->XferSize--;
2746 hi2c->XferCount--;
2747 }
2748 }
2749 }
2750
2751 hi2c->State = HAL_I2C_STATE_READY;
2752 hi2c->Mode = HAL_I2C_MODE_NONE;
2753
2754 /* Process Unlocked */
2755 __HAL_UNLOCK(hi2c);
2756
2757 return HAL_OK;
2758 }
2759 else
2760 {
2761 return HAL_BUSY;
2762 }
2763 }
2764
2765 /**
2766 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2767 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2768 * the configuration information for the specified I2C.
2769 * @param DevAddress Target device address: The device 7 bits address value
2770 * in datasheet must be shifted to the left before calling the interface
2771 * @param MemAddress Internal memory address
2772 * @param MemAddSize Size of internal memory address
2773 * @param pData Pointer to data buffer
2774 * @param Size Amount of data to be sent
2775 * @retval HAL status
2776 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2777 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2778 {
2779 __IO uint32_t count = 0U;
2780
2781 /* Check the parameters */
2782 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2783
2784 if (hi2c->State == HAL_I2C_STATE_READY)
2785 {
2786 /* Wait until BUSY flag is reset */
2787 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2788 do
2789 {
2790 count--;
2791 if (count == 0U)
2792 {
2793 hi2c->PreviousState = I2C_STATE_NONE;
2794 hi2c->State = HAL_I2C_STATE_READY;
2795 hi2c->Mode = HAL_I2C_MODE_NONE;
2796 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2797
2798 /* Process Unlocked */
2799 __HAL_UNLOCK(hi2c);
2800
2801 return HAL_ERROR;
2802 }
2803 }
2804 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2805
2806 /* Process Locked */
2807 __HAL_LOCK(hi2c);
2808
2809 /* Check if the I2C is already enabled */
2810 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2811 {
2812 /* Enable I2C peripheral */
2813 __HAL_I2C_ENABLE(hi2c);
2814 }
2815
2816 /* Disable Pos */
2817 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2818
2819 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2820 hi2c->Mode = HAL_I2C_MODE_MEM;
2821 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2822
2823 /* Prepare transfer parameters */
2824 hi2c->pBuffPtr = pData;
2825 hi2c->XferCount = Size;
2826 hi2c->XferSize = hi2c->XferCount;
2827 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2828 hi2c->Devaddress = DevAddress;
2829 hi2c->Memaddress = MemAddress;
2830 hi2c->MemaddSize = MemAddSize;
2831 hi2c->EventCount = 0U;
2832
2833 /* Generate Start */
2834 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2835
2836 /* Process Unlocked */
2837 __HAL_UNLOCK(hi2c);
2838
2839 /* Note : The I2C interrupts must be enabled after unlocking current process
2840 to avoid the risk of I2C interrupt handle execution before current
2841 process unlock */
2842
2843 /* Enable EVT, BUF and ERR interrupt */
2844 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2845
2846 return HAL_OK;
2847 }
2848 else
2849 {
2850 return HAL_BUSY;
2851 }
2852 }
2853
2854 /**
2855 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2856 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2857 * the configuration information for the specified I2C.
2858 * @param DevAddress Target device address
2859 * @param MemAddress Internal memory address
2860 * @param MemAddSize Size of internal memory address
2861 * @param pData Pointer to data buffer
2862 * @param Size Amount of data to be sent
2863 * @retval HAL status
2864 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2865 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2866 {
2867 __IO uint32_t count = 0U;
2868
2869 /* Check the parameters */
2870 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2871
2872 if (hi2c->State == HAL_I2C_STATE_READY)
2873 {
2874 /* Wait until BUSY flag is reset */
2875 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2876 do
2877 {
2878 count--;
2879 if (count == 0U)
2880 {
2881 hi2c->PreviousState = I2C_STATE_NONE;
2882 hi2c->State = HAL_I2C_STATE_READY;
2883 hi2c->Mode = HAL_I2C_MODE_NONE;
2884 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2885
2886 /* Process Unlocked */
2887 __HAL_UNLOCK(hi2c);
2888
2889 return HAL_ERROR;
2890 }
2891 }
2892 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2893
2894 /* Process Locked */
2895 __HAL_LOCK(hi2c);
2896
2897 /* Check if the I2C is already enabled */
2898 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2899 {
2900 /* Enable I2C peripheral */
2901 __HAL_I2C_ENABLE(hi2c);
2902 }
2903
2904 /* Disable Pos */
2905 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2906
2907 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2908 hi2c->Mode = HAL_I2C_MODE_MEM;
2909 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2910
2911 /* Prepare transfer parameters */
2912 hi2c->pBuffPtr = pData;
2913 hi2c->XferCount = Size;
2914 hi2c->XferSize = hi2c->XferCount;
2915 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2916 hi2c->Devaddress = DevAddress;
2917 hi2c->Memaddress = MemAddress;
2918 hi2c->MemaddSize = MemAddSize;
2919 hi2c->EventCount = 0U;
2920
2921 /* Enable Acknowledge */
2922 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2923
2924 /* Generate Start */
2925 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2926
2927 /* Process Unlocked */
2928 __HAL_UNLOCK(hi2c);
2929
2930 if (hi2c->XferSize > 0U)
2931 {
2932 /* Note : The I2C interrupts must be enabled after unlocking current process
2933 to avoid the risk of I2C interrupt handle execution before current
2934 process unlock */
2935
2936 /* Enable EVT, BUF and ERR interrupt */
2937 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2938 }
2939 return HAL_OK;
2940 }
2941 else
2942 {
2943 return HAL_BUSY;
2944 }
2945 }
2946
2947 /**
2948 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
2949 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2950 * the configuration information for the specified I2C.
2951 * @param DevAddress Target device address: The device 7 bits address value
2952 * in datasheet must be shifted to the left before calling the interface
2953 * @param MemAddress Internal memory address
2954 * @param MemAddSize Size of internal memory address
2955 * @param pData Pointer to data buffer
2956 * @param Size Amount of data to be sent
2957 * @retval HAL status
2958 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2959 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2960 {
2961 __IO uint32_t count = 0U;
2962 HAL_StatusTypeDef dmaxferstatus;
2963
2964 /* Init tickstart for timeout management*/
2965 uint32_t tickstart = HAL_GetTick();
2966
2967 /* Check the parameters */
2968 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2969
2970 if (hi2c->State == HAL_I2C_STATE_READY)
2971 {
2972 /* Wait until BUSY flag is reset */
2973 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2974 do
2975 {
2976 count--;
2977 if (count == 0U)
2978 {
2979 hi2c->PreviousState = I2C_STATE_NONE;
2980 hi2c->State = HAL_I2C_STATE_READY;
2981 hi2c->Mode = HAL_I2C_MODE_NONE;
2982 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2983
2984 /* Process Unlocked */
2985 __HAL_UNLOCK(hi2c);
2986
2987 return HAL_ERROR;
2988 }
2989 }
2990 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2991
2992 /* Process Locked */
2993 __HAL_LOCK(hi2c);
2994
2995 /* Check if the I2C is already enabled */
2996 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2997 {
2998 /* Enable I2C peripheral */
2999 __HAL_I2C_ENABLE(hi2c);
3000 }
3001
3002 /* Disable Pos */
3003 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3004
3005 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3006 hi2c->Mode = HAL_I2C_MODE_MEM;
3007 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3008
3009 /* Prepare transfer parameters */
3010 hi2c->pBuffPtr = pData;
3011 hi2c->XferCount = Size;
3012 hi2c->XferSize = hi2c->XferCount;
3013 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3014
3015 if (hi2c->XferSize > 0U)
3016 {
3017 /* Set the I2C DMA transfer complete callback */
3018 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3019
3020 /* Set the DMA error callback */
3021 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3022
3023 /* Set the unused DMA callbacks to NULL */
3024 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3025 hi2c->hdmatx->XferM1CpltCallback = NULL;
3026 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
3027 hi2c->hdmatx->XferAbortCallback = NULL;
3028
3029 /* Enable the DMA stream */
3030 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3031
3032 if (dmaxferstatus == HAL_OK)
3033 {
3034 /* Send Slave Address and Memory Address */
3035 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3036 {
3037 return HAL_ERROR;
3038 }
3039
3040 /* Clear ADDR flag */
3041 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3042
3043 /* Process Unlocked */
3044 __HAL_UNLOCK(hi2c);
3045
3046 /* Note : The I2C interrupts must be enabled after unlocking current process
3047 to avoid the risk of I2C interrupt handle execution before current
3048 process unlock */
3049 /* Enable ERR interrupt */
3050 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3051
3052 /* Enable DMA Request */
3053 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3054
3055 return HAL_OK;
3056 }
3057 else
3058 {
3059 /* Update I2C state */
3060 hi2c->State = HAL_I2C_STATE_READY;
3061 hi2c->Mode = HAL_I2C_MODE_NONE;
3062
3063 /* Update I2C error code */
3064 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3065
3066 /* Process Unlocked */
3067 __HAL_UNLOCK(hi2c);
3068
3069 return HAL_ERROR;
3070 }
3071 }
3072 else
3073 {
3074 /* Update I2C state */
3075 hi2c->State = HAL_I2C_STATE_READY;
3076 hi2c->Mode = HAL_I2C_MODE_NONE;
3077
3078 /* Update I2C error code */
3079 hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
3080
3081 /* Process Unlocked */
3082 __HAL_UNLOCK(hi2c);
3083
3084 return HAL_ERROR;
3085 }
3086 }
3087 else
3088 {
3089 return HAL_BUSY;
3090 }
3091 }
3092
3093 /**
3094 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3095 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3096 * the configuration information for the specified I2C.
3097 * @param DevAddress Target device address: The device 7 bits address value
3098 * in datasheet must be shifted to the left before calling the interface
3099 * @param MemAddress Internal memory address
3100 * @param MemAddSize Size of internal memory address
3101 * @param pData Pointer to data buffer
3102 * @param Size Amount of data to be read
3103 * @retval HAL status
3104 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3105 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3106 {
3107 /* Init tickstart for timeout management*/
3108 uint32_t tickstart = HAL_GetTick();
3109 __IO uint32_t count = 0U;
3110 HAL_StatusTypeDef dmaxferstatus;
3111
3112 /* Check the parameters */
3113 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3114
3115 if (hi2c->State == HAL_I2C_STATE_READY)
3116 {
3117 /* Wait until BUSY flag is reset */
3118 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3119 do
3120 {
3121 count--;
3122 if (count == 0U)
3123 {
3124 hi2c->PreviousState = I2C_STATE_NONE;
3125 hi2c->State = HAL_I2C_STATE_READY;
3126 hi2c->Mode = HAL_I2C_MODE_NONE;
3127 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3128
3129 /* Process Unlocked */
3130 __HAL_UNLOCK(hi2c);
3131
3132 return HAL_ERROR;
3133 }
3134 }
3135 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3136
3137 /* Process Locked */
3138 __HAL_LOCK(hi2c);
3139
3140 /* Check if the I2C is already enabled */
3141 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3142 {
3143 /* Enable I2C peripheral */
3144 __HAL_I2C_ENABLE(hi2c);
3145 }
3146
3147 /* Disable Pos */
3148 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3149
3150 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3151 hi2c->Mode = HAL_I2C_MODE_MEM;
3152 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3153
3154 /* Prepare transfer parameters */
3155 hi2c->pBuffPtr = pData;
3156 hi2c->XferCount = Size;
3157 hi2c->XferSize = hi2c->XferCount;
3158 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3159
3160 if (hi2c->XferSize > 0U)
3161 {
3162 /* Set the I2C DMA transfer complete callback */
3163 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
3164
3165 /* Set the DMA error callback */
3166 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3167
3168 /* Set the unused DMA callbacks to NULL */
3169 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3170 hi2c->hdmarx->XferM1CpltCallback = NULL;
3171 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
3172 hi2c->hdmarx->XferAbortCallback = NULL;
3173
3174 /* Enable the DMA stream */
3175 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
3176
3177 if (dmaxferstatus == HAL_OK)
3178 {
3179 /* Send Slave Address and Memory Address */
3180 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3181 {
3182 return HAL_ERROR;
3183 }
3184
3185 if (hi2c->XferSize == 1U)
3186 {
3187 /* Disable Acknowledge */
3188 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3189 }
3190 else
3191 {
3192 /* Enable Last DMA bit */
3193 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3194 }
3195
3196 /* Clear ADDR flag */
3197 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3198
3199 /* Process Unlocked */
3200 __HAL_UNLOCK(hi2c);
3201
3202 /* Note : The I2C interrupts must be enabled after unlocking current process
3203 to avoid the risk of I2C interrupt handle execution before current
3204 process unlock */
3205 /* Enable ERR interrupt */
3206 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3207
3208 /* Enable DMA Request */
3209 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
3210 }
3211 else
3212 {
3213 /* Update I2C state */
3214 hi2c->State = HAL_I2C_STATE_READY;
3215 hi2c->Mode = HAL_I2C_MODE_NONE;
3216
3217 /* Update I2C error code */
3218 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3219
3220 /* Process Unlocked */
3221 __HAL_UNLOCK(hi2c);
3222
3223 return HAL_ERROR;
3224 }
3225 }
3226 else
3227 {
3228 /* Send Slave Address and Memory Address */
3229 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3230 {
3231 return HAL_ERROR;
3232 }
3233
3234 /* Clear ADDR flag */
3235 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3236
3237 /* Generate Stop */
3238 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3239
3240 hi2c->State = HAL_I2C_STATE_READY;
3241
3242 /* Process Unlocked */
3243 __HAL_UNLOCK(hi2c);
3244 }
3245
3246 return HAL_OK;
3247 }
3248 else
3249 {
3250 return HAL_BUSY;
3251 }
3252 }
3253
3254 /**
3255 * @brief Checks if target device is ready for communication.
3256 * @note This function is used with Memory devices
3257 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3258 * the configuration information for the specified I2C.
3259 * @param DevAddress Target device address: The device 7 bits address value
3260 * in datasheet must be shifted to the left before calling the interface
3261 * @param Trials Number of trials
3262 * @param Timeout Timeout duration
3263 * @retval HAL status
3264 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3265 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
3266 {
3267 /* Get tick */
3268 uint32_t tickstart = HAL_GetTick();
3269 uint32_t I2C_Trials = 1U;
3270 FlagStatus tmp1;
3271 FlagStatus tmp2;
3272
3273 if (hi2c->State == HAL_I2C_STATE_READY)
3274 {
3275 /* Wait until BUSY flag is reset */
3276 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3277 {
3278 return HAL_BUSY;
3279 }
3280
3281 /* Process Locked */
3282 __HAL_LOCK(hi2c);
3283
3284 /* Check if the I2C is already enabled */
3285 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3286 {
3287 /* Enable I2C peripheral */
3288 __HAL_I2C_ENABLE(hi2c);
3289 }
3290
3291 /* Disable Pos */
3292 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3293
3294 hi2c->State = HAL_I2C_STATE_BUSY;
3295 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3296 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3297
3298 do
3299 {
3300 /* Generate Start */
3301 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3302
3303 /* Wait until SB flag is set */
3304 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
3305 {
3306 return HAL_ERROR;
3307 }
3308
3309 /* Send slave address */
3310 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
3311
3312 /* Wait until ADDR or AF flag are set */
3313 /* Get tick */
3314 tickstart = HAL_GetTick();
3315
3316 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3317 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3318 while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET))
3319 {
3320 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3321 {
3322 hi2c->State = HAL_I2C_STATE_TIMEOUT;
3323 }
3324 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3325 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3326 }
3327
3328 hi2c->State = HAL_I2C_STATE_READY;
3329
3330 /* Check if the ADDR flag has been set */
3331 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
3332 {
3333 /* Generate Stop */
3334 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3335
3336 /* Clear ADDR Flag */
3337 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3338
3339 /* Wait until BUSY flag is reset */
3340 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3341 {
3342 return HAL_ERROR;
3343 }
3344
3345 hi2c->State = HAL_I2C_STATE_READY;
3346
3347 /* Process Unlocked */
3348 __HAL_UNLOCK(hi2c);
3349
3350 return HAL_OK;
3351 }
3352 else
3353 {
3354 /* Generate Stop */
3355 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3356
3357 /* Clear AF Flag */
3358 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3359
3360 /* Wait until BUSY flag is reset */
3361 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3362 {
3363 return HAL_ERROR;
3364 }
3365 }
3366
3367 /* Increment Trials */
3368 I2C_Trials++;
3369 }
3370 while (I2C_Trials < Trials);
3371
3372 hi2c->State = HAL_I2C_STATE_READY;
3373
3374 /* Process Unlocked */
3375 __HAL_UNLOCK(hi2c);
3376
3377 return HAL_ERROR;
3378 }
3379 else
3380 {
3381 return HAL_BUSY;
3382 }
3383 }
3384
3385 /**
3386 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3387 * @note This interface allow to manage repeated start condition when a direction change during transfer
3388 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3389 * the configuration information for the specified I2C.
3390 * @param DevAddress Target device address: The device 7 bits address value
3391 * in datasheet must be shifted to the left before calling the interface
3392 * @param pData Pointer to data buffer
3393 * @param Size Amount of data to be sent
3394 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3395 * @retval HAL status
3396 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3397 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3398 {
3399 __IO uint32_t Prev_State = 0x00U;
3400 __IO uint32_t count = 0x00U;
3401
3402 /* Check the parameters */
3403 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3404
3405 if (hi2c->State == HAL_I2C_STATE_READY)
3406 {
3407 /* Check Busy Flag only if FIRST call of Master interface */
3408 if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3409 {
3410 /* Wait until BUSY flag is reset */
3411 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3412 do
3413 {
3414 count--;
3415 if (count == 0U)
3416 {
3417 hi2c->PreviousState = I2C_STATE_NONE;
3418 hi2c->State = HAL_I2C_STATE_READY;
3419 hi2c->Mode = HAL_I2C_MODE_NONE;
3420 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3421
3422 /* Process Unlocked */
3423 __HAL_UNLOCK(hi2c);
3424
3425 return HAL_ERROR;
3426 }
3427 }
3428 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3429 }
3430
3431 /* Process Locked */
3432 __HAL_LOCK(hi2c);
3433
3434 /* Check if the I2C is already enabled */
3435 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3436 {
3437 /* Enable I2C peripheral */
3438 __HAL_I2C_ENABLE(hi2c);
3439 }
3440
3441 /* Disable Pos */
3442 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3443
3444 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3445 hi2c->Mode = HAL_I2C_MODE_MASTER;
3446 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3447
3448 /* Prepare transfer parameters */
3449 hi2c->pBuffPtr = pData;
3450 hi2c->XferCount = Size;
3451 hi2c->XferSize = hi2c->XferCount;
3452 hi2c->XferOptions = XferOptions;
3453 hi2c->Devaddress = DevAddress;
3454
3455 Prev_State = hi2c->PreviousState;
3456
3457 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3458 /* Mean Previous state is same as current state */
3459 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3460 {
3461 /* Generate Start */
3462 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3463 }
3464
3465 /* Process Unlocked */
3466 __HAL_UNLOCK(hi2c);
3467
3468 /* Note : The I2C interrupts must be enabled after unlocking current process
3469 to avoid the risk of I2C interrupt handle execution before current
3470 process unlock */
3471
3472 /* Enable EVT, BUF and ERR interrupt */
3473 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3474
3475 return HAL_OK;
3476 }
3477 else
3478 {
3479 return HAL_BUSY;
3480 }
3481 }
3482
3483 /**
3484 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3485 * @note This interface allow to manage repeated start condition when a direction change during transfer
3486 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3487 * the configuration information for the specified I2C.
3488 * @param DevAddress Target device address: The device 7 bits address value
3489 * in datasheet must be shifted to the left before calling the interface
3490 * @param pData Pointer to data buffer
3491 * @param Size Amount of data to be sent
3492 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3493 * @retval HAL status
3494 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3495 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3496 {
3497 __IO uint32_t Prev_State = 0x00U;
3498 __IO uint32_t count = 0x00U;
3499 HAL_StatusTypeDef dmaxferstatus;
3500
3501 /* Check the parameters */
3502 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3503
3504 if (hi2c->State == HAL_I2C_STATE_READY)
3505 {
3506 /* Check Busy Flag only if FIRST call of Master interface */
3507 if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3508 {
3509 /* Wait until BUSY flag is reset */
3510 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3511 do
3512 {
3513 count--;
3514 if (count == 0U)
3515 {
3516 hi2c->PreviousState = I2C_STATE_NONE;
3517 hi2c->State = HAL_I2C_STATE_READY;
3518 hi2c->Mode = HAL_I2C_MODE_NONE;
3519 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3520
3521 /* Process Unlocked */
3522 __HAL_UNLOCK(hi2c);
3523
3524 return HAL_ERROR;
3525 }
3526 }
3527 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3528 }
3529
3530 /* Process Locked */
3531 __HAL_LOCK(hi2c);
3532
3533 /* Check if the I2C is already enabled */
3534 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3535 {
3536 /* Enable I2C peripheral */
3537 __HAL_I2C_ENABLE(hi2c);
3538 }
3539
3540 /* Disable Pos */
3541 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3542
3543 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3544 hi2c->Mode = HAL_I2C_MODE_MASTER;
3545 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3546
3547 /* Prepare transfer parameters */
3548 hi2c->pBuffPtr = pData;
3549 hi2c->XferCount = Size;
3550 hi2c->XferSize = hi2c->XferCount;
3551 hi2c->XferOptions = XferOptions;
3552 hi2c->Devaddress = DevAddress;
3553
3554 Prev_State = hi2c->PreviousState;
3555
3556 if (hi2c->XferSize > 0U)
3557 {
3558 /* Set the I2C DMA transfer complete callback */
3559 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3560
3561 /* Set the DMA error callback */
3562 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3563
3564 /* Set the unused DMA callbacks to NULL */
3565 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3566 hi2c->hdmatx->XferAbortCallback = NULL;
3567
3568 /* Enable the DMA stream */
3569 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3570
3571 if (dmaxferstatus == HAL_OK)
3572 {
3573 /* Enable Acknowledge */
3574 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3575
3576 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3577 /* Mean Previous state is same as current state */
3578 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3579 {
3580 /* Generate Start */
3581 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3582 }
3583
3584 /* Process Unlocked */
3585 __HAL_UNLOCK(hi2c);
3586
3587 /* Note : The I2C interrupts must be enabled after unlocking current process
3588 to avoid the risk of I2C interrupt handle execution before current
3589 process unlock */
3590
3591 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
3592 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
3593 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
3594 {
3595 /* Enable DMA Request */
3596 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3597 }
3598
3599 /* Enable EVT and ERR interrupt */
3600 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
3601 }
3602 else
3603 {
3604 /* Update I2C state */
3605 hi2c->State = HAL_I2C_STATE_READY;
3606 hi2c->Mode = HAL_I2C_MODE_NONE;
3607
3608 /* Update I2C error code */
3609 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3610
3611 /* Process Unlocked */
3612 __HAL_UNLOCK(hi2c);
3613
3614 return HAL_ERROR;
3615 }
3616 }
3617 else
3618 {
3619 /* Enable Acknowledge */
3620 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3621
3622 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3623 /* Mean Previous state is same as current state */
3624 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3625 {
3626 /* Generate Start */
3627 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3628 }
3629
3630 /* Process Unlocked */
3631 __HAL_UNLOCK(hi2c);
3632
3633 /* Note : The I2C interrupts must be enabled after unlocking current process
3634 to avoid the risk of I2C interrupt handle execution before current
3635 process unlock */
3636
3637 /* Enable EVT, BUF and ERR interrupt */
3638 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3639 }
3640
3641 return HAL_OK;
3642 }
3643 else
3644 {
3645 return HAL_BUSY;
3646 }
3647 }
3648
3649 /**
3650 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3651 * @note This interface allow to manage repeated start condition when a direction change during transfer
3652 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3653 * the configuration information for the specified I2C.
3654 * @param DevAddress Target device address: The device 7 bits address value
3655 * in datasheet must be shifted to the left before calling the interface
3656 * @param pData Pointer to data buffer
3657 * @param Size Amount of data to be sent
3658 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3659 * @retval HAL status
3660 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3661 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3662 {
3663 __IO uint32_t Prev_State = 0x00U;
3664 __IO uint32_t count = 0U;
3665 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3666
3667 /* Check the parameters */
3668 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3669
3670 if (hi2c->State == HAL_I2C_STATE_READY)
3671 {
3672 /* Check Busy Flag only if FIRST call of Master interface */
3673 if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3674 {
3675 /* Wait until BUSY flag is reset */
3676 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3677 do
3678 {
3679 count--;
3680 if (count == 0U)
3681 {
3682 hi2c->PreviousState = I2C_STATE_NONE;
3683 hi2c->State = HAL_I2C_STATE_READY;
3684 hi2c->Mode = HAL_I2C_MODE_NONE;
3685 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3686
3687 /* Process Unlocked */
3688 __HAL_UNLOCK(hi2c);
3689
3690 return HAL_ERROR;
3691 }
3692 }
3693 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3694 }
3695
3696 /* Process Locked */
3697 __HAL_LOCK(hi2c);
3698
3699 /* Check if the I2C is already enabled */
3700 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3701 {
3702 /* Enable I2C peripheral */
3703 __HAL_I2C_ENABLE(hi2c);
3704 }
3705
3706 /* Disable Pos */
3707 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3708
3709 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3710 hi2c->Mode = HAL_I2C_MODE_MASTER;
3711 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3712
3713 /* Prepare transfer parameters */
3714 hi2c->pBuffPtr = pData;
3715 hi2c->XferCount = Size;
3716 hi2c->XferSize = hi2c->XferCount;
3717 hi2c->XferOptions = XferOptions;
3718 hi2c->Devaddress = DevAddress;
3719
3720 Prev_State = hi2c->PreviousState;
3721
3722 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
3723 {
3724 /* Disable Acknowledge */
3725 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3726
3727 /* Enable Pos */
3728 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3729
3730 /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */
3731 enableIT &= ~I2C_IT_BUF;
3732 }
3733 else
3734 {
3735 /* Enable Acknowledge */
3736 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3737 }
3738
3739 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3740 /* Mean Previous state is same as current state */
3741 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3742 {
3743 /* Generate Start */
3744 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3745 }
3746
3747 /* Process Unlocked */
3748 __HAL_UNLOCK(hi2c);
3749
3750 /* Note : The I2C interrupts must be enabled after unlocking current process
3751 to avoid the risk of I2C interrupt handle execution before current
3752 process unlock */
3753
3754 /* Enable interrupts */
3755 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
3756
3757 return HAL_OK;
3758 }
3759 else
3760 {
3761 return HAL_BUSY;
3762 }
3763 }
3764
3765 /**
3766 * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA
3767 * @note This interface allow to manage repeated start condition when a direction change during transfer
3768 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3769 * the configuration information for the specified I2C.
3770 * @param DevAddress Target device address: The device 7 bits address value
3771 * in datasheet must be shifted to the left before calling the interface
3772 * @param pData Pointer to data buffer
3773 * @param Size Amount of data to be sent
3774 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3775 * @retval HAL status
3776 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3777 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3778 {
3779 __IO uint32_t Prev_State = 0x00U;
3780 __IO uint32_t count = 0U;
3781 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3782 HAL_StatusTypeDef dmaxferstatus;
3783
3784 /* Check the parameters */
3785 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3786
3787 if (hi2c->State == HAL_I2C_STATE_READY)
3788 {
3789 /* Check Busy Flag only if FIRST call of Master interface */
3790 if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3791 {
3792 /* Wait until BUSY flag is reset */
3793 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3794 do
3795 {
3796 count--;
3797 if (count == 0U)
3798 {
3799 hi2c->PreviousState = I2C_STATE_NONE;
3800 hi2c->State = HAL_I2C_STATE_READY;
3801 hi2c->Mode = HAL_I2C_MODE_NONE;
3802 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3803
3804 /* Process Unlocked */
3805 __HAL_UNLOCK(hi2c);
3806
3807 return HAL_ERROR;
3808 }
3809 }
3810 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3811 }
3812
3813 /* Process Locked */
3814 __HAL_LOCK(hi2c);
3815
3816 /* Check if the I2C is already enabled */
3817 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3818 {
3819 /* Enable I2C peripheral */
3820 __HAL_I2C_ENABLE(hi2c);
3821 }
3822
3823 /* Disable Pos */
3824 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3825
3826 /* Clear Last DMA bit */
3827 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3828
3829 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3830 hi2c->Mode = HAL_I2C_MODE_MASTER;
3831 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3832
3833 /* Prepare transfer parameters */
3834 hi2c->pBuffPtr = pData;
3835 hi2c->XferCount = Size;
3836 hi2c->XferSize = hi2c->XferCount;
3837 hi2c->XferOptions = XferOptions;
3838 hi2c->Devaddress = DevAddress;
3839
3840 Prev_State = hi2c->PreviousState;
3841
3842 if (hi2c->XferSize > 0U)
3843 {
3844 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
3845 {
3846 /* Disable Acknowledge */
3847 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3848
3849 /* Enable Pos */
3850 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3851
3852 /* Enable Last DMA bit */
3853 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3854 }
3855 else
3856 {
3857 /* Enable Acknowledge */
3858 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3859
3860 if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
3861 {
3862 /* Enable Last DMA bit */
3863 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3864 }
3865 }
3866
3867 /* Set the I2C DMA transfer complete callback */
3868 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
3869
3870 /* Set the DMA error callback */
3871 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3872
3873 /* Set the unused DMA callbacks to NULL */
3874 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3875 hi2c->hdmarx->XferAbortCallback = NULL;
3876
3877 /* Enable the DMA stream */
3878 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
3879
3880 if (dmaxferstatus == HAL_OK)
3881 {
3882 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3883 /* Mean Previous state is same as current state */
3884 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3885 {
3886 /* Generate Start */
3887 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3888 }
3889
3890 /* Process Unlocked */
3891 __HAL_UNLOCK(hi2c);
3892
3893 /* Note : The I2C interrupts must be enabled after unlocking current process
3894 to avoid the risk of I2C interrupt handle execution before current
3895 process unlock */
3896
3897 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
3898 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
3899 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
3900 {
3901 /* Enable DMA Request */
3902 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3903 }
3904
3905 /* Enable EVT and ERR interrupt */
3906 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
3907 }
3908 else
3909 {
3910 /* Update I2C state */
3911 hi2c->State = HAL_I2C_STATE_READY;
3912 hi2c->Mode = HAL_I2C_MODE_NONE;
3913
3914 /* Update I2C error code */
3915 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3916
3917 /* Process Unlocked */
3918 __HAL_UNLOCK(hi2c);
3919
3920 return HAL_ERROR;
3921 }
3922 }
3923 else
3924 {
3925 /* Enable Acknowledge */
3926 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3927
3928 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3929 /* Mean Previous state is same as current state */
3930 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3931 {
3932 /* Generate Start */
3933 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3934 }
3935
3936 /* Process Unlocked */
3937 __HAL_UNLOCK(hi2c);
3938
3939 /* Note : The I2C interrupts must be enabled after unlocking current process
3940 to avoid the risk of I2C interrupt handle execution before current
3941 process unlock */
3942
3943 /* Enable interrupts */
3944 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
3945 }
3946 return HAL_OK;
3947 }
3948 else
3949 {
3950 return HAL_BUSY;
3951 }
3952 }
3953
3954 /**
3955 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt
3956 * @note This interface allow to manage repeated start condition when a direction change during transfer
3957 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3958 * the configuration information for the specified I2C.
3959 * @param pData Pointer to data buffer
3960 * @param Size Amount of data to be sent
3961 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3962 * @retval HAL status
3963 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3964 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3965 {
3966 /* Check the parameters */
3967 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3968
3969 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3970 {
3971 if ((pData == NULL) || (Size == 0U))
3972 {
3973 return HAL_ERROR;
3974 }
3975
3976 /* Process Locked */
3977 __HAL_LOCK(hi2c);
3978
3979 /* Check if the I2C is already enabled */
3980 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3981 {
3982 /* Enable I2C peripheral */
3983 __HAL_I2C_ENABLE(hi2c);
3984 }
3985
3986 /* Disable Pos */
3987 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3988
3989 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
3990 hi2c->Mode = HAL_I2C_MODE_SLAVE;
3991 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3992
3993 /* Prepare transfer parameters */
3994 hi2c->pBuffPtr = pData;
3995 hi2c->XferCount = Size;
3996 hi2c->XferSize = hi2c->XferCount;
3997 hi2c->XferOptions = XferOptions;
3998
3999 /* Clear ADDR flag */
4000 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4001
4002 /* Process Unlocked */
4003 __HAL_UNLOCK(hi2c);
4004
4005 /* Note : The I2C interrupts must be enabled after unlocking current process
4006 to avoid the risk of I2C interrupt handle execution before current
4007 process unlock */
4008
4009 /* Enable EVT, BUF and ERR interrupt */
4010 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4011
4012 return HAL_OK;
4013 }
4014 else
4015 {
4016 return HAL_BUSY;
4017 }
4018 }
4019
4020 /**
4021 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA
4022 * @note This interface allow to manage repeated start condition when a direction change during transfer
4023 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4024 * the configuration information for the specified I2C.
4025 * @param pData Pointer to data buffer
4026 * @param Size Amount of data to be sent
4027 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4028 * @retval HAL status
4029 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4030 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4031 {
4032 HAL_StatusTypeDef dmaxferstatus;
4033
4034 /* Check the parameters */
4035 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4036
4037 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4038 {
4039 if ((pData == NULL) || (Size == 0U))
4040 {
4041 return HAL_ERROR;
4042 }
4043
4044 /* Process Locked */
4045 __HAL_LOCK(hi2c);
4046
4047 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4048 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4049
4050 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4051 /* and then toggle the HAL slave RX state to TX state */
4052 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4053 {
4054 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4055 {
4056 /* Abort DMA Xfer if any */
4057 if (hi2c->hdmarx != NULL)
4058 {
4059 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4060
4061 /* Set the I2C DMA Abort callback :
4062 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4063 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4064
4065 /* Abort DMA RX */
4066 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4067 {
4068 /* Call Directly XferAbortCallback function in case of error */
4069 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4070 }
4071 }
4072 }
4073 }
4074 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4075 {
4076 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4077 {
4078 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4079
4080 /* Abort DMA Xfer if any */
4081 if (hi2c->hdmatx != NULL)
4082 {
4083 /* Set the I2C DMA Abort callback :
4084 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4085 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4086
4087 /* Abort DMA TX */
4088 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4089 {
4090 /* Call Directly XferAbortCallback function in case of error */
4091 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4092 }
4093 }
4094 }
4095 }
4096 else
4097 {
4098 /* Nothing to do */
4099 }
4100
4101 /* Check if the I2C is already enabled */
4102 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4103 {
4104 /* Enable I2C peripheral */
4105 __HAL_I2C_ENABLE(hi2c);
4106 }
4107
4108 /* Disable Pos */
4109 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4110
4111 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4112 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4113 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4114
4115 /* Prepare transfer parameters */
4116 hi2c->pBuffPtr = pData;
4117 hi2c->XferCount = Size;
4118 hi2c->XferSize = hi2c->XferCount;
4119 hi2c->XferOptions = XferOptions;
4120
4121 /* Set the I2C DMA transfer complete callback */
4122 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
4123
4124 /* Set the DMA error callback */
4125 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4126
4127 /* Set the unused DMA callbacks to NULL */
4128 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4129 hi2c->hdmatx->XferAbortCallback = NULL;
4130
4131 /* Enable the DMA stream */
4132 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
4133
4134 if (dmaxferstatus == HAL_OK)
4135 {
4136 /* Enable Address Acknowledge */
4137 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4138
4139 /* Clear ADDR flag */
4140 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4141
4142 /* Process Unlocked */
4143 __HAL_UNLOCK(hi2c);
4144
4145 /* Note : The I2C interrupts must be enabled after unlocking current process
4146 to avoid the risk of I2C interrupt handle execution before current
4147 process unlock */
4148 /* Enable EVT and ERR interrupt */
4149 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4150
4151 /* Enable DMA Request */
4152 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
4153
4154 return HAL_OK;
4155 }
4156 else
4157 {
4158 /* Update I2C state */
4159 hi2c->State = HAL_I2C_STATE_READY;
4160 hi2c->Mode = HAL_I2C_MODE_NONE;
4161
4162 /* Update I2C error code */
4163 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4164
4165 /* Process Unlocked */
4166 __HAL_UNLOCK(hi2c);
4167
4168 return HAL_ERROR;
4169 }
4170 }
4171 else
4172 {
4173 return HAL_BUSY;
4174 }
4175 }
4176
4177 /**
4178 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
4179 * @note This interface allow to manage repeated start condition when a direction change during transfer
4180 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4181 * the configuration information for the specified I2C.
4182 * @param pData Pointer to data buffer
4183 * @param Size Amount of data to be sent
4184 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4185 * @retval HAL status
4186 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4187 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4188 {
4189 /* Check the parameters */
4190 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4191
4192 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4193 {
4194 if ((pData == NULL) || (Size == 0U))
4195 {
4196 return HAL_ERROR;
4197 }
4198
4199 /* Process Locked */
4200 __HAL_LOCK(hi2c);
4201
4202 /* Check if the I2C is already enabled */
4203 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4204 {
4205 /* Enable I2C peripheral */
4206 __HAL_I2C_ENABLE(hi2c);
4207 }
4208
4209 /* Disable Pos */
4210 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4211
4212 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4213 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4214 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4215
4216 /* Prepare transfer parameters */
4217 hi2c->pBuffPtr = pData;
4218 hi2c->XferCount = Size;
4219 hi2c->XferSize = hi2c->XferCount;
4220 hi2c->XferOptions = XferOptions;
4221
4222 /* Clear ADDR flag */
4223 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4224
4225 /* Process Unlocked */
4226 __HAL_UNLOCK(hi2c);
4227
4228 /* Note : The I2C interrupts must be enabled after unlocking current process
4229 to avoid the risk of I2C interrupt handle execution before current
4230 process unlock */
4231
4232 /* Enable EVT, BUF and ERR interrupt */
4233 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4234
4235 return HAL_OK;
4236 }
4237 else
4238 {
4239 return HAL_BUSY;
4240 }
4241 }
4242
4243 /**
4244 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA
4245 * @note This interface allow to manage repeated start condition when a direction change during transfer
4246 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4247 * the configuration information for the specified I2C.
4248 * @param pData Pointer to data buffer
4249 * @param Size Amount of data to be sent
4250 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4251 * @retval HAL status
4252 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4253 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4254 {
4255 HAL_StatusTypeDef dmaxferstatus;
4256
4257 /* Check the parameters */
4258 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4259
4260 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4261 {
4262 if ((pData == NULL) || (Size == 0U))
4263 {
4264 return HAL_ERROR;
4265 }
4266
4267 /* Process Locked */
4268 __HAL_LOCK(hi2c);
4269
4270 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4271 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4272
4273 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4274 /* and then toggle the HAL slave RX state to TX state */
4275 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4276 {
4277 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4278 {
4279 /* Abort DMA Xfer if any */
4280 if (hi2c->hdmarx != NULL)
4281 {
4282 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4283
4284 /* Set the I2C DMA Abort callback :
4285 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4286 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4287
4288 /* Abort DMA RX */
4289 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4290 {
4291 /* Call Directly XferAbortCallback function in case of error */
4292 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4293 }
4294 }
4295 }
4296 }
4297 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4298 {
4299 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4300 {
4301 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4302
4303 /* Abort DMA Xfer if any */
4304 if (hi2c->hdmatx != NULL)
4305 {
4306 /* Set the I2C DMA Abort callback :
4307 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4308 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4309
4310 /* Abort DMA TX */
4311 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4312 {
4313 /* Call Directly XferAbortCallback function in case of error */
4314 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4315 }
4316 }
4317 }
4318 }
4319 else
4320 {
4321 /* Nothing to do */
4322 }
4323
4324 /* Check if the I2C is already enabled */
4325 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4326 {
4327 /* Enable I2C peripheral */
4328 __HAL_I2C_ENABLE(hi2c);
4329 }
4330
4331 /* Disable Pos */
4332 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4333
4334 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4335 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4336 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4337
4338 /* Prepare transfer parameters */
4339 hi2c->pBuffPtr = pData;
4340 hi2c->XferCount = Size;
4341 hi2c->XferSize = hi2c->XferCount;
4342 hi2c->XferOptions = XferOptions;
4343
4344 /* Set the I2C DMA transfer complete callback */
4345 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
4346
4347 /* Set the DMA error callback */
4348 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4349
4350 /* Set the unused DMA callbacks to NULL */
4351 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4352 hi2c->hdmarx->XferAbortCallback = NULL;
4353
4354 /* Enable the DMA stream */
4355 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4356
4357 if (dmaxferstatus == HAL_OK)
4358 {
4359 /* Enable Address Acknowledge */
4360 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4361
4362 /* Clear ADDR flag */
4363 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4364
4365 /* Process Unlocked */
4366 __HAL_UNLOCK(hi2c);
4367
4368 /* Enable DMA Request */
4369 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4370
4371 /* Note : The I2C interrupts must be enabled after unlocking current process
4372 to avoid the risk of I2C interrupt handle execution before current
4373 process unlock */
4374 /* Enable EVT and ERR interrupt */
4375 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4376
4377 return HAL_OK;
4378 }
4379 else
4380 {
4381 /* Update I2C state */
4382 hi2c->State = HAL_I2C_STATE_READY;
4383 hi2c->Mode = HAL_I2C_MODE_NONE;
4384
4385 /* Update I2C error code */
4386 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4387
4388 /* Process Unlocked */
4389 __HAL_UNLOCK(hi2c);
4390
4391 return HAL_ERROR;
4392 }
4393 }
4394 else
4395 {
4396 return HAL_BUSY;
4397 }
4398 }
4399
4400 /**
4401 * @brief Enable the Address listen mode with Interrupt.
4402 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4403 * the configuration information for the specified I2C.
4404 * @retval HAL status
4405 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4406 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4407 {
4408 if (hi2c->State == HAL_I2C_STATE_READY)
4409 {
4410 hi2c->State = HAL_I2C_STATE_LISTEN;
4411
4412 /* Check if the I2C is already enabled */
4413 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4414 {
4415 /* Enable I2C peripheral */
4416 __HAL_I2C_ENABLE(hi2c);
4417 }
4418
4419 /* Enable Address Acknowledge */
4420 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4421
4422 /* Enable EVT and ERR interrupt */
4423 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4424
4425 return HAL_OK;
4426 }
4427 else
4428 {
4429 return HAL_BUSY;
4430 }
4431 }
4432
4433 /**
4434 * @brief Disable the Address listen mode with Interrupt.
4435 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4436 * the configuration information for the specified I2C.
4437 * @retval HAL status
4438 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4439 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4440 {
4441 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4442 uint32_t tmp;
4443
4444 /* Disable Address listen mode only if a transfer is not ongoing */
4445 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4446 {
4447 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4448 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4449 hi2c->State = HAL_I2C_STATE_READY;
4450 hi2c->Mode = HAL_I2C_MODE_NONE;
4451
4452 /* Disable Address Acknowledge */
4453 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4454
4455 /* Disable EVT and ERR interrupt */
4456 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4457
4458 return HAL_OK;
4459 }
4460 else
4461 {
4462 return HAL_BUSY;
4463 }
4464 }
4465
4466 /**
4467 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4468 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4469 * the configuration information for the specified I2C.
4470 * @param DevAddress Target device address: The device 7 bits address value
4471 * in datasheet must be shifted to the left before calling the interface
4472 * @retval HAL status
4473 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4474 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4475 {
4476 /* Prevent unused argument(s) compilation warning */
4477 UNUSED(DevAddress);
4478
4479 /* Abort Master transfer during Receive or Transmit process */
4480 if (hi2c->Mode == HAL_I2C_MODE_MASTER)
4481 {
4482 /* Process Locked */
4483 __HAL_LOCK(hi2c);
4484
4485 hi2c->PreviousState = I2C_STATE_NONE;
4486 hi2c->State = HAL_I2C_STATE_ABORT;
4487
4488 /* Disable Acknowledge */
4489 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4490
4491 /* Generate Stop */
4492 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
4493
4494 hi2c->XferCount = 0U;
4495
4496 /* Disable EVT, BUF and ERR interrupt */
4497 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4498
4499 /* Process Unlocked */
4500 __HAL_UNLOCK(hi2c);
4501
4502 /* Call the corresponding callback to inform upper layer of End of Transfer */
4503 I2C_ITError(hi2c);
4504
4505 return HAL_OK;
4506 }
4507 else
4508 {
4509 /* Wrong usage of abort function */
4510 /* This function should be used only in case of abort monitored by master device */
4511 return HAL_ERROR;
4512 }
4513 }
4514
4515 /**
4516 * @}
4517 */
4518
4519 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4520 * @{
4521 */
4522
4523 /**
4524 * @brief This function handles I2C event interrupt request.
4525 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4526 * the configuration information for the specified I2C.
4527 * @retval None
4528 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4529 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
4530 {
4531 uint32_t sr1itflags;
4532 uint32_t sr2itflags = 0U;
4533 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
4534 uint32_t CurrentXferOptions = hi2c->XferOptions;
4535 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4536 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
4537
4538 /* Master or Memory mode selected */
4539 if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
4540 {
4541 sr2itflags = READ_REG(hi2c->Instance->SR2);
4542 sr1itflags = READ_REG(hi2c->Instance->SR1);
4543
4544 /* Exit IRQ event until Start Bit detected in case of Other frame requested */
4545 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U))
4546 {
4547 return;
4548 }
4549
4550 /* SB Set ----------------------------------------------------------------*/
4551 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4552 {
4553 /* Convert OTHER_xxx XferOptions if any */
4554 I2C_ConvertOtherXferOptions(hi2c);
4555
4556 I2C_Master_SB(hi2c);
4557 }
4558 /* ADD10 Set -------------------------------------------------------------*/
4559 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4560 {
4561 I2C_Master_ADD10(hi2c);
4562 }
4563 /* ADDR Set --------------------------------------------------------------*/
4564 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4565 {
4566 I2C_Master_ADDR(hi2c);
4567 }
4568 /* I2C in mode Transmitter -----------------------------------------------*/
4569 else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET)
4570 {
4571 /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4572 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4573 {
4574 /* TXE set and BTF reset -----------------------------------------------*/
4575 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4576 {
4577 I2C_MasterTransmit_TXE(hi2c);
4578 }
4579 /* BTF set -------------------------------------------------------------*/
4580 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4581 {
4582 I2C_MasterTransmit_BTF(hi2c);
4583 }
4584 else
4585 {
4586 /* Do nothing */
4587 }
4588 }
4589 }
4590 /* I2C in mode Receiver --------------------------------------------------*/
4591 else
4592 {
4593 /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4594 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4595 {
4596 /* RXNE set and BTF reset -----------------------------------------------*/
4597 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4598 {
4599 I2C_MasterReceive_RXNE(hi2c);
4600 }
4601 /* BTF set -------------------------------------------------------------*/
4602 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4603 {
4604 I2C_MasterReceive_BTF(hi2c);
4605 }
4606 else
4607 {
4608 /* Do nothing */
4609 }
4610 }
4611 }
4612 }
4613 /* Slave mode selected */
4614 else
4615 {
4616 /* If an error is detected, read only SR1 register to prevent */
4617 /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */
4618 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4619 {
4620 sr1itflags = READ_REG(hi2c->Instance->SR1);
4621 }
4622 else
4623 {
4624 sr2itflags = READ_REG(hi2c->Instance->SR2);
4625 sr1itflags = READ_REG(hi2c->Instance->SR1);
4626 }
4627
4628 /* ADDR set --------------------------------------------------------------*/
4629 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4630 {
4631 /* Now time to read SR2, this will clear ADDR flag automatically */
4632 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4633 {
4634 sr2itflags = READ_REG(hi2c->Instance->SR2);
4635 }
4636 I2C_Slave_ADDR(hi2c, sr2itflags);
4637 }
4638 /* STOPF set --------------------------------------------------------------*/
4639 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4640 {
4641 I2C_Slave_STOPF(hi2c);
4642 }
4643 /* I2C in mode Transmitter -----------------------------------------------*/
4644 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
4645 {
4646 /* TXE set and BTF reset -----------------------------------------------*/
4647 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4648 {
4649 I2C_SlaveTransmit_TXE(hi2c);
4650 }
4651 /* BTF set -------------------------------------------------------------*/
4652 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4653 {
4654 I2C_SlaveTransmit_BTF(hi2c);
4655 }
4656 else
4657 {
4658 /* Do nothing */
4659 }
4660 }
4661 /* I2C in mode Receiver --------------------------------------------------*/
4662 else
4663 {
4664 /* RXNE set and BTF reset ----------------------------------------------*/
4665 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4666 {
4667 I2C_SlaveReceive_RXNE(hi2c);
4668 }
4669 /* BTF set -------------------------------------------------------------*/
4670 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4671 {
4672 I2C_SlaveReceive_BTF(hi2c);
4673 }
4674 else
4675 {
4676 /* Do nothing */
4677 }
4678 }
4679 }
4680 }
4681
4682 /**
4683 * @brief This function handles I2C error interrupt request.
4684 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4685 * the configuration information for the specified I2C.
4686 * @retval None
4687 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4688 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4689 {
4690 HAL_I2C_ModeTypeDef tmp1;
4691 uint32_t tmp2;
4692 HAL_I2C_StateTypeDef tmp3;
4693 uint32_t tmp4;
4694 uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
4695 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
4696 uint32_t error = HAL_I2C_ERROR_NONE;
4697
4698 /* I2C Bus error interrupt occurred ----------------------------------------*/
4699 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4700 {
4701 error |= HAL_I2C_ERROR_BERR;
4702
4703 /* Clear BERR flag */
4704 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4705 }
4706
4707 /* I2C Arbitration Lost error interrupt occurred ---------------------------*/
4708 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4709 {
4710 error |= HAL_I2C_ERROR_ARLO;
4711
4712 /* Clear ARLO flag */
4713 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4714 }
4715
4716 /* I2C Acknowledge failure error interrupt occurred ------------------------*/
4717 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4718 {
4719 tmp1 = hi2c->Mode;
4720 tmp2 = hi2c->XferCount;
4721 tmp3 = hi2c->State;
4722 tmp4 = hi2c->PreviousState;
4723 if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
4724 ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
4725 ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
4726 {
4727 I2C_Slave_AF(hi2c);
4728 }
4729 else
4730 {
4731 /* Clear AF flag */
4732 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4733
4734 error |= HAL_I2C_ERROR_AF;
4735
4736 /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
4737 if (hi2c->Mode == HAL_I2C_MODE_MASTER)
4738 {
4739 /* Generate Stop */
4740 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
4741 }
4742 }
4743 }
4744
4745 /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
4746 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4747 {
4748 error |= HAL_I2C_ERROR_OVR;
4749 /* Clear OVR flag */
4750 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4751 }
4752
4753 /* Call the Error Callback in case of Error detected -----------------------*/
4754 if (error != HAL_I2C_ERROR_NONE)
4755 {
4756 hi2c->ErrorCode |= error;
4757 I2C_ITError(hi2c);
4758 }
4759 }
4760
4761 /**
4762 * @brief Master Tx Transfer completed callback.
4763 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4764 * the configuration information for the specified I2C.
4765 * @retval None
4766 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)4767 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4768 {
4769 /* Prevent unused argument(s) compilation warning */
4770 UNUSED(hi2c);
4771
4772 /* NOTE : This function should not be modified, when the callback is needed,
4773 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4774 */
4775 }
4776
4777 /**
4778 * @brief Master Rx Transfer completed callback.
4779 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4780 * the configuration information for the specified I2C.
4781 * @retval None
4782 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)4783 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
4784 {
4785 /* Prevent unused argument(s) compilation warning */
4786 UNUSED(hi2c);
4787
4788 /* NOTE : This function should not be modified, when the callback is needed,
4789 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
4790 */
4791 }
4792
4793 /** @brief Slave Tx Transfer completed callback.
4794 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4795 * the configuration information for the specified I2C.
4796 * @retval None
4797 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)4798 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
4799 {
4800 /* Prevent unused argument(s) compilation warning */
4801 UNUSED(hi2c);
4802
4803 /* NOTE : This function should not be modified, when the callback is needed,
4804 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
4805 */
4806 }
4807
4808 /**
4809 * @brief Slave Rx Transfer completed callback.
4810 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4811 * the configuration information for the specified I2C.
4812 * @retval None
4813 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)4814 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
4815 {
4816 /* Prevent unused argument(s) compilation warning */
4817 UNUSED(hi2c);
4818
4819 /* NOTE : This function should not be modified, when the callback is needed,
4820 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
4821 */
4822 }
4823
4824 /**
4825 * @brief Slave Address Match callback.
4826 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4827 * the configuration information for the specified I2C.
4828 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition
4829 * @param AddrMatchCode Address Match Code
4830 * @retval None
4831 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)4832 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
4833 {
4834 /* Prevent unused argument(s) compilation warning */
4835 UNUSED(hi2c);
4836 UNUSED(TransferDirection);
4837 UNUSED(AddrMatchCode);
4838
4839 /* NOTE : This function should not be modified, when the callback is needed,
4840 the HAL_I2C_AddrCallback() could be implemented in the user file
4841 */
4842 }
4843
4844 /**
4845 * @brief Listen Complete callback.
4846 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4847 * the configuration information for the specified I2C.
4848 * @retval None
4849 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)4850 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
4851 {
4852 /* Prevent unused argument(s) compilation warning */
4853 UNUSED(hi2c);
4854
4855 /* NOTE : This function should not be modified, when the callback is needed,
4856 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
4857 */
4858 }
4859
4860 /**
4861 * @brief Memory Tx Transfer completed callback.
4862 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4863 * the configuration information for the specified I2C.
4864 * @retval None
4865 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)4866 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
4867 {
4868 /* Prevent unused argument(s) compilation warning */
4869 UNUSED(hi2c);
4870
4871 /* NOTE : This function should not be modified, when the callback is needed,
4872 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
4873 */
4874 }
4875
4876 /**
4877 * @brief Memory Rx Transfer completed callback.
4878 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4879 * the configuration information for the specified I2C.
4880 * @retval None
4881 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)4882 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
4883 {
4884 /* Prevent unused argument(s) compilation warning */
4885 UNUSED(hi2c);
4886
4887 /* NOTE : This function should not be modified, when the callback is needed,
4888 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
4889 */
4890 }
4891
4892 /**
4893 * @brief I2C error callback.
4894 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4895 * the configuration information for the specified I2C.
4896 * @retval None
4897 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)4898 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
4899 {
4900 /* Prevent unused argument(s) compilation warning */
4901 UNUSED(hi2c);
4902
4903 /* NOTE : This function should not be modified, when the callback is needed,
4904 the HAL_I2C_ErrorCallback could be implemented in the user file
4905 */
4906 }
4907
4908 /**
4909 * @brief I2C abort callback.
4910 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4911 * the configuration information for the specified I2C.
4912 * @retval None
4913 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)4914 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
4915 {
4916 /* Prevent unused argument(s) compilation warning */
4917 UNUSED(hi2c);
4918
4919 /* NOTE : This function should not be modified, when the callback is needed,
4920 the HAL_I2C_AbortCpltCallback could be implemented in the user file
4921 */
4922 }
4923
4924 /**
4925 * @}
4926 */
4927
4928 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
4929 * @brief Peripheral State, Mode and Error functions
4930 *
4931 @verbatim
4932 ===============================================================================
4933 ##### Peripheral State, Mode and Error functions #####
4934 ===============================================================================
4935 [..]
4936 This subsection permit to get in run-time the status of the peripheral
4937 and the data flow.
4938
4939 @endverbatim
4940 * @{
4941 */
4942
4943 /**
4944 * @brief Return the I2C handle state.
4945 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4946 * the configuration information for the specified I2C.
4947 * @retval HAL state
4948 */
HAL_I2C_GetState(I2C_HandleTypeDef * hi2c)4949 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
4950 {
4951 /* Return I2C handle state */
4952 return hi2c->State;
4953 }
4954
4955 /**
4956 * @brief Returns the I2C Master, Slave, Memory or no mode.
4957 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4958 * the configuration information for I2C module
4959 * @retval HAL mode
4960 */
HAL_I2C_GetMode(I2C_HandleTypeDef * hi2c)4961 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
4962 {
4963 return hi2c->Mode;
4964 }
4965
4966 /**
4967 * @brief Return the I2C error code.
4968 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4969 * the configuration information for the specified I2C.
4970 * @retval I2C Error Code
4971 */
HAL_I2C_GetError(I2C_HandleTypeDef * hi2c)4972 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
4973 {
4974 return hi2c->ErrorCode;
4975 }
4976
4977 /**
4978 * @}
4979 */
4980
4981 /**
4982 * @}
4983 */
4984
4985 /** @addtogroup I2C_Private_Functions
4986 * @{
4987 */
4988
4989 /**
4990 * @brief Handle TXE flag for Master
4991 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4992 * the configuration information for I2C module
4993 * @retval None
4994 */
I2C_MasterTransmit_TXE(I2C_HandleTypeDef * hi2c)4995 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
4996 {
4997 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
4998 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
4999 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
5000 uint32_t CurrentXferOptions = hi2c->XferOptions;
5001
5002 if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5003 {
5004 /* Call TxCpltCallback() directly if no stop mode is set */
5005 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5006 {
5007 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5008
5009 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5010 hi2c->Mode = HAL_I2C_MODE_NONE;
5011 hi2c->State = HAL_I2C_STATE_READY;
5012
5013 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5014 hi2c->MasterTxCpltCallback(hi2c);
5015 #else
5016 HAL_I2C_MasterTxCpltCallback(hi2c);
5017 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5018 }
5019 else /* Generate Stop condition then Call TxCpltCallback() */
5020 {
5021 /* Disable EVT, BUF and ERR interrupt */
5022 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5023
5024 /* Generate Stop */
5025 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5026
5027 hi2c->PreviousState = I2C_STATE_NONE;
5028 hi2c->State = HAL_I2C_STATE_READY;
5029
5030 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5031 {
5032 hi2c->Mode = HAL_I2C_MODE_NONE;
5033 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5034 hi2c->MemTxCpltCallback(hi2c);
5035 #else
5036 HAL_I2C_MemTxCpltCallback(hi2c);
5037 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5038 }
5039 else
5040 {
5041 hi2c->Mode = HAL_I2C_MODE_NONE;
5042 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5043 hi2c->MasterTxCpltCallback(hi2c);
5044 #else
5045 HAL_I2C_MasterTxCpltCallback(hi2c);
5046 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5047 }
5048 }
5049 }
5050 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
5051 ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
5052 {
5053 if (hi2c->XferCount == 0U)
5054 {
5055 /* Disable BUF interrupt */
5056 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5057 }
5058 else
5059 {
5060 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5061 {
5062 if (hi2c->EventCount == 0U)
5063 {
5064 /* If Memory address size is 8Bit */
5065 if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
5066 {
5067 /* Send Memory Address */
5068 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5069
5070 hi2c->EventCount += 2U;
5071 }
5072 /* If Memory address size is 16Bit */
5073 else
5074 {
5075 /* Send MSB of Memory Address */
5076 hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
5077
5078 hi2c->EventCount++;
5079 }
5080 }
5081 else if (hi2c->EventCount == 1U)
5082 {
5083 /* Send LSB of Memory Address */
5084 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5085
5086 hi2c->EventCount++;
5087 }
5088 else if (hi2c->EventCount == 2U)
5089 {
5090 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5091 {
5092 /* Generate Restart */
5093 hi2c->Instance->CR1 |= I2C_CR1_START;
5094 }
5095 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5096 {
5097 /* Write data to DR */
5098 hi2c->Instance->DR = *hi2c->pBuffPtr;
5099
5100 /* Increment Buffer pointer */
5101 hi2c->pBuffPtr++;
5102
5103 /* Update counter */
5104 hi2c->XferCount--;
5105 }
5106 else
5107 {
5108 /* Do nothing */
5109 }
5110 }
5111 else
5112 {
5113 /* Do nothing */
5114 }
5115 }
5116 else
5117 {
5118 /* Write data to DR */
5119 hi2c->Instance->DR = *hi2c->pBuffPtr;
5120
5121 /* Increment Buffer pointer */
5122 hi2c->pBuffPtr++;
5123
5124 /* Update counter */
5125 hi2c->XferCount--;
5126 }
5127 }
5128 }
5129 else
5130 {
5131 /* Do nothing */
5132 }
5133 }
5134
5135 /**
5136 * @brief Handle BTF flag for Master transmitter
5137 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5138 * the configuration information for I2C module
5139 * @retval None
5140 */
I2C_MasterTransmit_BTF(I2C_HandleTypeDef * hi2c)5141 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
5142 {
5143 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5144 uint32_t CurrentXferOptions = hi2c->XferOptions;
5145
5146 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5147 {
5148 if (hi2c->XferCount != 0U)
5149 {
5150 /* Write data to DR */
5151 hi2c->Instance->DR = *hi2c->pBuffPtr;
5152
5153 /* Increment Buffer pointer */
5154 hi2c->pBuffPtr++;
5155
5156 /* Update counter */
5157 hi2c->XferCount--;
5158 }
5159 else
5160 {
5161 /* Call TxCpltCallback() directly if no stop mode is set */
5162 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5163 {
5164 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5165
5166 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5167 hi2c->Mode = HAL_I2C_MODE_NONE;
5168 hi2c->State = HAL_I2C_STATE_READY;
5169
5170 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5171 hi2c->MasterTxCpltCallback(hi2c);
5172 #else
5173 HAL_I2C_MasterTxCpltCallback(hi2c);
5174 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5175 }
5176 else /* Generate Stop condition then Call TxCpltCallback() */
5177 {
5178 /* Disable EVT, BUF and ERR interrupt */
5179 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5180
5181 /* Generate Stop */
5182 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5183
5184 hi2c->PreviousState = I2C_STATE_NONE;
5185 hi2c->State = HAL_I2C_STATE_READY;
5186
5187 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5188 {
5189 hi2c->Mode = HAL_I2C_MODE_NONE;
5190 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5191 hi2c->MemTxCpltCallback(hi2c);
5192 #else
5193 HAL_I2C_MemTxCpltCallback(hi2c);
5194 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5195 }
5196 else
5197 {
5198 hi2c->Mode = HAL_I2C_MODE_NONE;
5199
5200 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5201 hi2c->MasterTxCpltCallback(hi2c);
5202 #else
5203 HAL_I2C_MasterTxCpltCallback(hi2c);
5204 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5205 }
5206 }
5207 }
5208 }
5209 }
5210
5211 /**
5212 * @brief Handle RXNE flag for Master
5213 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5214 * the configuration information for I2C module
5215 * @retval None
5216 */
I2C_MasterReceive_RXNE(I2C_HandleTypeDef * hi2c)5217 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
5218 {
5219 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5220 {
5221 uint32_t tmp;
5222
5223 tmp = hi2c->XferCount;
5224 if (tmp > 3U)
5225 {
5226 /* Read data from DR */
5227 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5228
5229 /* Increment Buffer pointer */
5230 hi2c->pBuffPtr++;
5231
5232 /* Update counter */
5233 hi2c->XferCount--;
5234
5235 if (hi2c->XferCount == (uint16_t)3)
5236 {
5237 /* Disable BUF interrupt, this help to treat correctly the last 4 bytes
5238 on BTF subroutine */
5239 /* Disable BUF interrupt */
5240 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5241 }
5242 }
5243 else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U)))
5244 {
5245 /* Disable Acknowledge */
5246 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5247
5248 /* Disable EVT, BUF and ERR interrupt */
5249 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5250
5251 /* Read data from DR */
5252 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5253
5254 /* Increment Buffer pointer */
5255 hi2c->pBuffPtr++;
5256
5257 /* Update counter */
5258 hi2c->XferCount--;
5259
5260 hi2c->State = HAL_I2C_STATE_READY;
5261
5262 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5263 {
5264 hi2c->Mode = HAL_I2C_MODE_NONE;
5265 hi2c->PreviousState = I2C_STATE_NONE;
5266
5267 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5268 hi2c->MemRxCpltCallback(hi2c);
5269 #else
5270 HAL_I2C_MemRxCpltCallback(hi2c);
5271 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5272 }
5273 else
5274 {
5275 hi2c->Mode = HAL_I2C_MODE_NONE;
5276 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5277
5278 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5279 hi2c->MasterRxCpltCallback(hi2c);
5280 #else
5281 HAL_I2C_MasterRxCpltCallback(hi2c);
5282 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5283 }
5284 }
5285 else
5286 {
5287 /* Do nothing */
5288 }
5289 }
5290 }
5291
5292 /**
5293 * @brief Handle BTF flag for Master receiver
5294 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5295 * the configuration information for I2C module
5296 * @retval None
5297 */
I2C_MasterReceive_BTF(I2C_HandleTypeDef * hi2c)5298 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
5299 {
5300 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5301 uint32_t CurrentXferOptions = hi2c->XferOptions;
5302
5303 if (hi2c->XferCount == 4U)
5304 {
5305 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5306 on BTF subroutine if there is a reception delay between N-1 and N byte */
5307 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5308
5309 /* Read data from DR */
5310 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5311
5312 /* Increment Buffer pointer */
5313 hi2c->pBuffPtr++;
5314
5315 /* Update counter */
5316 hi2c->XferCount--;
5317 }
5318 else if (hi2c->XferCount == 3U)
5319 {
5320 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5321 on BTF subroutine if there is a reception delay between N-1 and N byte */
5322 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5323
5324 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME))
5325 {
5326 /* Disable Acknowledge */
5327 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5328 }
5329
5330 /* Read data from DR */
5331 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5332
5333 /* Increment Buffer pointer */
5334 hi2c->pBuffPtr++;
5335
5336 /* Update counter */
5337 hi2c->XferCount--;
5338 }
5339 else if (hi2c->XferCount == 2U)
5340 {
5341 /* Prepare next transfer or stop current transfer */
5342 if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP))
5343 {
5344 /* Disable Acknowledge */
5345 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5346 }
5347 else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME))
5348 {
5349 /* Enable Acknowledge */
5350 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5351 }
5352 else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)
5353 {
5354 /* Generate Stop */
5355 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5356 }
5357 else
5358 {
5359 /* Do nothing */
5360 }
5361
5362 /* Read data from DR */
5363 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5364
5365 /* Increment Buffer pointer */
5366 hi2c->pBuffPtr++;
5367
5368 /* Update counter */
5369 hi2c->XferCount--;
5370
5371 /* Read data from DR */
5372 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5373
5374 /* Increment Buffer pointer */
5375 hi2c->pBuffPtr++;
5376
5377 /* Update counter */
5378 hi2c->XferCount--;
5379
5380 /* Disable EVT and ERR interrupt */
5381 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
5382
5383 hi2c->State = HAL_I2C_STATE_READY;
5384 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5385 {
5386 hi2c->Mode = HAL_I2C_MODE_NONE;
5387 hi2c->PreviousState = I2C_STATE_NONE;
5388 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5389 hi2c->MemRxCpltCallback(hi2c);
5390 #else
5391 HAL_I2C_MemRxCpltCallback(hi2c);
5392 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5393 }
5394 else
5395 {
5396 hi2c->Mode = HAL_I2C_MODE_NONE;
5397 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5398 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5399 hi2c->MasterRxCpltCallback(hi2c);
5400 #else
5401 HAL_I2C_MasterRxCpltCallback(hi2c);
5402 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5403 }
5404 }
5405 else
5406 {
5407 /* Read data from DR */
5408 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5409
5410 /* Increment Buffer pointer */
5411 hi2c->pBuffPtr++;
5412
5413 /* Update counter */
5414 hi2c->XferCount--;
5415 }
5416 }
5417
5418 /**
5419 * @brief Handle SB flag for Master
5420 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5421 * the configuration information for I2C module
5422 * @retval None
5423 */
I2C_Master_SB(I2C_HandleTypeDef * hi2c)5424 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c)
5425 {
5426 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5427 {
5428 if (hi2c->EventCount == 0U)
5429 {
5430 /* Send slave address */
5431 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5432 }
5433 else
5434 {
5435 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5436 }
5437 }
5438 else
5439 {
5440 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
5441 {
5442 /* Send slave 7 Bits address */
5443 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5444 {
5445 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5446 }
5447 else
5448 {
5449 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5450 }
5451
5452 if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL))
5453 {
5454 /* Enable DMA Request */
5455 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5456 }
5457 }
5458 else
5459 {
5460 if (hi2c->EventCount == 0U)
5461 {
5462 /* Send header of slave address */
5463 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
5464 }
5465 else if (hi2c->EventCount == 1U)
5466 {
5467 /* Send header of slave address */
5468 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
5469 }
5470 else
5471 {
5472 /* Do nothing */
5473 }
5474 }
5475 }
5476 }
5477
5478 /**
5479 * @brief Handle ADD10 flag for Master
5480 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5481 * the configuration information for I2C module
5482 * @retval None
5483 */
I2C_Master_ADD10(I2C_HandleTypeDef * hi2c)5484 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
5485 {
5486 /* Send slave address */
5487 hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
5488
5489 if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL))
5490 {
5491 if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL))
5492 {
5493 /* Enable DMA Request */
5494 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5495 }
5496 }
5497 }
5498
5499 /**
5500 * @brief Handle ADDR flag for Master
5501 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5502 * the configuration information for I2C module
5503 * @retval None
5504 */
I2C_Master_ADDR(I2C_HandleTypeDef * hi2c)5505 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
5506 {
5507 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
5508 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
5509 uint32_t CurrentXferOptions = hi2c->XferOptions;
5510 uint32_t Prev_State = hi2c->PreviousState;
5511
5512 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5513 {
5514 if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
5515 {
5516 /* Clear ADDR flag */
5517 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5518 }
5519 else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
5520 {
5521 /* Clear ADDR flag */
5522 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5523
5524 /* Generate Restart */
5525 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
5526
5527 hi2c->EventCount++;
5528 }
5529 else
5530 {
5531 if (hi2c->XferCount == 0U)
5532 {
5533 /* Clear ADDR flag */
5534 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5535
5536 /* Generate Stop */
5537 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5538 }
5539 else if (hi2c->XferCount == 1U)
5540 {
5541 if (CurrentXferOptions == I2C_NO_OPTION_FRAME)
5542 {
5543 /* Disable Acknowledge */
5544 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5545
5546 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
5547 {
5548 /* Disable Acknowledge */
5549 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5550
5551 /* Clear ADDR flag */
5552 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5553 }
5554 else
5555 {
5556 /* Clear ADDR flag */
5557 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5558
5559 /* Generate Stop */
5560 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5561 }
5562 }
5563 /* Prepare next transfer or stop current transfer */
5564 else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
5565 && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME)))
5566 {
5567 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
5568 {
5569 /* Disable Acknowledge */
5570 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5571 }
5572 else
5573 {
5574 /* Enable Acknowledge */
5575 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5576 }
5577
5578 /* Clear ADDR flag */
5579 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5580 }
5581 else
5582 {
5583 /* Disable Acknowledge */
5584 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5585
5586 /* Clear ADDR flag */
5587 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5588
5589 /* Generate Stop */
5590 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5591 }
5592 }
5593 else if (hi2c->XferCount == 2U)
5594 {
5595 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
5596 {
5597 /* Disable Acknowledge */
5598 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5599
5600 /* Enable Pos */
5601 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
5602 }
5603 else
5604 {
5605 /* Enable Acknowledge */
5606 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5607 }
5608
5609 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
5610 {
5611 /* Enable Last DMA bit */
5612 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
5613 }
5614
5615 /* Clear ADDR flag */
5616 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5617 }
5618 else
5619 {
5620 /* Enable Acknowledge */
5621 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5622
5623 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
5624 {
5625 /* Enable Last DMA bit */
5626 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
5627 }
5628
5629 /* Clear ADDR flag */
5630 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5631 }
5632
5633 /* Reset Event counter */
5634 hi2c->EventCount = 0U;
5635 }
5636 }
5637 else
5638 {
5639 /* Clear ADDR flag */
5640 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5641 }
5642 }
5643
5644 /**
5645 * @brief Handle TXE flag for Slave
5646 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5647 * the configuration information for I2C module
5648 * @retval None
5649 */
I2C_SlaveTransmit_TXE(I2C_HandleTypeDef * hi2c)5650 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
5651 {
5652 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5653 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5654
5655 if (hi2c->XferCount != 0U)
5656 {
5657 /* Write data to DR */
5658 hi2c->Instance->DR = *hi2c->pBuffPtr;
5659
5660 /* Increment Buffer pointer */
5661 hi2c->pBuffPtr++;
5662
5663 /* Update counter */
5664 hi2c->XferCount--;
5665
5666 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
5667 {
5668 /* Last Byte is received, disable Interrupt */
5669 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5670
5671 /* Set state at HAL_I2C_STATE_LISTEN */
5672 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5673 hi2c->State = HAL_I2C_STATE_LISTEN;
5674
5675 /* Call the corresponding callback to inform upper layer of End of Transfer */
5676 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5677 hi2c->SlaveTxCpltCallback(hi2c);
5678 #else
5679 HAL_I2C_SlaveTxCpltCallback(hi2c);
5680 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5681 }
5682 }
5683 }
5684
5685 /**
5686 * @brief Handle BTF flag for Slave transmitter
5687 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5688 * the configuration information for I2C module
5689 * @retval None
5690 */
I2C_SlaveTransmit_BTF(I2C_HandleTypeDef * hi2c)5691 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
5692 {
5693 if (hi2c->XferCount != 0U)
5694 {
5695 /* Write data to DR */
5696 hi2c->Instance->DR = *hi2c->pBuffPtr;
5697
5698 /* Increment Buffer pointer */
5699 hi2c->pBuffPtr++;
5700
5701 /* Update counter */
5702 hi2c->XferCount--;
5703 }
5704 }
5705
5706 /**
5707 * @brief Handle RXNE flag for Slave
5708 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5709 * the configuration information for I2C module
5710 * @retval None
5711 */
I2C_SlaveReceive_RXNE(I2C_HandleTypeDef * hi2c)5712 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
5713 {
5714 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5715 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5716
5717 if (hi2c->XferCount != 0U)
5718 {
5719 /* Read data from DR */
5720 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5721
5722 /* Increment Buffer pointer */
5723 hi2c->pBuffPtr++;
5724
5725 /* Update counter */
5726 hi2c->XferCount--;
5727
5728 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
5729 {
5730 /* Last Byte is received, disable Interrupt */
5731 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5732
5733 /* Set state at HAL_I2C_STATE_LISTEN */
5734 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5735 hi2c->State = HAL_I2C_STATE_LISTEN;
5736
5737 /* Call the corresponding callback to inform upper layer of End of Transfer */
5738 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5739 hi2c->SlaveRxCpltCallback(hi2c);
5740 #else
5741 HAL_I2C_SlaveRxCpltCallback(hi2c);
5742 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5743 }
5744 }
5745 }
5746
5747 /**
5748 * @brief Handle BTF flag for Slave receiver
5749 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5750 * the configuration information for I2C module
5751 * @retval None
5752 */
I2C_SlaveReceive_BTF(I2C_HandleTypeDef * hi2c)5753 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
5754 {
5755 if (hi2c->XferCount != 0U)
5756 {
5757 /* Read data from DR */
5758 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5759
5760 /* Increment Buffer pointer */
5761 hi2c->pBuffPtr++;
5762
5763 /* Update counter */
5764 hi2c->XferCount--;
5765 }
5766 }
5767
5768 /**
5769 * @brief Handle ADD flag for Slave
5770 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5771 * the configuration information for I2C module
5772 * @param IT2Flags Interrupt2 flags to handle.
5773 * @retval None
5774 */
I2C_Slave_ADDR(I2C_HandleTypeDef * hi2c,uint32_t IT2Flags)5775 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags)
5776 {
5777 uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
5778 uint16_t SlaveAddrCode;
5779
5780 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
5781 {
5782 /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */
5783 __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF));
5784
5785 /* Transfer Direction requested by Master */
5786 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET)
5787 {
5788 TransferDirection = I2C_DIRECTION_TRANSMIT;
5789 }
5790
5791 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET)
5792 {
5793 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1;
5794 }
5795 else
5796 {
5797 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2;
5798 }
5799
5800 /* Process Unlocked */
5801 __HAL_UNLOCK(hi2c);
5802
5803 /* Call Slave Addr callback */
5804 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5805 hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
5806 #else
5807 HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
5808 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5809 }
5810 else
5811 {
5812 /* Clear ADDR flag */
5813 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5814
5815 /* Process Unlocked */
5816 __HAL_UNLOCK(hi2c);
5817 }
5818 }
5819
5820 /**
5821 * @brief Handle STOPF flag for Slave
5822 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5823 * the configuration information for I2C module
5824 * @retval None
5825 */
I2C_Slave_STOPF(I2C_HandleTypeDef * hi2c)5826 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
5827 {
5828 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
5829 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5830
5831 /* Disable EVT, BUF and ERR interrupt */
5832 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5833
5834 /* Clear STOPF flag */
5835 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
5836
5837 /* Disable Acknowledge */
5838 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5839
5840 /* If a DMA is ongoing, Update handle size context */
5841 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
5842 {
5843 if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
5844 {
5845 hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx));
5846
5847 if (hi2c->XferCount != 0U)
5848 {
5849 /* Set ErrorCode corresponding to a Non-Acknowledge */
5850 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5851 }
5852
5853 /* Disable, stop the current DMA */
5854 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5855
5856 /* Abort DMA Xfer if any */
5857 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
5858 {
5859 /* Set the I2C DMA Abort callback :
5860 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
5861 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
5862
5863 /* Abort DMA RX */
5864 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
5865 {
5866 /* Call Directly XferAbortCallback function in case of error */
5867 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
5868 }
5869 }
5870 }
5871 else
5872 {
5873 hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx));
5874
5875 if (hi2c->XferCount != 0U)
5876 {
5877 /* Set ErrorCode corresponding to a Non-Acknowledge */
5878 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5879 }
5880
5881 /* Disable, stop the current DMA */
5882 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5883
5884 /* Abort DMA Xfer if any */
5885 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
5886 {
5887 /* Set the I2C DMA Abort callback :
5888 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
5889 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
5890
5891 /* Abort DMA TX */
5892 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
5893 {
5894 /* Call Directly XferAbortCallback function in case of error */
5895 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
5896 }
5897 }
5898 }
5899 }
5900
5901 /* All data are not transferred, so set error code accordingly */
5902 if (hi2c->XferCount != 0U)
5903 {
5904 /* Store Last receive data if any */
5905 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
5906 {
5907 /* Read data from DR */
5908 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5909
5910 /* Increment Buffer pointer */
5911 hi2c->pBuffPtr++;
5912
5913 /* Update counter */
5914 hi2c->XferCount--;
5915 }
5916
5917 /* Store Last receive data if any */
5918 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
5919 {
5920 /* Read data from DR */
5921 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5922
5923 /* Increment Buffer pointer */
5924 hi2c->pBuffPtr++;
5925
5926 /* Update counter */
5927 hi2c->XferCount--;
5928 }
5929
5930 if (hi2c->XferCount != 0U)
5931 {
5932 /* Set ErrorCode corresponding to a Non-Acknowledge */
5933 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5934 }
5935 }
5936
5937 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
5938 {
5939 /* Call the corresponding callback to inform upper layer of End of Transfer */
5940 I2C_ITError(hi2c);
5941 }
5942 else
5943 {
5944 if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
5945 {
5946 /* Set state at HAL_I2C_STATE_LISTEN */
5947 hi2c->PreviousState = I2C_STATE_NONE;
5948 hi2c->State = HAL_I2C_STATE_LISTEN;
5949
5950 /* Call the corresponding callback to inform upper layer of End of Transfer */
5951 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5952 hi2c->SlaveRxCpltCallback(hi2c);
5953 #else
5954 HAL_I2C_SlaveRxCpltCallback(hi2c);
5955 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5956 }
5957
5958 if (hi2c->State == HAL_I2C_STATE_LISTEN)
5959 {
5960 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
5961 hi2c->PreviousState = I2C_STATE_NONE;
5962 hi2c->State = HAL_I2C_STATE_READY;
5963 hi2c->Mode = HAL_I2C_MODE_NONE;
5964
5965 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
5966 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5967 hi2c->ListenCpltCallback(hi2c);
5968 #else
5969 HAL_I2C_ListenCpltCallback(hi2c);
5970 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5971 }
5972 else
5973 {
5974 if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
5975 {
5976 hi2c->PreviousState = I2C_STATE_NONE;
5977 hi2c->State = HAL_I2C_STATE_READY;
5978 hi2c->Mode = HAL_I2C_MODE_NONE;
5979
5980 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5981 hi2c->SlaveRxCpltCallback(hi2c);
5982 #else
5983 HAL_I2C_SlaveRxCpltCallback(hi2c);
5984 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5985 }
5986 }
5987 }
5988 }
5989
5990 /**
5991 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5992 * the configuration information for I2C module
5993 * @retval None
5994 */
I2C_Slave_AF(I2C_HandleTypeDef * hi2c)5995 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
5996 {
5997 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5998 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5999 uint32_t CurrentXferOptions = hi2c->XferOptions;
6000
6001 if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
6002 (CurrentState == HAL_I2C_STATE_LISTEN))
6003 {
6004 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6005
6006 /* Disable EVT, BUF and ERR interrupt */
6007 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6008
6009 /* Clear AF flag */
6010 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6011
6012 /* Disable Acknowledge */
6013 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6014
6015 hi2c->PreviousState = I2C_STATE_NONE;
6016 hi2c->State = HAL_I2C_STATE_READY;
6017 hi2c->Mode = HAL_I2C_MODE_NONE;
6018
6019 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6020 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6021 hi2c->ListenCpltCallback(hi2c);
6022 #else
6023 HAL_I2C_ListenCpltCallback(hi2c);
6024 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6025 }
6026 else if (CurrentState == HAL_I2C_STATE_BUSY_TX)
6027 {
6028 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6029 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6030 hi2c->State = HAL_I2C_STATE_READY;
6031 hi2c->Mode = HAL_I2C_MODE_NONE;
6032
6033 /* Disable EVT, BUF and ERR interrupt */
6034 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6035
6036 /* Clear AF flag */
6037 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6038
6039 /* Disable Acknowledge */
6040 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6041
6042 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6043 hi2c->SlaveTxCpltCallback(hi2c);
6044 #else
6045 HAL_I2C_SlaveTxCpltCallback(hi2c);
6046 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6047 }
6048 else
6049 {
6050 /* Clear AF flag only */
6051 /* State Listen, but XferOptions == FIRST or NEXT */
6052 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6053 }
6054 }
6055
6056 /**
6057 * @brief I2C interrupts error process
6058 * @param hi2c I2C handle.
6059 * @retval None
6060 */
I2C_ITError(I2C_HandleTypeDef * hi2c)6061 static void I2C_ITError(I2C_HandleTypeDef *hi2c)
6062 {
6063 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6064 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6065
6066 if ((hi2c->Mode == HAL_I2C_MODE_MASTER) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
6067 {
6068 /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
6069 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
6070 }
6071
6072 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6073 {
6074 /* keep HAL_I2C_STATE_LISTEN */
6075 hi2c->PreviousState = I2C_STATE_NONE;
6076 hi2c->State = HAL_I2C_STATE_LISTEN;
6077 }
6078 else
6079 {
6080 /* If state is an abort treatment on going, don't change state */
6081 /* This change will be do later */
6082 if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT))
6083 {
6084 hi2c->State = HAL_I2C_STATE_READY;
6085 }
6086 hi2c->PreviousState = I2C_STATE_NONE;
6087 hi2c->Mode = HAL_I2C_MODE_NONE;
6088 }
6089
6090 /* Abort DMA transfer */
6091 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
6092 {
6093 hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
6094
6095 if (hi2c->hdmatx->State != HAL_DMA_STATE_READY)
6096 {
6097 /* Set the DMA Abort callback :
6098 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6099 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6100
6101 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6102 {
6103 /* Disable I2C peripheral to prevent dummy data in buffer */
6104 __HAL_I2C_DISABLE(hi2c);
6105
6106 hi2c->State = HAL_I2C_STATE_READY;
6107
6108 /* Call Directly XferAbortCallback function in case of error */
6109 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6110 }
6111 }
6112 else
6113 {
6114 /* Set the DMA Abort callback :
6115 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6116 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6117
6118 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6119 {
6120 /* Store Last receive data if any */
6121 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6122 {
6123 /* Read data from DR */
6124 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6125
6126 /* Increment Buffer pointer */
6127 hi2c->pBuffPtr++;
6128 }
6129
6130 /* Disable I2C peripheral to prevent dummy data in buffer */
6131 __HAL_I2C_DISABLE(hi2c);
6132
6133 hi2c->State = HAL_I2C_STATE_READY;
6134
6135 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6136 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6137 }
6138 }
6139 }
6140 else if (hi2c->State == HAL_I2C_STATE_ABORT)
6141 {
6142 hi2c->State = HAL_I2C_STATE_READY;
6143 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
6144
6145 /* Store Last receive data if any */
6146 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6147 {
6148 /* Read data from DR */
6149 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6150
6151 /* Increment Buffer pointer */
6152 hi2c->pBuffPtr++;
6153 }
6154
6155 /* Disable I2C peripheral to prevent dummy data in buffer */
6156 __HAL_I2C_DISABLE(hi2c);
6157
6158 /* Call the corresponding callback to inform upper layer of End of Transfer */
6159 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6160 hi2c->AbortCpltCallback(hi2c);
6161 #else
6162 HAL_I2C_AbortCpltCallback(hi2c);
6163 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6164 }
6165 else
6166 {
6167 /* Store Last receive data if any */
6168 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6169 {
6170 /* Read data from DR */
6171 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6172
6173 /* Increment Buffer pointer */
6174 hi2c->pBuffPtr++;
6175 }
6176
6177 /* Call user error callback */
6178 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6179 hi2c->ErrorCallback(hi2c);
6180 #else
6181 HAL_I2C_ErrorCallback(hi2c);
6182 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6183 }
6184 /* STOP Flag is not set after a NACK reception */
6185 /* So may inform upper layer that listen phase is stopped */
6186 /* during NACK error treatment */
6187 CurrentState = hi2c->State;
6188 if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))
6189 {
6190 /* Disable EVT, BUF and ERR interrupt */
6191 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6192
6193 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6194 hi2c->PreviousState = I2C_STATE_NONE;
6195 hi2c->State = HAL_I2C_STATE_READY;
6196 hi2c->Mode = HAL_I2C_MODE_NONE;
6197
6198 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6199 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6200 hi2c->ListenCpltCallback(hi2c);
6201 #else
6202 HAL_I2C_ListenCpltCallback(hi2c);
6203 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6204 }
6205 }
6206
6207 /**
6208 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6209 * the configuration information for I2C module
6210 * @param DevAddress Target device address: The device 7 bits address value
6211 * in datasheet must be shifted to the left before calling the interface
6212 * @param Timeout Timeout duration
6213 * @param Tickstart Tick start value
6214 * @retval HAL status
6215 */
I2C_MasterRequestWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Timeout,uint32_t Tickstart)6216 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6217 {
6218 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6219 uint32_t CurrentXferOptions = hi2c->XferOptions;
6220
6221 /* Generate Start condition if first transfer */
6222 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6223 {
6224 /* Generate Start */
6225 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6226 }
6227 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
6228 {
6229 /* Generate ReStart */
6230 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6231 }
6232 else
6233 {
6234 /* Do nothing */
6235 }
6236
6237 /* Wait until SB flag is set */
6238 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6239 {
6240 return HAL_ERROR;
6241 }
6242
6243 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6244 {
6245 /* Send slave address */
6246 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6247 }
6248 else
6249 {
6250 /* Send header of slave address */
6251 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6252
6253 /* Wait until ADD10 flag is set */
6254 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6255 {
6256 return HAL_ERROR;
6257 }
6258
6259 /* Send slave address */
6260 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6261 }
6262
6263 /* Wait until ADDR flag is set */
6264 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6265 {
6266 return HAL_ERROR;
6267 }
6268
6269 return HAL_OK;
6270 }
6271
6272 /**
6273 * @brief Master sends target device address for read request.
6274 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6275 * the configuration information for I2C module
6276 * @param DevAddress Target device address: The device 7 bits address value
6277 * in datasheet must be shifted to the left before calling the interface
6278 * @param Timeout Timeout duration
6279 * @param Tickstart Tick start value
6280 * @retval HAL status
6281 */
I2C_MasterRequestRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Timeout,uint32_t Tickstart)6282 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6283 {
6284 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6285 uint32_t CurrentXferOptions = hi2c->XferOptions;
6286
6287 /* Enable Acknowledge */
6288 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6289
6290 /* Generate Start condition if first transfer */
6291 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6292 {
6293 /* Generate Start */
6294 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6295 }
6296 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
6297 {
6298 /* Generate ReStart */
6299 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6300 }
6301 else
6302 {
6303 /* Do nothing */
6304 }
6305
6306 /* Wait until SB flag is set */
6307 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6308 {
6309 return HAL_ERROR;
6310 }
6311
6312 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6313 {
6314 /* Send slave address */
6315 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
6316 }
6317 else
6318 {
6319 /* Send header of slave address */
6320 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6321
6322 /* Wait until ADD10 flag is set */
6323 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6324 {
6325 return HAL_ERROR;
6326 }
6327
6328 /* Send slave address */
6329 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6330
6331 /* Wait until ADDR flag is set */
6332 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6333 {
6334 return HAL_ERROR;
6335 }
6336
6337 /* Clear ADDR flag */
6338 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6339
6340 /* Generate Restart */
6341 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6342
6343 /* Wait until SB flag is set */
6344 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6345 {
6346 return HAL_ERROR;
6347 }
6348
6349 /* Send header of slave address */
6350 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
6351 }
6352
6353 /* Wait until ADDR flag is set */
6354 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6355 {
6356 return HAL_ERROR;
6357 }
6358
6359 return HAL_OK;
6360 }
6361
6362 /**
6363 * @brief Master sends target device address followed by internal memory address for write request.
6364 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6365 * the configuration information for I2C module
6366 * @param DevAddress Target device address: The device 7 bits address value
6367 * in datasheet must be shifted to the left before calling the interface
6368 * @param MemAddress Internal memory address
6369 * @param MemAddSize Size of internal memory address
6370 * @param Timeout Timeout duration
6371 * @param Tickstart Tick start value
6372 * @retval HAL status
6373 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6374 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6375 {
6376 /* Generate Start */
6377 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6378
6379 /* Wait until SB flag is set */
6380 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6381 {
6382 return HAL_ERROR;
6383 }
6384
6385 /* Send slave address */
6386 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6387
6388 /* Wait until ADDR flag is set */
6389 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6390 {
6391 return HAL_ERROR;
6392 }
6393
6394 /* Clear ADDR flag */
6395 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6396
6397 /* Wait until TXE flag is set */
6398 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6399 {
6400 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6401 {
6402 /* Generate Stop */
6403 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6404 }
6405 return HAL_ERROR;
6406 }
6407
6408 /* If Memory address size is 8Bit */
6409 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6410 {
6411 /* Send Memory Address */
6412 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6413 }
6414 /* If Memory address size is 16Bit */
6415 else
6416 {
6417 /* Send MSB of Memory Address */
6418 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6419
6420 /* Wait until TXE flag is set */
6421 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6422 {
6423 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6424 {
6425 /* Generate Stop */
6426 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6427 }
6428 return HAL_ERROR;
6429 }
6430
6431 /* Send LSB of Memory Address */
6432 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6433 }
6434
6435 return HAL_OK;
6436 }
6437
6438 /**
6439 * @brief Master sends target device address followed by internal memory address for read request.
6440 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6441 * the configuration information for I2C module
6442 * @param DevAddress Target device address: The device 7 bits address value
6443 * in datasheet must be shifted to the left before calling the interface
6444 * @param MemAddress Internal memory address
6445 * @param MemAddSize Size of internal memory address
6446 * @param Timeout Timeout duration
6447 * @param Tickstart Tick start value
6448 * @retval HAL status
6449 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6450 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6451 {
6452 /* Enable Acknowledge */
6453 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6454
6455 /* Generate Start */
6456 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6457
6458 /* Wait until SB flag is set */
6459 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6460 {
6461 return HAL_ERROR;
6462 }
6463
6464 /* Send slave address */
6465 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6466
6467 /* Wait until ADDR flag is set */
6468 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6469 {
6470 return HAL_ERROR;
6471 }
6472
6473 /* Clear ADDR flag */
6474 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6475
6476 /* Wait until TXE flag is set */
6477 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6478 {
6479 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6480 {
6481 /* Generate Stop */
6482 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6483 }
6484 return HAL_ERROR;
6485 }
6486
6487 /* If Memory address size is 8Bit */
6488 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6489 {
6490 /* Send Memory Address */
6491 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6492 }
6493 /* If Memory address size is 16Bit */
6494 else
6495 {
6496 /* Send MSB of Memory Address */
6497 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6498
6499 /* Wait until TXE flag is set */
6500 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6501 {
6502 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6503 {
6504 /* Generate Stop */
6505 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6506 }
6507 return HAL_ERROR;
6508 }
6509
6510 /* Send LSB of Memory Address */
6511 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6512 }
6513
6514 /* Wait until TXE flag is set */
6515 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6516 {
6517 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6518 {
6519 /* Generate Stop */
6520 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6521 }
6522 return HAL_ERROR;
6523 }
6524
6525 /* Generate Restart */
6526 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6527
6528 /* Wait until SB flag is set */
6529 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6530 {
6531 return HAL_ERROR;
6532 }
6533
6534 /* Send slave address */
6535 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
6536
6537 /* Wait until ADDR flag is set */
6538 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6539 {
6540 return HAL_ERROR;
6541 }
6542
6543 return HAL_OK;
6544 }
6545
6546 /**
6547 * @brief DMA I2C process complete callback.
6548 * @param hdma DMA handle
6549 * @retval None
6550 */
I2C_DMAXferCplt(DMA_HandleTypeDef * hdma)6551 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
6552 {
6553 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
6554
6555 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6556 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6557 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
6558 uint32_t CurrentXferOptions = hi2c->XferOptions;
6559
6560 /* Disable EVT and ERR interrupt */
6561 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6562
6563 /* Clear Complete callback */
6564 hi2c->hdmatx->XferCpltCallback = NULL;
6565 hi2c->hdmarx->XferCpltCallback = NULL;
6566
6567 if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
6568 {
6569 /* Disable DMA Request */
6570 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6571
6572 hi2c->XferCount = 0U;
6573
6574 if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)
6575 {
6576 /* Set state at HAL_I2C_STATE_LISTEN */
6577 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6578 hi2c->State = HAL_I2C_STATE_LISTEN;
6579
6580 /* Call the corresponding callback to inform upper layer of End of Transfer */
6581 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6582 hi2c->SlaveTxCpltCallback(hi2c);
6583 #else
6584 HAL_I2C_SlaveTxCpltCallback(hi2c);
6585 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6586 }
6587 else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
6588 {
6589 /* Set state at HAL_I2C_STATE_LISTEN */
6590 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6591 hi2c->State = HAL_I2C_STATE_LISTEN;
6592
6593 /* Call the corresponding callback to inform upper layer of End of Transfer */
6594 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6595 hi2c->SlaveRxCpltCallback(hi2c);
6596 #else
6597 HAL_I2C_SlaveRxCpltCallback(hi2c);
6598 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6599 }
6600 else
6601 {
6602 /* Do nothing */
6603 }
6604
6605 /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */
6606 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6607 }
6608 /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */
6609 else if (hi2c->Mode != HAL_I2C_MODE_NONE)
6610 {
6611 if (hi2c->XferCount == (uint16_t)1)
6612 {
6613 /* Disable Acknowledge */
6614 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6615 }
6616
6617 /* Disable EVT and ERR interrupt */
6618 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6619
6620 /* Prepare next transfer or stop current transfer */
6621 if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
6622 {
6623 /* Generate Stop */
6624 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6625 }
6626
6627 /* Disable Last DMA */
6628 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
6629
6630 /* Disable DMA Request */
6631 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6632
6633 hi2c->XferCount = 0U;
6634
6635 /* Check if Errors has been detected during transfer */
6636 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6637 {
6638 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6639 hi2c->ErrorCallback(hi2c);
6640 #else
6641 HAL_I2C_ErrorCallback(hi2c);
6642 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6643 }
6644 else
6645 {
6646 hi2c->State = HAL_I2C_STATE_READY;
6647
6648 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6649 {
6650 hi2c->Mode = HAL_I2C_MODE_NONE;
6651 hi2c->PreviousState = I2C_STATE_NONE;
6652
6653 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6654 hi2c->MemRxCpltCallback(hi2c);
6655 #else
6656 HAL_I2C_MemRxCpltCallback(hi2c);
6657 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6658 }
6659 else
6660 {
6661 hi2c->Mode = HAL_I2C_MODE_NONE;
6662 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6663
6664 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6665 hi2c->MasterRxCpltCallback(hi2c);
6666 #else
6667 HAL_I2C_MasterRxCpltCallback(hi2c);
6668 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6669 }
6670 }
6671 }
6672 else
6673 {
6674 /* Do nothing */
6675 }
6676 }
6677
6678 /**
6679 * @brief DMA I2C communication error callback.
6680 * @param hdma DMA handle
6681 * @retval None
6682 */
I2C_DMAError(DMA_HandleTypeDef * hdma)6683 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
6684 {
6685 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
6686
6687 /* Clear Complete callback */
6688 hi2c->hdmatx->XferCpltCallback = NULL;
6689 hi2c->hdmarx->XferCpltCallback = NULL;
6690
6691 /* Ignore DMA FIFO error */
6692 if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
6693 {
6694 /* Disable Acknowledge */
6695 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
6696
6697 hi2c->XferCount = 0U;
6698
6699 hi2c->State = HAL_I2C_STATE_READY;
6700 hi2c->Mode = HAL_I2C_MODE_NONE;
6701
6702 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
6703
6704 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6705 hi2c->ErrorCallback(hi2c);
6706 #else
6707 HAL_I2C_ErrorCallback(hi2c);
6708 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6709 }
6710 }
6711
6712 /**
6713 * @brief DMA I2C communication abort callback
6714 * (To be called at end of DMA Abort procedure).
6715 * @param hdma DMA handle.
6716 * @retval None
6717 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)6718 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
6719 {
6720 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
6721
6722 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6723 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6724
6725 /* Clear Complete callback */
6726 hi2c->hdmatx->XferCpltCallback = NULL;
6727 hi2c->hdmarx->XferCpltCallback = NULL;
6728
6729 /* Disable Acknowledge */
6730 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6731
6732 hi2c->XferCount = 0U;
6733
6734 /* Reset XferAbortCallback */
6735 hi2c->hdmatx->XferAbortCallback = NULL;
6736 hi2c->hdmarx->XferAbortCallback = NULL;
6737
6738 /* Disable I2C peripheral to prevent dummy data in buffer */
6739 __HAL_I2C_DISABLE(hi2c);
6740
6741 /* Check if come from abort from user */
6742 if (hi2c->State == HAL_I2C_STATE_ABORT)
6743 {
6744 hi2c->State = HAL_I2C_STATE_READY;
6745 hi2c->Mode = HAL_I2C_MODE_NONE;
6746 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
6747
6748 /* Call the corresponding callback to inform upper layer of End of Transfer */
6749 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6750 hi2c->AbortCpltCallback(hi2c);
6751 #else
6752 HAL_I2C_AbortCpltCallback(hi2c);
6753 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6754 }
6755 else
6756 {
6757 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6758 {
6759 /* Renable I2C peripheral */
6760 __HAL_I2C_ENABLE(hi2c);
6761
6762 /* Enable Acknowledge */
6763 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6764
6765 /* keep HAL_I2C_STATE_LISTEN */
6766 hi2c->PreviousState = I2C_STATE_NONE;
6767 hi2c->State = HAL_I2C_STATE_LISTEN;
6768 }
6769 else
6770 {
6771 hi2c->State = HAL_I2C_STATE_READY;
6772 hi2c->Mode = HAL_I2C_MODE_NONE;
6773 }
6774
6775 /* Call the corresponding callback to inform upper layer of End of Transfer */
6776 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6777 hi2c->ErrorCallback(hi2c);
6778 #else
6779 HAL_I2C_ErrorCallback(hi2c);
6780 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6781 }
6782 }
6783
6784 /**
6785 * @brief This function handles I2C Communication Timeout.
6786 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6787 * the configuration information for I2C module
6788 * @param Flag specifies the I2C flag to check.
6789 * @param Status The new Flag status (SET or RESET).
6790 * @param Timeout Timeout duration
6791 * @param Tickstart Tick start value
6792 * @retval HAL status
6793 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)6794 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
6795 {
6796 /* Wait until flag is set */
6797 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
6798 {
6799 /* Check for the Timeout */
6800 if (Timeout != HAL_MAX_DELAY)
6801 {
6802 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6803 {
6804 hi2c->PreviousState = I2C_STATE_NONE;
6805 hi2c->State = HAL_I2C_STATE_READY;
6806 hi2c->Mode = HAL_I2C_MODE_NONE;
6807 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6808
6809 /* Process Unlocked */
6810 __HAL_UNLOCK(hi2c);
6811
6812 return HAL_ERROR;
6813 }
6814 }
6815 }
6816 return HAL_OK;
6817 }
6818
6819 /**
6820 * @brief This function handles I2C Communication Timeout for Master addressing phase.
6821 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6822 * the configuration information for I2C module
6823 * @param Flag specifies the I2C flag to check.
6824 * @param Timeout Timeout duration
6825 * @param Tickstart Tick start value
6826 * @retval HAL status
6827 */
I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,uint32_t Timeout,uint32_t Tickstart)6828 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
6829 {
6830 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
6831 {
6832 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6833 {
6834 /* Generate Stop */
6835 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6836
6837 /* Clear AF Flag */
6838 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6839
6840 hi2c->PreviousState = I2C_STATE_NONE;
6841 hi2c->State = HAL_I2C_STATE_READY;
6842 hi2c->Mode = HAL_I2C_MODE_NONE;
6843 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6844
6845 /* Process Unlocked */
6846 __HAL_UNLOCK(hi2c);
6847
6848 return HAL_ERROR;
6849 }
6850
6851 /* Check for the Timeout */
6852 if (Timeout != HAL_MAX_DELAY)
6853 {
6854 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6855 {
6856 hi2c->PreviousState = I2C_STATE_NONE;
6857 hi2c->State = HAL_I2C_STATE_READY;
6858 hi2c->Mode = HAL_I2C_MODE_NONE;
6859 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6860
6861 /* Process Unlocked */
6862 __HAL_UNLOCK(hi2c);
6863
6864 return HAL_ERROR;
6865 }
6866 }
6867 }
6868 return HAL_OK;
6869 }
6870
6871 /**
6872 * @brief This function handles I2C Communication Timeout for specific usage of TXE flag.
6873 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6874 * the configuration information for the specified I2C.
6875 * @param Timeout Timeout duration
6876 * @param Tickstart Tick start value
6877 * @retval HAL status
6878 */
I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6879 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
6880 {
6881 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
6882 {
6883 /* Check if a NACK is detected */
6884 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
6885 {
6886 return HAL_ERROR;
6887 }
6888
6889 /* Check for the Timeout */
6890 if (Timeout != HAL_MAX_DELAY)
6891 {
6892 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6893 {
6894 hi2c->PreviousState = I2C_STATE_NONE;
6895 hi2c->State = HAL_I2C_STATE_READY;
6896 hi2c->Mode = HAL_I2C_MODE_NONE;
6897 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6898
6899 /* Process Unlocked */
6900 __HAL_UNLOCK(hi2c);
6901
6902 return HAL_ERROR;
6903 }
6904 }
6905 }
6906 return HAL_OK;
6907 }
6908
6909 /**
6910 * @brief This function handles I2C Communication Timeout for specific usage of BTF flag.
6911 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6912 * the configuration information for the specified I2C.
6913 * @param Timeout Timeout duration
6914 * @param Tickstart Tick start value
6915 * @retval HAL status
6916 */
I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6917 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
6918 {
6919 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
6920 {
6921 /* Check if a NACK is detected */
6922 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
6923 {
6924 return HAL_ERROR;
6925 }
6926
6927 /* Check for the Timeout */
6928 if (Timeout != HAL_MAX_DELAY)
6929 {
6930 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6931 {
6932 hi2c->PreviousState = I2C_STATE_NONE;
6933 hi2c->State = HAL_I2C_STATE_READY;
6934 hi2c->Mode = HAL_I2C_MODE_NONE;
6935 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6936
6937 /* Process Unlocked */
6938 __HAL_UNLOCK(hi2c);
6939
6940 return HAL_ERROR;
6941 }
6942 }
6943 }
6944 return HAL_OK;
6945 }
6946
6947 /**
6948 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
6949 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6950 * the configuration information for the specified I2C.
6951 * @param Timeout Timeout duration
6952 * @param Tickstart Tick start value
6953 * @retval HAL status
6954 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6955 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
6956 {
6957 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
6958 {
6959 /* Check if a NACK is detected */
6960 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
6961 {
6962 return HAL_ERROR;
6963 }
6964
6965 /* Check for the Timeout */
6966 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6967 {
6968 hi2c->PreviousState = I2C_STATE_NONE;
6969 hi2c->State = HAL_I2C_STATE_READY;
6970 hi2c->Mode = HAL_I2C_MODE_NONE;
6971 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6972
6973 /* Process Unlocked */
6974 __HAL_UNLOCK(hi2c);
6975
6976 return HAL_ERROR;
6977 }
6978 }
6979 return HAL_OK;
6980 }
6981
6982 /**
6983 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
6984 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6985 * the configuration information for the specified I2C.
6986 * @param Timeout Timeout duration
6987 * @param Tickstart Tick start value
6988 * @retval HAL status
6989 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6990 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
6991 {
6992
6993 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
6994 {
6995 /* Check if a STOPF is detected */
6996 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6997 {
6998 /* Clear STOP Flag */
6999 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7000
7001 hi2c->PreviousState = I2C_STATE_NONE;
7002 hi2c->State = HAL_I2C_STATE_READY;
7003 hi2c->Mode = HAL_I2C_MODE_NONE;
7004 hi2c->ErrorCode |= HAL_I2C_ERROR_NONE;
7005
7006 /* Process Unlocked */
7007 __HAL_UNLOCK(hi2c);
7008
7009 return HAL_ERROR;
7010 }
7011
7012 /* Check for the Timeout */
7013 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7014 {
7015 hi2c->PreviousState = I2C_STATE_NONE;
7016 hi2c->State = HAL_I2C_STATE_READY;
7017 hi2c->Mode = HAL_I2C_MODE_NONE;
7018 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7019
7020 /* Process Unlocked */
7021 __HAL_UNLOCK(hi2c);
7022
7023 return HAL_ERROR;
7024 }
7025 }
7026 return HAL_OK;
7027 }
7028
7029 /**
7030 * @brief This function handles Acknowledge failed detection during an I2C Communication.
7031 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7032 * the configuration information for the specified I2C.
7033 * @retval HAL status
7034 */
I2C_IsAcknowledgeFailed(I2C_HandleTypeDef * hi2c)7035 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
7036 {
7037 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7038 {
7039 /* Clear NACKF Flag */
7040 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7041
7042 hi2c->PreviousState = I2C_STATE_NONE;
7043 hi2c->State = HAL_I2C_STATE_READY;
7044 hi2c->Mode = HAL_I2C_MODE_NONE;
7045 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
7046
7047 /* Process Unlocked */
7048 __HAL_UNLOCK(hi2c);
7049
7050 return HAL_ERROR;
7051 }
7052 return HAL_OK;
7053 }
7054
7055 /**
7056 * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
7057 * @param hi2c I2C handle.
7058 * @retval None
7059 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7060 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7061 {
7062 /* if user set XferOptions to I2C_OTHER_FRAME */
7063 /* it request implicitly to generate a restart condition */
7064 /* set XferOptions to I2C_FIRST_FRAME */
7065 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7066 {
7067 hi2c->XferOptions = I2C_FIRST_FRAME;
7068 }
7069 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7070 /* it request implicitly to generate a restart condition */
7071 /* then generate a stop condition at the end of transfer */
7072 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7073 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7074 {
7075 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7076 }
7077 else
7078 {
7079 /* Nothing to do */
7080 }
7081 }
7082
7083 /**
7084 * @}
7085 */
7086
7087 #endif /* HAL_I2C_MODULE_ENABLED */
7088 /**
7089 * @}
7090 */
7091
7092 /**
7093 * @}
7094 */
7095
7096 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
7097