1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_rcc.c
4 * @author MCD Application Team
5 * @brief RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Reset and Clock Control (RCC) peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### RCC specific features #####
14 ==============================================================================
15 [..]
16 After reset the device is running from Internal High Speed oscillator
17 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
18 and I-Cache are disabled, and all peripherals are off except internal
19 SRAM, Flash and JTAG.
20 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
21 all peripherals mapped on these busses are running at HSI speed.
22 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
23 (+) All GPIOs are in input floating state, except the JTAG pins which
24 are assigned to be used for debug purpose.
25
26 [..]
27 Once the device started from reset, the user application has to:
28 (+) Configure the clock source to be used to drive the System clock
29 (if the application needs higher frequency/performance)
30 (+) Configure the System clock frequency and Flash settings
31 (+) Configure the AHB and APB busses prescalers
32 (+) Enable the clock for the peripheral(s) to be used
33 (+) Configure the clock source(s) for peripherals which clocks are not
34 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
35
36 ##### RCC Limitations #####
37 ==============================================================================
38 [..]
39 A delay between an RCC peripheral clock enable and the effective peripheral
40 enabling should be taken into account in order to manage the peripheral read/write
41 from/to registers.
42 (+) This delay depends on the peripheral mapping.
43 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
44 after the clock enable bit is set on the hardware register
45 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
46 after the clock enable bit is set on the hardware register
47
48 [..]
49 Implemented Workaround:
50 (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
51 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
52
53 @endverbatim
54 ******************************************************************************
55 * @attention
56 *
57 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
58 * All rights reserved.</center></h2>
59 *
60 * This software component is licensed by ST under BSD 3-Clause license,
61 * the "License"; You may not use this file except in compliance with the
62 * License. You may obtain a copy of the License at:
63 * opensource.org/licenses/BSD-3-Clause
64 *
65 ******************************************************************************
66 */
67
68 /* Includes ------------------------------------------------------------------*/
69 #include "stm32f4xx_hal.h"
70
71 /** @addtogroup STM32F4xx_HAL_Driver
72 * @{
73 */
74
75 /** @defgroup RCC RCC
76 * @brief RCC HAL module driver
77 * @{
78 */
79
80 #ifdef HAL_RCC_MODULE_ENABLED
81
82 /* Private typedef -----------------------------------------------------------*/
83 /* Private define ------------------------------------------------------------*/
84 /** @addtogroup RCC_Private_Constants
85 * @{
86 */
87
88 /* Private macro -------------------------------------------------------------*/
89 #define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
90 #define MCO1_GPIO_PORT GPIOA
91 #define MCO1_PIN GPIO_PIN_8
92
93 #define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
94 #define MCO2_GPIO_PORT GPIOC
95 #define MCO2_PIN GPIO_PIN_9
96 /**
97 * @}
98 */
99
100 /* Private variables ---------------------------------------------------------*/
101 /** @defgroup RCC_Private_Variables RCC Private Variables
102 * @{
103 */
104 /**
105 * @}
106 */
107 /* Private function prototypes -----------------------------------------------*/
108 /* Private functions ---------------------------------------------------------*/
109
110 /** @defgroup RCC_Exported_Functions RCC Exported Functions
111 * @{
112 */
113
114 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
115 * @brief Initialization and Configuration functions
116 *
117 @verbatim
118 ===============================================================================
119 ##### Initialization and de-initialization functions #####
120 ===============================================================================
121 [..]
122 This section provides functions allowing to configure the internal/external oscillators
123 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
124 and APB2).
125
126 [..] Internal/external clock and PLL configuration
127 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
128 the PLL as System clock source.
129
130 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
131 clock source.
132
133 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
134 through the PLL as System clock source. Can be used also as RTC clock source.
135
136 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
137
138 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
139 (++) The first output is used to generate the high speed system clock (up to 168 MHz)
140 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
141 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
142
143 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
144 and if a HSE clock failure occurs(HSE used directly or through PLL as System
145 clock source), the System clocks automatically switched to HSI and an interrupt
146 is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
147 (Non-Maskable Interrupt) exception vector.
148
149 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
150 clock (through a configurable prescaler) on PA8 pin.
151
152 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
153 clock (through a configurable prescaler) on PC9 pin.
154
155 [..] System, AHB and APB busses clocks configuration
156 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
157 HSE and PLL.
158 The AHB clock (HCLK) is derived from System clock through configurable
159 prescaler and used to clock the CPU, memory and peripherals mapped
160 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
161 from AHB clock through configurable prescalers and used to clock
162 the peripherals mapped on these busses. You can use
163 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
164
165 (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
166 frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
167 Depending on the device voltage range, the maximum frequency should
168 be adapted accordingly (refer to the product datasheets for more details).
169
170 (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,
171 the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
172 Depending on the device voltage range, the maximum frequency should
173 be adapted accordingly (refer to the product datasheets for more details).
174
175 (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
176 PCLK2 84 MHz and PCLK1 42 MHz.
177 Depending on the device voltage range, the maximum frequency should
178 be adapted accordingly (refer to the product datasheets for more details).
179
180 (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
181 PCLK2 100 MHz and PCLK1 50 MHz.
182 Depending on the device voltage range, the maximum frequency should
183 be adapted accordingly (refer to the product datasheets for more details).
184
185 @endverbatim
186 * @{
187 */
188
189 /**
190 * @brief Resets the RCC clock configuration to the default reset state.
191 * @note The default reset state of the clock configuration is given below:
192 * - HSI ON and used as system clock source
193 * - HSE and PLL OFF
194 * - AHB, APB1 and APB2 prescaler set to 1.
195 * - CSS, MCO1 and MCO2 OFF
196 * - All interrupts disabled
197 * @note This function doesn't modify the configuration of the
198 * - Peripheral clocks
199 * - LSI, LSE and RTC clocks
200 * @retval HAL status
201 */
HAL_RCC_DeInit(void)202 __weak HAL_StatusTypeDef HAL_RCC_DeInit(void)
203 {
204 return HAL_OK;
205 }
206
207 /**
208 * @brief Initializes the RCC Oscillators according to the specified parameters in the
209 * RCC_OscInitTypeDef.
210 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
211 * contains the configuration information for the RCC Oscillators.
212 * @note The PLL is not disabled when used as system clock.
213 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
214 * supported by this API. User should request a transition to LSE Off
215 * first and then LSE On or LSE Bypass.
216 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
217 * supported by this API. User should request a transition to HSE Off
218 * first and then HSE On or HSE Bypass.
219 * @retval HAL status
220 */
HAL_RCC_OscConfig(RCC_OscInitTypeDef * RCC_OscInitStruct)221 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
222 {
223 uint32_t tickstart;
224
225 /* Check Null pointer */
226 if(RCC_OscInitStruct == NULL)
227 {
228 return HAL_ERROR;
229 }
230
231 /* Check the parameters */
232 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
233 /*------------------------------- HSE Configuration ------------------------*/
234 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
235 {
236 /* Check the parameters */
237 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
238 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
239 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
240 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
241 {
242 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
243 {
244 return HAL_ERROR;
245 }
246 }
247 else
248 {
249 /* Set the new HSE configuration ---------------------------------------*/
250 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
251
252 /* Check the HSE State */
253 if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
254 {
255 /* Get Start Tick */
256 tickstart = HAL_GetTick();
257
258 /* Wait till HSE is ready */
259 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
260 {
261 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
262 {
263 return HAL_TIMEOUT;
264 }
265 }
266 }
267 else
268 {
269 /* Get Start Tick */
270 tickstart = HAL_GetTick();
271
272 /* Wait till HSE is bypassed or disabled */
273 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
274 {
275 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
276 {
277 return HAL_TIMEOUT;
278 }
279 }
280 }
281 }
282 }
283 /*----------------------------- HSI Configuration --------------------------*/
284 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
285 {
286 /* Check the parameters */
287 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
288 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
289
290 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
291 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
292 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
293 {
294 /* When HSI is used as system clock it will not disabled */
295 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
296 {
297 return HAL_ERROR;
298 }
299 /* Otherwise, just the calibration is allowed */
300 else
301 {
302 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
303 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
304 }
305 }
306 else
307 {
308 /* Check the HSI State */
309 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
310 {
311 /* Enable the Internal High Speed oscillator (HSI). */
312 __HAL_RCC_HSI_ENABLE();
313
314 /* Get Start Tick*/
315 tickstart = HAL_GetTick();
316
317 /* Wait till HSI is ready */
318 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
319 {
320 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
321 {
322 return HAL_TIMEOUT;
323 }
324 }
325
326 /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
327 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
328 }
329 else
330 {
331 /* Disable the Internal High Speed oscillator (HSI). */
332 __HAL_RCC_HSI_DISABLE();
333
334 /* Get Start Tick*/
335 tickstart = HAL_GetTick();
336
337 /* Wait till HSI is ready */
338 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
339 {
340 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
341 {
342 return HAL_TIMEOUT;
343 }
344 }
345 }
346 }
347 }
348 /*------------------------------ LSI Configuration -------------------------*/
349 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
350 {
351 /* Check the parameters */
352 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
353
354 /* Check the LSI State */
355 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
356 {
357 /* Enable the Internal Low Speed oscillator (LSI). */
358 __HAL_RCC_LSI_ENABLE();
359
360 /* Get Start Tick*/
361 tickstart = HAL_GetTick();
362
363 /* Wait till LSI is ready */
364 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
365 {
366 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
367 {
368 return HAL_TIMEOUT;
369 }
370 }
371 }
372 else
373 {
374 /* Disable the Internal Low Speed oscillator (LSI). */
375 __HAL_RCC_LSI_DISABLE();
376
377 /* Get Start Tick */
378 tickstart = HAL_GetTick();
379
380 /* Wait till LSI is ready */
381 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
382 {
383 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
384 {
385 return HAL_TIMEOUT;
386 }
387 }
388 }
389 }
390 /*------------------------------ LSE Configuration -------------------------*/
391 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
392 {
393 FlagStatus pwrclkchanged = RESET;
394
395 /* Check the parameters */
396 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
397
398 /* Update LSE configuration in Backup Domain control register */
399 /* Requires to enable write access to Backup Domain of necessary */
400 if(__HAL_RCC_PWR_IS_CLK_DISABLED())
401 {
402 __HAL_RCC_PWR_CLK_ENABLE();
403 pwrclkchanged = SET;
404 }
405
406 if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
407 {
408 /* Enable write access to Backup domain */
409 SET_BIT(PWR->CR, PWR_CR_DBP);
410
411 /* Wait for Backup domain Write protection disable */
412 tickstart = HAL_GetTick();
413
414 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
415 {
416 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
417 {
418 return HAL_TIMEOUT;
419 }
420 }
421 }
422
423 /* Set the new LSE configuration -----------------------------------------*/
424 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
425 /* Check the LSE State */
426 if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
427 {
428 /* Get Start Tick*/
429 tickstart = HAL_GetTick();
430
431 /* Wait till LSE is ready */
432 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
433 {
434 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
435 {
436 return HAL_TIMEOUT;
437 }
438 }
439 }
440 else
441 {
442 /* Get Start Tick */
443 tickstart = HAL_GetTick();
444
445 /* Wait till LSE is ready */
446 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
447 {
448 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
449 {
450 return HAL_TIMEOUT;
451 }
452 }
453 }
454
455 /* Restore clock configuration if changed */
456 if(pwrclkchanged == SET)
457 {
458 __HAL_RCC_PWR_CLK_DISABLE();
459 }
460 }
461 /*-------------------------------- PLL Configuration -----------------------*/
462 /* Check the parameters */
463 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
464 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
465 {
466 /* Check if the PLL is used as system clock or not */
467 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
468 {
469 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
470 {
471 /* Check the parameters */
472 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
473 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
474 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
475 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
476 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
477
478 /* Disable the main PLL. */
479 __HAL_RCC_PLL_DISABLE();
480
481 /* Get Start Tick */
482 tickstart = HAL_GetTick();
483
484 /* Wait till PLL is ready */
485 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
486 {
487 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
488 {
489 return HAL_TIMEOUT;
490 }
491 }
492
493 /* Configure the main PLL clock source, multiplication and division factors. */
494 WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
495 RCC_OscInitStruct->PLL.PLLM | \
496 (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
497 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
498 (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
499 /* Enable the main PLL. */
500 __HAL_RCC_PLL_ENABLE();
501
502 /* Get Start Tick */
503 tickstart = HAL_GetTick();
504
505 /* Wait till PLL is ready */
506 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
507 {
508 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
509 {
510 return HAL_TIMEOUT;
511 }
512 }
513 }
514 else
515 {
516 /* Disable the main PLL. */
517 __HAL_RCC_PLL_DISABLE();
518
519 /* Get Start Tick */
520 tickstart = HAL_GetTick();
521
522 /* Wait till PLL is ready */
523 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
524 {
525 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
526 {
527 return HAL_TIMEOUT;
528 }
529 }
530 }
531 }
532 else
533 {
534 return HAL_ERROR;
535 }
536 }
537 return HAL_OK;
538 }
539
540 /**
541 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
542 * parameters in the RCC_ClkInitStruct.
543 * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
544 * contains the configuration information for the RCC peripheral.
545 * @param FLatency FLASH Latency, this parameter depend on device selected
546 *
547 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
548 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
549 *
550 * @note The HSI is used (enabled by hardware) as system clock source after
551 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
552 * of failure of the HSE used directly or indirectly as system clock
553 * (if the Clock Security System CSS is enabled).
554 *
555 * @note A switch from one clock source to another occurs only if the target
556 * clock source is ready (clock stable after startup delay or PLL locked).
557 * If a clock source which is not yet ready is selected, the switch will
558 * occur when the clock source will be ready.
559 *
560 * @note Depending on the device voltage range, the software has to set correctly
561 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
562 * (for more details refer to section above "Initialization/de-initialization functions")
563 * @retval None
564 */
HAL_RCC_ClockConfig(RCC_ClkInitTypeDef * RCC_ClkInitStruct,uint32_t FLatency)565 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
566 {
567 uint32_t tickstart;
568
569 /* Check Null pointer */
570 if(RCC_ClkInitStruct == NULL)
571 {
572 return HAL_ERROR;
573 }
574
575 /* Check the parameters */
576 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
577 assert_param(IS_FLASH_LATENCY(FLatency));
578
579 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
580 must be correctly programmed according to the frequency of the CPU clock
581 (HCLK) and the supply voltage of the device. */
582
583 /* Increasing the number of wait states because of higher CPU frequency */
584 if(FLatency > __HAL_FLASH_GET_LATENCY())
585 {
586 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
587 __HAL_FLASH_SET_LATENCY(FLatency);
588
589 /* Check that the new number of wait states is taken into account to access the Flash
590 memory by reading the FLASH_ACR register */
591 if(__HAL_FLASH_GET_LATENCY() != FLatency)
592 {
593 return HAL_ERROR;
594 }
595 }
596
597 /*-------------------------- HCLK Configuration --------------------------*/
598 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
599 {
600 /* Set the highest APBx dividers in order to ensure that we do not go through
601 a non-spec phase whatever we decrease or increase HCLK. */
602 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
603 {
604 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
605 }
606
607 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
608 {
609 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
610 }
611
612 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
613 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
614 }
615
616 /*------------------------- SYSCLK Configuration ---------------------------*/
617 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
618 {
619 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
620
621 /* HSE is selected as System Clock Source */
622 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
623 {
624 /* Check the HSE ready flag */
625 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
626 {
627 return HAL_ERROR;
628 }
629 }
630 /* PLL is selected as System Clock Source */
631 else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
632 (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
633 {
634 /* Check the PLL ready flag */
635 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
636 {
637 return HAL_ERROR;
638 }
639 }
640 /* HSI is selected as System Clock Source */
641 else
642 {
643 /* Check the HSI ready flag */
644 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
645 {
646 return HAL_ERROR;
647 }
648 }
649
650 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
651
652 /* Get Start Tick */
653 tickstart = HAL_GetTick();
654
655 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
656 {
657 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
658 {
659 return HAL_TIMEOUT;
660 }
661 }
662 }
663
664 /* Decreasing the number of wait states because of lower CPU frequency */
665 if(FLatency < __HAL_FLASH_GET_LATENCY())
666 {
667 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
668 __HAL_FLASH_SET_LATENCY(FLatency);
669
670 /* Check that the new number of wait states is taken into account to access the Flash
671 memory by reading the FLASH_ACR register */
672 if(__HAL_FLASH_GET_LATENCY() != FLatency)
673 {
674 return HAL_ERROR;
675 }
676 }
677
678 /*-------------------------- PCLK1 Configuration ---------------------------*/
679 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
680 {
681 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
682 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
683 }
684
685 /*-------------------------- PCLK2 Configuration ---------------------------*/
686 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
687 {
688 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
689 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
690 }
691
692 /* Update the SystemCoreClock global variable */
693 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
694
695 /* Configure the source of time base considering new system clocks settings */
696 HAL_InitTick (TICK_INT_PRIORITY);
697
698 return HAL_OK;
699 }
700
701 /**
702 * @}
703 */
704
705 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
706 * @brief RCC clocks control functions
707 *
708 @verbatim
709 ===============================================================================
710 ##### Peripheral Control functions #####
711 ===============================================================================
712 [..]
713 This subsection provides a set of functions allowing to control the RCC Clocks
714 frequencies.
715
716 @endverbatim
717 * @{
718 */
719
720 /**
721 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
722 * @note PA8/PC9 should be configured in alternate function mode.
723 * @param RCC_MCOx specifies the output direction for the clock source.
724 * This parameter can be one of the following values:
725 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
726 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
727 * @param RCC_MCOSource specifies the clock source to output.
728 * This parameter can be one of the following values:
729 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
730 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
731 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
732 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
733 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
734 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
735 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
736 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
737 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
738 * @param RCC_MCODiv specifies the MCOx prescaler.
739 * This parameter can be one of the following values:
740 * @arg RCC_MCODIV_1: no division applied to MCOx clock
741 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
742 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
743 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
744 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
745 * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
746 * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
747 * @retval None
748 */
HAL_RCC_MCOConfig(uint32_t RCC_MCOx,uint32_t RCC_MCOSource,uint32_t RCC_MCODiv)749 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
750 {
751 GPIO_InitTypeDef GPIO_InitStruct;
752 /* Check the parameters */
753 assert_param(IS_RCC_MCO(RCC_MCOx));
754 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
755 /* RCC_MCO1 */
756 if(RCC_MCOx == RCC_MCO1)
757 {
758 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
759
760 /* MCO1 Clock Enable */
761 __MCO1_CLK_ENABLE();
762
763 /* Configure the MCO1 pin in alternate function mode */
764 GPIO_InitStruct.Pin = MCO1_PIN;
765 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
766 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
767 GPIO_InitStruct.Pull = GPIO_NOPULL;
768 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
769 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
770
771 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
772 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
773
774 /* This RCC MCO1 enable feature is available only on STM32F410xx devices */
775 #if defined(RCC_CFGR_MCO1EN)
776 __HAL_RCC_MCO1_ENABLE();
777 #endif /* RCC_CFGR_MCO1EN */
778 }
779 #if defined(RCC_CFGR_MCO2)
780 else
781 {
782 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
783
784 /* MCO2 Clock Enable */
785 __MCO2_CLK_ENABLE();
786
787 /* Configure the MCO2 pin in alternate function mode */
788 GPIO_InitStruct.Pin = MCO2_PIN;
789 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
790 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
791 GPIO_InitStruct.Pull = GPIO_NOPULL;
792 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
793 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
794
795 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
796 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
797
798 /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
799 #if defined(RCC_CFGR_MCO2EN)
800 __HAL_RCC_MCO2_ENABLE();
801 #endif /* RCC_CFGR_MCO2EN */
802 }
803 #endif /* RCC_CFGR_MCO2 */
804 }
805
806 /**
807 * @brief Enables the Clock Security System.
808 * @note If a failure is detected on the HSE oscillator clock, this oscillator
809 * is automatically disabled and an interrupt is generated to inform the
810 * software about the failure (Clock Security System Interrupt, CSSI),
811 * allowing the MCU to perform rescue operations. The CSSI is linked to
812 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
813 * @retval None
814 */
HAL_RCC_EnableCSS(void)815 void HAL_RCC_EnableCSS(void)
816 {
817 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
818 }
819
820 /**
821 * @brief Disables the Clock Security System.
822 * @retval None
823 */
HAL_RCC_DisableCSS(void)824 void HAL_RCC_DisableCSS(void)
825 {
826 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
827 }
828
829 /**
830 * @brief Returns the SYSCLK frequency
831 *
832 * @note The system frequency computed by this function is not the real
833 * frequency in the chip. It is calculated based on the predefined
834 * constant and the selected clock source:
835 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
836 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
837 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
838 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
839 * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
840 * 16 MHz) but the real value may vary depending on the variations
841 * in voltage and temperature.
842 * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
843 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
844 * frequency of the crystal used. Otherwise, this function may
845 * have wrong result.
846 *
847 * @note The result of this function could be not correct when using fractional
848 * value for HSE crystal.
849 *
850 * @note This function can be used by the user application to compute the
851 * baudrate for the communication peripherals or configure other parameters.
852 *
853 * @note Each time SYSCLK changes, this function must be called to update the
854 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
855 *
856 *
857 * @retval SYSCLK frequency
858 */
HAL_RCC_GetSysClockFreq(void)859 __weak uint32_t HAL_RCC_GetSysClockFreq(void)
860 {
861 uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
862 uint32_t sysclockfreq = 0U;
863
864 /* Get SYSCLK source -------------------------------------------------------*/
865 switch (RCC->CFGR & RCC_CFGR_SWS)
866 {
867 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
868 {
869 sysclockfreq = HSI_VALUE;
870 break;
871 }
872 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
873 {
874 sysclockfreq = HSE_VALUE;
875 break;
876 }
877 case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
878 {
879 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
880 SYSCLK = PLL_VCO / PLLP */
881 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
882 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
883 {
884 /* HSE used as PLL clock source */
885 pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
886 }
887 else
888 {
889 /* HSI used as PLL clock source */
890 pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
891 }
892 pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
893
894 sysclockfreq = pllvco/pllp;
895 break;
896 }
897 default:
898 {
899 sysclockfreq = HSI_VALUE;
900 break;
901 }
902 }
903 return sysclockfreq;
904 }
905
906 /**
907 * @brief Returns the HCLK frequency
908 * @note Each time HCLK changes, this function must be called to update the
909 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
910 *
911 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
912 * and updated within this function
913 * @retval HCLK frequency
914 */
HAL_RCC_GetHCLKFreq(void)915 uint32_t HAL_RCC_GetHCLKFreq(void)
916 {
917 return SystemCoreClock;
918 }
919
920 /**
921 * @brief Returns the PCLK1 frequency
922 * @note Each time PCLK1 changes, this function must be called to update the
923 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
924 * @retval PCLK1 frequency
925 */
HAL_RCC_GetPCLK1Freq(void)926 uint32_t HAL_RCC_GetPCLK1Freq(void)
927 {
928 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
929 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
930 }
931
932 /**
933 * @brief Returns the PCLK2 frequency
934 * @note Each time PCLK2 changes, this function must be called to update the
935 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
936 * @retval PCLK2 frequency
937 */
HAL_RCC_GetPCLK2Freq(void)938 uint32_t HAL_RCC_GetPCLK2Freq(void)
939 {
940 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
941 return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
942 }
943
944 /**
945 * @brief Configures the RCC_OscInitStruct according to the internal
946 * RCC configuration registers.
947 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
948 * will be configured.
949 * @retval None
950 */
HAL_RCC_GetOscConfig(RCC_OscInitTypeDef * RCC_OscInitStruct)951 __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
952 {
953 /* Set all possible values for the Oscillator type parameter ---------------*/
954 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
955
956 /* Get the HSE configuration -----------------------------------------------*/
957 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
958 {
959 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
960 }
961 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
962 {
963 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
964 }
965 else
966 {
967 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
968 }
969
970 /* Get the HSI configuration -----------------------------------------------*/
971 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
972 {
973 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
974 }
975 else
976 {
977 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
978 }
979
980 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
981
982 /* Get the LSE configuration -----------------------------------------------*/
983 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
984 {
985 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
986 }
987 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
988 {
989 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
990 }
991 else
992 {
993 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
994 }
995
996 /* Get the LSI configuration -----------------------------------------------*/
997 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
998 {
999 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
1000 }
1001 else
1002 {
1003 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
1004 }
1005
1006 /* Get the PLL configuration -----------------------------------------------*/
1007 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
1008 {
1009 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
1010 }
1011 else
1012 {
1013 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
1014 }
1015 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
1016 RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
1017 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
1018 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);
1019 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
1020 }
1021
1022 /**
1023 * @brief Configures the RCC_ClkInitStruct according to the internal
1024 * RCC configuration registers.
1025 * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
1026 * will be configured.
1027 * @param pFLatency Pointer on the Flash Latency.
1028 * @retval None
1029 */
HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef * RCC_ClkInitStruct,uint32_t * pFLatency)1030 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
1031 {
1032 /* Set all possible values for the Clock type parameter --------------------*/
1033 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
1034
1035 /* Get the SYSCLK configuration --------------------------------------------*/
1036 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
1037
1038 /* Get the HCLK configuration ----------------------------------------------*/
1039 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
1040
1041 /* Get the APB1 configuration ----------------------------------------------*/
1042 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
1043
1044 /* Get the APB2 configuration ----------------------------------------------*/
1045 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
1046
1047 /* Get the Flash Wait State (Latency) configuration ------------------------*/
1048 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
1049 }
1050
1051 /**
1052 * @brief This function handles the RCC CSS interrupt request.
1053 * @note This API should be called under the NMI_Handler().
1054 * @retval None
1055 */
HAL_RCC_NMI_IRQHandler(void)1056 void HAL_RCC_NMI_IRQHandler(void)
1057 {
1058 /* Check RCC CSSF flag */
1059 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
1060 {
1061 /* RCC Clock Security System interrupt user callback */
1062 HAL_RCC_CSSCallback();
1063
1064 /* Clear RCC CSS pending bit */
1065 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
1066 }
1067 }
1068
1069 /**
1070 * @brief RCC Clock Security System interrupt callback
1071 * @retval None
1072 */
HAL_RCC_CSSCallback(void)1073 __weak void HAL_RCC_CSSCallback(void)
1074 {
1075 /* NOTE : This function Should not be modified, when the callback is needed,
1076 the HAL_RCC_CSSCallback could be implemented in the user file
1077 */
1078 }
1079
1080 /**
1081 * @}
1082 */
1083
1084 /**
1085 * @}
1086 */
1087
1088 #endif /* HAL_RCC_MODULE_ENABLED */
1089 /**
1090 * @}
1091 */
1092
1093 /**
1094 * @}
1095 */
1096
1097 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1098