1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_utils.c
4 * @author MCD Application Team
5 * @brief UTILS LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32f4xx_ll_utils.h"
21 #include "stm32f4xx_ll_rcc.h"
22 #include "stm32f4xx_ll_system.h"
23 #include "stm32f4xx_ll_pwr.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32F4xx_LL_Driver
31 * @{
32 */
33
34 /** @addtogroup UTILS_LL
35 * @{
36 */
37
38 /* Private types -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /* Private constants ---------------------------------------------------------*/
41 /** @addtogroup UTILS_LL_Private_Constants
42 * @{
43 */
44 #if defined(RCC_MAX_FREQUENCY_SCALE1)
45 #define UTILS_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
46 #endif /*RCC_MAX_FREQUENCY_SCALE1 */
47 #define UTILS_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY_SCALE2 /*!< Maximum frequency for system clock at power scale2, in Hz */
48 #if defined(RCC_MAX_FREQUENCY_SCALE3)
49 #define UTILS_MAX_FREQUENCY_SCALE3 RCC_MAX_FREQUENCY_SCALE3 /*!< Maximum frequency for system clock at power scale3, in Hz */
50 #endif /* MAX_FREQUENCY_SCALE3 */
51
52 /* Defines used for PLL range */
53 #define UTILS_PLLVCO_INPUT_MIN RCC_PLLVCO_INPUT_MIN /*!< Frequency min for PLLVCO input, in Hz */
54 #define UTILS_PLLVCO_INPUT_MAX RCC_PLLVCO_INPUT_MAX /*!< Frequency max for PLLVCO input, in Hz */
55 #define UTILS_PLLVCO_OUTPUT_MIN RCC_PLLVCO_OUTPUT_MIN /*!< Frequency min for PLLVCO output, in Hz */
56 #define UTILS_PLLVCO_OUTPUT_MAX RCC_PLLVCO_OUTPUT_MAX /*!< Frequency max for PLLVCO output, in Hz */
57
58 /* Defines used for HSE range */
59 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
60 #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
61
62 /* Defines used for FLASH latency according to HCLK Frequency */
63 #if defined(FLASH_SCALE1_LATENCY1_FREQ)
64 #define UTILS_SCALE1_LATENCY1_FREQ FLASH_SCALE1_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
65 #endif
66 #if defined(FLASH_SCALE1_LATENCY2_FREQ)
67 #define UTILS_SCALE1_LATENCY2_FREQ FLASH_SCALE1_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
68 #endif
69 #if defined(FLASH_SCALE1_LATENCY3_FREQ)
70 #define UTILS_SCALE1_LATENCY3_FREQ FLASH_SCALE1_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
71 #endif
72 #if defined(FLASH_SCALE1_LATENCY4_FREQ)
73 #define UTILS_SCALE1_LATENCY4_FREQ FLASH_SCALE1_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
74 #endif
75 #if defined(FLASH_SCALE1_LATENCY5_FREQ)
76 #define UTILS_SCALE1_LATENCY5_FREQ FLASH_SCALE1_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
77 #endif
78 #define UTILS_SCALE2_LATENCY1_FREQ FLASH_SCALE2_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
79 #define UTILS_SCALE2_LATENCY2_FREQ FLASH_SCALE2_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
80 #if defined(FLASH_SCALE2_LATENCY3_FREQ)
81 #define UTILS_SCALE2_LATENCY3_FREQ FLASH_SCALE2_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
82 #endif
83 #if defined(FLASH_SCALE2_LATENCY4_FREQ)
84 #define UTILS_SCALE2_LATENCY4_FREQ FLASH_SCALE2_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
85 #endif
86 #if defined(FLASH_SCALE2_LATENCY5_FREQ)
87 #define UTILS_SCALE2_LATENCY5_FREQ FLASH_SCALE2_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
88 #endif
89 #if defined(FLASH_SCALE3_LATENCY1_FREQ)
90 #define UTILS_SCALE3_LATENCY1_FREQ FLASH_SCALE3_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
91 #endif
92 #if defined(FLASH_SCALE3_LATENCY2_FREQ)
93 #define UTILS_SCALE3_LATENCY2_FREQ FLASH_SCALE3_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
94 #endif
95 #if defined(FLASH_SCALE3_LATENCY3_FREQ)
96 #define UTILS_SCALE3_LATENCY3_FREQ FLASH_SCALE3_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
97 #endif
98 #if defined(FLASH_SCALE3_LATENCY4_FREQ)
99 #define UTILS_SCALE3_LATENCY4_FREQ FLASH_SCALE3_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
100 #endif
101 #if defined(FLASH_SCALE3_LATENCY5_FREQ)
102 #define UTILS_SCALE3_LATENCY5_FREQ FLASH_SCALE3_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 3 */
103 #endif
104 /**
105 * @}
106 */
107
108 /* Private macros ------------------------------------------------------------*/
109 /** @addtogroup UTILS_LL_Private_Macros
110 * @{
111 */
112 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
113 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
114 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
115 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
116 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
117 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
118 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
119 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
120 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
121
122 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
123 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
124 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
125 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
126 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
127
128 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
129 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
130 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
131 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
132 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
133
134 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
135 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
136 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
137 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
138 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
139 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
140 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
141 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
142 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
143 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
144 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
145 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
146 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
147 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
148 || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
149 || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
150 || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
151 || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
152 || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
153 || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
154 || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
155 || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
156 || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
157 || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
158 || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
159 || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
160 || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
161 || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
162 || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
163 || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
164 || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
165 || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
166 || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
167 || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
168 || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
169 || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
170 || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
171 || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
172 || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
173 || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
174 || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
175 || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
176 || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
177 || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
178 || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
179 || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
180 || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
181 || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
182 || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
183 || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
184 || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
185 || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
186 || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
187 || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
188 || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
189 || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
190 || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
191 || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
192 || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
193 || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
194 || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
195 || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
196
197 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((RCC_PLLN_MIN_VALUE <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLN_MAX_VALUE))
198
199 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
200 || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
201 || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
202 || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
203
204 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
205
206 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
207
208 #if !defined(RCC_MAX_FREQUENCY_SCALE1)
209 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
210 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
211
212 #elif defined(RCC_MAX_FREQUENCY_SCALE3)
213 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
214 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
215 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
216
217 #else
218 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
219 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
220
221 #endif /* RCC_MAX_FREQUENCY_SCALE1*/
222 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
223 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
224
225 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
226 /**
227 * @}
228 */
229 /* Private function prototypes -----------------------------------------------*/
230 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
231 * @{
232 */
233 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
234 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
235 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
236 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
237 static ErrorStatus UTILS_PLL_IsBusy(void);
238 /**
239 * @}
240 */
241
242 /* Exported functions --------------------------------------------------------*/
243 /** @addtogroup UTILS_LL_Exported_Functions
244 * @{
245 */
246
247 /** @addtogroup UTILS_LL_EF_DELAY
248 * @{
249 */
250
251 /**
252 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
253 * @note When a RTOS is used, it is recommended to avoid changing the Systick
254 * configuration by calling this function, for a delay use rather osDelay RTOS service.
255 * @param HCLKFrequency HCLK frequency in Hz
256 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
257 * @retval None
258 */
LL_Init1msTick(uint32_t HCLKFrequency)259 void LL_Init1msTick(uint32_t HCLKFrequency)
260 {
261 /* Use frequency provided in argument */
262 LL_InitTick(HCLKFrequency, 1000U);
263 }
264
265 /**
266 * @brief This function provides accurate delay (in milliseconds) based
267 * on SysTick counter flag
268 * @note When a RTOS is used, it is recommended to avoid using blocking delay
269 * and use rather osDelay service.
270 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
271 * will configure Systick to 1ms
272 * @param Delay specifies the delay time length, in milliseconds.
273 * @retval None
274 */
LL_mDelay(uint32_t Delay)275 void LL_mDelay(uint32_t Delay)
276 {
277 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
278 /* Add this code to indicate that local variable is not used */
279 ((void)tmp);
280
281 /* Add a period to guaranty minimum wait */
282 if(Delay < LL_MAX_DELAY)
283 {
284 Delay++;
285 }
286
287 while (Delay)
288 {
289 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
290 {
291 Delay--;
292 }
293 }
294 }
295
296 /**
297 * @}
298 */
299
300 /** @addtogroup UTILS_EF_SYSTEM
301 * @brief System Configuration functions
302 *
303 @verbatim
304 ===============================================================================
305 ##### System Configuration functions #####
306 ===============================================================================
307 [..]
308 System, AHB and APB buses clocks configuration
309
310 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 180000000 Hz.
311 @endverbatim
312 @internal
313 Depending on the device voltage range, the maximum frequency should be
314 adapted accordingly to the Refenece manual.
315 @endinternal
316 * @{
317 */
318
319 /**
320 * @brief This function sets directly SystemCoreClock CMSIS variable.
321 * @note Variable can be calculated also through SystemCoreClockUpdate function.
322 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
323 * @retval None
324 */
LL_SetSystemCoreClock(uint32_t HCLKFrequency)325 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
326 {
327 /* HCLK clock frequency */
328 SystemCoreClock = HCLKFrequency;
329 }
330
331 /**
332 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
333 * @note The application need to ensure that PLL is disabled.
334 * @note Function is based on the following formula:
335 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
336 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
337 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
338 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
339 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
340 * the configuration information for the PLL.
341 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
342 * the configuration information for the BUS prescalers.
343 * @retval An ErrorStatus enumeration value:
344 * - SUCCESS: Max frequency configuration done
345 * - ERROR: Max frequency configuration not done
346 */
LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)347 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
348 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
349 {
350 ErrorStatus status = SUCCESS;
351 uint32_t pllfreq = 0U;
352
353 /* Check if one of the PLL is enabled */
354 if(UTILS_PLL_IsBusy() == SUCCESS)
355 {
356 /* Calculate the new PLL output frequency */
357 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
358
359 /* Enable HSI if not enabled */
360 if(LL_RCC_HSI_IsReady() != 1U)
361 {
362 LL_RCC_HSI_Enable();
363 while (LL_RCC_HSI_IsReady() != 1U)
364 {
365 /* Wait for HSI ready */
366 }
367 }
368
369 /* Configure PLL */
370 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
371 UTILS_PLLInitStruct->PLLP);
372
373 /* Enable PLL and switch system clock to PLL */
374 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
375 }
376 else
377 {
378 /* Current PLL configuration cannot be modified */
379 status = ERROR;
380 }
381
382 return status;
383 }
384
385 /**
386 * @brief This function configures system clock with HSE as clock source of the PLL
387 * @note The application need to ensure that PLL is disabled.
388 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
389 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
390 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
391 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
392 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
393 * @param HSEBypass This parameter can be one of the following values:
394 * @arg @ref LL_UTILS_HSEBYPASS_ON
395 * @arg @ref LL_UTILS_HSEBYPASS_OFF
396 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
397 * the configuration information for the PLL.
398 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
399 * the configuration information for the BUS prescalers.
400 * @retval An ErrorStatus enumeration value:
401 * - SUCCESS: Max frequency configuration done
402 * - ERROR: Max frequency configuration not done
403 */
LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,uint32_t HSEBypass,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)404 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
405 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
406 {
407 ErrorStatus status = SUCCESS;
408 uint32_t pllfreq = 0U;
409
410 /* Check the parameters */
411 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
412 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
413
414 /* Check if one of the PLL is enabled */
415 if(UTILS_PLL_IsBusy() == SUCCESS)
416 {
417 /* Calculate the new PLL output frequency */
418 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
419
420 /* Enable HSE if not enabled */
421 if(LL_RCC_HSE_IsReady() != 1U)
422 {
423 /* Check if need to enable HSE bypass feature or not */
424 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
425 {
426 LL_RCC_HSE_EnableBypass();
427 }
428 else
429 {
430 LL_RCC_HSE_DisableBypass();
431 }
432
433 /* Enable HSE */
434 LL_RCC_HSE_Enable();
435 while (LL_RCC_HSE_IsReady() != 1U)
436 {
437 /* Wait for HSE ready */
438 }
439 }
440
441 /* Configure PLL */
442 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
443 UTILS_PLLInitStruct->PLLP);
444
445 /* Enable PLL and switch system clock to PLL */
446 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
447 }
448 else
449 {
450 /* Current PLL configuration cannot be modified */
451 status = ERROR;
452 }
453
454 return status;
455 }
456
457 /**
458 * @}
459 */
460
461 /**
462 * @}
463 */
464
465 /** @addtogroup UTILS_LL_Private_Functions
466 * @{
467 */
468 /**
469 * @brief Update number of Flash wait states in line with new frequency and current
470 voltage range.
471 * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
472 * @param HCLK_Frequency HCLK frequency
473 * @retval An ErrorStatus enumeration value:
474 * - SUCCESS: Latency has been modified
475 * - ERROR: Latency cannot be modified
476 */
UTILS_SetFlashLatency(uint32_t HCLK_Frequency)477 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
478 {
479 ErrorStatus status = SUCCESS;
480
481 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
482
483 /* Frequency cannot be equal to 0 */
484 if(HCLK_Frequency == 0U)
485 {
486 status = ERROR;
487 }
488 else
489 {
490 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
491 {
492 #if defined (UTILS_SCALE1_LATENCY5_FREQ)
493 if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
494 {
495 latency = LL_FLASH_LATENCY_5;
496 }
497 #endif /*UTILS_SCALE1_LATENCY5_FREQ */
498 #if defined (UTILS_SCALE1_LATENCY4_FREQ)
499 if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
500 {
501 latency = LL_FLASH_LATENCY_4;
502 }
503 #endif /* UTILS_SCALE1_LATENCY4_FREQ */
504 #if defined (UTILS_SCALE1_LATENCY3_FREQ)
505 if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
506 {
507 latency = LL_FLASH_LATENCY_3;
508 }
509 #endif /* UTILS_SCALE1_LATENCY3_FREQ */
510 #if defined (UTILS_SCALE1_LATENCY2_FREQ)
511 if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
512 {
513 latency = LL_FLASH_LATENCY_2;
514 }
515 else
516 {
517 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
518 {
519 latency = LL_FLASH_LATENCY_1;
520 }
521 }
522 #endif /* UTILS_SCALE1_LATENCY2_FREQ */
523 }
524 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
525 {
526 #if defined (UTILS_SCALE2_LATENCY5_FREQ)
527 if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
528 {
529 latency = LL_FLASH_LATENCY_5;
530 }
531 #endif /*UTILS_SCALE1_LATENCY5_FREQ */
532 #if defined (UTILS_SCALE2_LATENCY4_FREQ)
533 if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
534 {
535 latency = LL_FLASH_LATENCY_4;
536 }
537 #endif /*UTILS_SCALE1_LATENCY4_FREQ */
538 #if defined (UTILS_SCALE2_LATENCY3_FREQ)
539 if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
540 {
541 latency = LL_FLASH_LATENCY_3;
542 }
543 #endif /*UTILS_SCALE1_LATENCY3_FREQ */
544 if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
545 {
546 latency = LL_FLASH_LATENCY_2;
547 }
548 else
549 {
550 if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
551 {
552 latency = LL_FLASH_LATENCY_1;
553 }
554 }
555 }
556 #if defined (LL_PWR_REGU_VOLTAGE_SCALE3)
557 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3)
558 {
559 #if defined (UTILS_SCALE3_LATENCY3_FREQ)
560 if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
561 {
562 latency = LL_FLASH_LATENCY_3;
563 }
564 #endif /*UTILS_SCALE1_LATENCY3_FREQ */
565 #if defined (UTILS_SCALE3_LATENCY2_FREQ)
566 if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
567 {
568 latency = LL_FLASH_LATENCY_2;
569 }
570 else
571 {
572 if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
573 {
574 latency = LL_FLASH_LATENCY_1;
575 }
576 }
577 }
578 #endif /*UTILS_SCALE1_LATENCY2_FREQ */
579 #endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */
580
581 LL_FLASH_SetLatency(latency);
582
583 /* Check that the new number of wait states is taken into account to access the Flash
584 memory by reading the FLASH_ACR register */
585 if(LL_FLASH_GetLatency() != latency)
586 {
587 status = ERROR;
588 }
589 }
590 return status;
591 }
592
593 /**
594 * @brief Function to check that PLL can be modified
595 * @param PLL_InputFrequency PLL input frequency (in Hz)
596 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
597 * the configuration information for the PLL.
598 * @retval PLL output frequency (in Hz)
599 */
UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct)600 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
601 {
602 uint32_t pllfreq = 0U;
603
604 /* Check the parameters */
605 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
606 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
607 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
608
609 /* Check different PLL parameters according to RM */
610 /* - PLLM: ensure that the VCO input frequency ranges from @ref UTILS_PLLVCO_INPUT_MIN to @ref UTILS_PLLVCO_INPUT_MAX MHz. */
611 pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
612 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
613
614 /* - PLLN: ensure that the VCO output frequency is between @ref UTILS_PLLVCO_OUTPUT_MIN and @ref UTILS_PLLVCO_OUTPUT_MAX .*/
615 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
616 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
617
618 /* - PLLP: ensure that max frequency at @ref RCC_MAX_FREQUENCY Hz is reached */
619 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
620 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
621
622 return pllfreq;
623 }
624
625 /**
626 * @brief Function to check that PLL can be modified
627 * @retval An ErrorStatus enumeration value:
628 * - SUCCESS: PLL modification can be done
629 * - ERROR: PLL is busy
630 */
UTILS_PLL_IsBusy(void)631 static ErrorStatus UTILS_PLL_IsBusy(void)
632 {
633 ErrorStatus status = SUCCESS;
634
635 /* Check if PLL is busy*/
636 if(LL_RCC_PLL_IsReady() != 0U)
637 {
638 /* PLL configuration cannot be modified */
639 status = ERROR;
640 }
641
642 #if defined(RCC_PLLSAI_SUPPORT)
643 /* Check if PLLSAI is busy*/
644 if(LL_RCC_PLLSAI_IsReady() != 0U)
645 {
646 /* PLLSAI1 configuration cannot be modified */
647 status = ERROR;
648 }
649 #endif /*RCC_PLLSAI_SUPPORT*/
650 #if defined(RCC_PLLI2S_SUPPORT)
651 /* Check if PLLI2S is busy*/
652 if(LL_RCC_PLLI2S_IsReady() != 0U)
653 {
654 /* PLLI2S configuration cannot be modified */
655 status = ERROR;
656 }
657 #endif /*RCC_PLLI2S_SUPPORT*/
658 return status;
659 }
660
661 /**
662 * @brief Function to enable PLL and switch system clock to PLL
663 * @param SYSCLK_Frequency SYSCLK frequency
664 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
665 * the configuration information for the BUS prescalers.
666 * @retval An ErrorStatus enumeration value:
667 * - SUCCESS: No problem to switch system to PLL
668 * - ERROR: Problem to switch system to PLL
669 */
UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)670 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
671 {
672 ErrorStatus status = SUCCESS;
673 uint32_t hclk_frequency = 0U;
674
675 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
676 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
677 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
678
679 /* Calculate HCLK frequency */
680 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
681
682 /* Increasing the number of wait states because of higher CPU frequency */
683 if(SystemCoreClock < hclk_frequency)
684 {
685 /* Set FLASH latency to highest latency */
686 status = UTILS_SetFlashLatency(hclk_frequency);
687 }
688
689 /* Update system clock configuration */
690 if(status == SUCCESS)
691 {
692 /* Enable PLL */
693 LL_RCC_PLL_Enable();
694 while (LL_RCC_PLL_IsReady() != 1U)
695 {
696 /* Wait for PLL ready */
697 }
698
699 /* Sysclk activation on the main PLL */
700 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
701 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
702 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
703 {
704 /* Wait for system clock switch to PLL */
705 }
706
707 /* Set APB1 & APB2 prescaler*/
708 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
709 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
710 }
711
712 /* Decreasing the number of wait states because of lower CPU frequency */
713 if(SystemCoreClock > hclk_frequency)
714 {
715 /* Set FLASH latency to lowest latency */
716 status = UTILS_SetFlashLatency(hclk_frequency);
717 }
718
719 /* Update SystemCoreClock variable */
720 if(status == SUCCESS)
721 {
722 LL_SetSystemCoreClock(hclk_frequency);
723 }
724
725 return status;
726 }
727
728 /**
729 * @}
730 */
731
732 /**
733 * @}
734 */
735
736 /**
737 * @}
738 */
739
740 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
741