1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_dma2d.h
4 * @author MCD Application Team
5 * @brief Header file of DMA2D LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_LL_DMA2D_H
22 #define STM32L4xx_LL_DMA2D_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx.h"
30
31 /** @addtogroup STM32L4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA2D)
36
37 /** @defgroup DMA2D_LL DMA2D
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 #if defined(USE_FULL_LL_DRIVER)
46 /** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
47 * @{
48 */
49
50 /**
51 * @}
52 */
53 #endif /*USE_FULL_LL_DRIVER*/
54
55 /* Exported types ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
58 * @{
59 */
60
61 /**
62 * @brief LL DMA2D Init Structure Definition
63 */
64 typedef struct
65 {
66 uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
67 - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
68
69 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/
70
71 uint32_t ColorMode; /*!< Specifies the color format of the output image.
72 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
73
74 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
75
76 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
77 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
78 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
79 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
80 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
81 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
82
83 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
84 function @ref LL_DMA2D_ConfigOutputColor(). */
85
86 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
87 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
88 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
89 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
90 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
91 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
92
93 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
94 function @ref LL_DMA2D_ConfigOutputColor(). */
95
96 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
97 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
98 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
99 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
100 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
101 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
102
103 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
104 function @ref LL_DMA2D_ConfigOutputColor(). */
105
106 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
107 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
108 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
109 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
110 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
111
112 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
113 function @ref LL_DMA2D_ConfigOutputColor(). */
114
115 uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
116 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
117
118 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
119
120 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
121 uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image.
122 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE.
123
124 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */
125 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
126
127 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
128 uint32_t LineOffsetMode; /*!< Specifies the output line offset mode.
129 - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE.
130
131 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */
132 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
133
134 uint32_t LineOffset; /*!< Specifies the output line offset value.
135 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF on devices
136 where the Line Offset Mode feature is available.
137 else between Min_Data = 0x0000 and Max_Data = 0xFFFF on other devices.
138
139 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
140
141 uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
142 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
143
144 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
145
146 uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered.
147 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
148
149 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
150
151 uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
152 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
153
154 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
155
156 uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
157 - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
158
159 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
160
161 } LL_DMA2D_InitTypeDef;
162
163 /**
164 * @brief LL DMA2D Layer Configuration Structure Definition
165 */
166 typedef struct
167 {
168 uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
169 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
170
171 This parameter can be modified afterwards using unitary functions
172 - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
173 - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
174
175 uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
176 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
177
178 This parameter can be modified afterwards using unitary functions
179 - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
180 - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
181
182 uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
183 - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
184
185 This parameter can be modified afterwards using unitary functions
186 - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
187 - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
188
189 uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
190 - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
191
192 This parameter can be modified afterwards using unitary functions
193 - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
194 - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
195
196 uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
197 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
198
199 This parameter can be modified afterwards using unitary functions
200 - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
201 - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
202
203 uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
204 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
205
206 This parameter can be modified afterwards using unitary functions
207 - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
208 - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
209
210 uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
211 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
212
213 This parameter can be modified afterwards using unitary functions
214 - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
215 - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
216
217 uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
218 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
219
220 This parameter can be modified afterwards using unitary functions
221 - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
222 - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
223
224 uint32_t Green; /*!< Specifies the foreground or background Green color value.
225 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
226
227 This parameter can be modified afterwards using unitary functions
228 - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
229 - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
230
231 uint32_t Red; /*!< Specifies the foreground or background Red color value.
232 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
233
234 This parameter can be modified afterwards using unitary functions
235 - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
236 - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
237
238 uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
239 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
240
241 This parameter can be modified afterwards using unitary functions
242 - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
243 - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
244
245 uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode.
246 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
247
248 This parameter can be modified afterwards using unitary functions
249 - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
250 - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
251
252 uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode.
253 This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
254
255 This parameter can be modified afterwards using unitary functions
256 - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
257 - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
258
259
260 } LL_DMA2D_LayerCfgTypeDef;
261
262 /**
263 * @brief LL DMA2D Output Color Structure Definition
264 */
265 typedef struct
266 {
267 uint32_t ColorMode; /*!< Specifies the color format of the output image.
268 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
269
270 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
271
272 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
273 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
274 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
275 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
276 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
277 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
278
279 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
280 function @ref LL_DMA2D_ConfigOutputColor(). */
281
282 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
283 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
284 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
285 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
286 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
287 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
288
289 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
290 function @ref LL_DMA2D_ConfigOutputColor(). */
291
292 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
293 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
294 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
295 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
296 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
297 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
298
299 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
300 function @ref LL_DMA2D_ConfigOutputColor(). */
301
302 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
303 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
304 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
305 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
306 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
307
308 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
309 function @ref LL_DMA2D_ConfigOutputColor(). */
310
311 } LL_DMA2D_ColorTypeDef;
312
313 /**
314 * @}
315 */
316 #endif /* USE_FULL_LL_DRIVER */
317
318 /* Exported constants --------------------------------------------------------*/
319 /** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
320 * @{
321 */
322
323 /** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
324 * @brief Flags defines which can be used with LL_DMA2D_ReadReg function
325 * @{
326 */
327 #define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
328 #define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
329 #define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
330 #define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
331 #define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
332 #define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
333 /**
334 * @}
335 */
336
337 /** @defgroup DMA2D_LL_EC_IT IT Defines
338 * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
339 * @{
340 */
341 #define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
342 #define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
343 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
344 #define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
345 #define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
346 #define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
347 /**
348 * @}
349 */
350
351 /** @defgroup DMA2D_LL_EC_MODE Mode
352 * @{
353 */
354 #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
355 #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
356 #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
357 #define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */
358 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
359 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */
360 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */
361 #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */
362 /**
363 * @}
364 */
365
366 /** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
367 * @{
368 */
369 #define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
370 #define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */
371 #define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */
372 #define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
373 #define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */
374 /**
375 * @}
376 */
377
378 /** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
379 * @{
380 */
381 #define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
382 #define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */
383 #define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */
384 #define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */
385 #define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */
386 #define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */
387 #define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */
388 #define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */
389 #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */
390 #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */
391 #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */
392 /**
393 * @}
394 */
395
396 /** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
397 * @{
398 */
399 #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
400 #define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */
401 #define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value
402 with original alpha channel value */
403 /**
404 * @}
405 */
406
407 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
408 /** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode
409 * @{
410 */
411 #define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */
412 #define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */
413 /**
414 * @}
415 */
416 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
417
418 /** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
419 * @{
420 */
421 #define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */
422 #define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */
423 /**
424 * @}
425 */
426
427 /** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
428 * @{
429 */
430 #define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */
431 #define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */
432 /**
433 * @}
434 */
435
436
437 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
438 /** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode
439 * @{
440 */
441 #define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */
442 #define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */
443 /**
444 * @}
445 */
446 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
447
448 /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
449 * @{
450 */
451 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
452 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */
453 /**
454 * @}
455 */
456
457
458 /**
459 * @}
460 */
461
462 /* Exported macro ------------------------------------------------------------*/
463 /** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
464 * @{
465 */
466
467 /** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
468 * @{
469 */
470
471 /**
472 * @brief Write a value in DMA2D register.
473 * @param __INSTANCE__ DMA2D Instance
474 * @param __REG__ Register to be written
475 * @param __VALUE__ Value to be written in the register
476 * @retval None
477 */
478 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
479
480 /**
481 * @brief Read a value in DMA2D register.
482 * @param __INSTANCE__ DMA2D Instance
483 * @param __REG__ Register to be read
484 * @retval Register value
485 */
486 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
487 /**
488 * @}
489 */
490
491 /**
492 * @}
493 */
494
495 /* Exported functions --------------------------------------------------------*/
496 /** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
497 * @{
498 */
499
500 /** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
501 * @{
502 */
503
504 /**
505 * @brief Start a DMA2D transfer.
506 * @rmtoll CR START LL_DMA2D_Start
507 * @param DMA2Dx DMA2D Instance
508 * @retval None
509 */
LL_DMA2D_Start(DMA2D_TypeDef * DMA2Dx)510 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
511 {
512 SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
513 }
514
515 /**
516 * @brief Indicate if a DMA2D transfer is ongoing.
517 * @rmtoll CR START LL_DMA2D_IsTransferOngoing
518 * @param DMA2Dx DMA2D Instance
519 * @retval State of bit (1 or 0).
520 */
LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef * DMA2Dx)521 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
522 {
523 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
524 }
525
526 /**
527 * @brief Suspend DMA2D transfer.
528 * @note This API can be used to suspend automatic foreground or background CLUT loading.
529 * @rmtoll CR SUSP LL_DMA2D_Suspend
530 * @param DMA2Dx DMA2D Instance
531 * @retval None
532 */
LL_DMA2D_Suspend(DMA2D_TypeDef * DMA2Dx)533 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
534 {
535 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
536 }
537
538 /**
539 * @brief Resume DMA2D transfer.
540 * @note This API can be used to resume automatic foreground or background CLUT loading.
541 * @rmtoll CR SUSP LL_DMA2D_Resume
542 * @param DMA2Dx DMA2D Instance
543 * @retval None
544 */
LL_DMA2D_Resume(DMA2D_TypeDef * DMA2Dx)545 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
546 {
547 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
548 }
549
550 /**
551 * @brief Indicate if DMA2D transfer is suspended.
552 * @note This API can be used to indicate whether or not automatic foreground or
553 * background CLUT loading is suspended.
554 * @rmtoll CR SUSP LL_DMA2D_IsSuspended
555 * @param DMA2Dx DMA2D Instance
556 * @retval State of bit (1 or 0).
557 */
LL_DMA2D_IsSuspended(DMA2D_TypeDef * DMA2Dx)558 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
559 {
560 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
561 }
562
563 /**
564 * @brief Abort DMA2D transfer.
565 * @note This API can be used to abort automatic foreground or background CLUT loading.
566 * @rmtoll CR ABORT LL_DMA2D_Abort
567 * @param DMA2Dx DMA2D Instance
568 * @retval None
569 */
LL_DMA2D_Abort(DMA2D_TypeDef * DMA2Dx)570 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
571 {
572 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
573 }
574
575 /**
576 * @brief Indicate if DMA2D transfer is aborted.
577 * @note This API can be used to indicate whether or not automatic foreground or
578 * background CLUT loading is aborted.
579 * @rmtoll CR ABORT LL_DMA2D_IsAborted
580 * @param DMA2Dx DMA2D Instance
581 * @retval State of bit (1 or 0).
582 */
LL_DMA2D_IsAborted(DMA2D_TypeDef * DMA2Dx)583 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
584 {
585 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
586 }
587
588 /**
589 * @brief Set DMA2D mode.
590 * @rmtoll CR MODE LL_DMA2D_SetMode
591 * @param DMA2Dx DMA2D Instance
592 * @param Mode This parameter can be one of the following values:
593 * @arg @ref LL_DMA2D_MODE_M2M
594 * @arg @ref LL_DMA2D_MODE_M2M_PFC
595 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
596 * @arg @ref LL_DMA2D_MODE_R2M
597 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG (*)
598 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (*)
599 *
600 * (*) value not defined in all devices.
601 * @retval None
602 */
LL_DMA2D_SetMode(DMA2D_TypeDef * DMA2Dx,uint32_t Mode)603 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
604 {
605 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
606 }
607
608 /**
609 * @brief Return DMA2D mode
610 * @rmtoll CR MODE LL_DMA2D_GetMode
611 * @param DMA2Dx DMA2D Instance
612 * @retval Returned value can be one of the following values:
613 * @arg @ref LL_DMA2D_MODE_M2M
614 * @arg @ref LL_DMA2D_MODE_M2M_PFC
615 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
616 * @arg @ref LL_DMA2D_MODE_R2M
617 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG (*)
618 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (*)
619 *
620 * (*) value not defined in all devices.
621 */
LL_DMA2D_GetMode(DMA2D_TypeDef * DMA2Dx)622 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
623 {
624 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
625 }
626
627 /**
628 * @brief Set DMA2D output color mode.
629 * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
630 * @param DMA2Dx DMA2D Instance
631 * @param ColorMode This parameter can be one of the following values:
632 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
633 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
634 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
635 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
636 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
637 * @retval None
638 */
LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)639 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
640 {
641 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
642 }
643
644 /**
645 * @brief Return DMA2D output color mode.
646 * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
647 * @param DMA2Dx DMA2D Instance
648 * @retval Returned value can be one of the following values:
649 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
650 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
651 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
652 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
653 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
654 */
LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef * DMA2Dx)655 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
656 {
657 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
658 }
659
660 /**
661 * @brief Set DMA2D output Red Blue swap mode.
662 * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode
663 * @param DMA2Dx DMA2D Instance
664 * @param RBSwapMode This parameter can be one of the following values:
665 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
666 * @arg @ref LL_DMA2D_RB_MODE_SWAP
667 * @retval None
668 */
LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)669 __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
670 {
671 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
672 }
673
674 /**
675 * @brief Return DMA2D output Red Blue swap mode.
676 * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode
677 * @param DMA2Dx DMA2D Instance
678 * @retval Returned value can be one of the following values:
679 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
680 * @arg @ref LL_DMA2D_RB_MODE_SWAP
681 */
LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef * DMA2Dx)682 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)
683 {
684 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
685 }
686
687 /**
688 * @brief Set DMA2D output alpha inversion mode.
689 * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode
690 * @param DMA2Dx DMA2D Instance
691 * @param AlphaInversionMode This parameter can be one of the following values:
692 * @arg @ref LL_DMA2D_ALPHA_REGULAR
693 * @arg @ref LL_DMA2D_ALPHA_INVERTED
694 * @retval None
695 */
LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)696 __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
697 {
698 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
699 }
700
701 /**
702 * @brief Return DMA2D output alpha inversion mode.
703 * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode
704 * @param DMA2Dx DMA2D Instance
705 * @retval Returned value can be one of the following values:
706 * @arg @ref LL_DMA2D_ALPHA_REGULAR
707 * @arg @ref LL_DMA2D_ALPHA_INVERTED
708 */
LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef * DMA2Dx)709 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
710 {
711 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
712 }
713
714
715 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
716 /**
717 * @brief Set DMA2D output swap mode.
718 * @rmtoll OPFCCR SB LL_DMA2D_SetOutputSwapMode
719 * @param DMA2Dx DMA2D Instance
720 * @param OutputSwapMode This parameter can be one of the following values:
721 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
722 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
723 * @retval None
724 */
LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t OutputSwapMode)725 __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
726 {
727 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode);
728 }
729
730 /**
731 * @brief Return DMA2D output swap mode.
732 * @rmtoll OPFCCR SB LL_DMA2D_GetOutputSwapMode
733 * @param DMA2Dx DMA2D Instance
734 * @retval Returned value can be one of the following values:
735 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
736 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
737 */
LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef * DMA2Dx)738 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx)
739 {
740 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB));
741 }
742 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
743
744 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
745 /**
746 * @brief Set DMA2D line offset mode.
747 * @rmtoll CR LOM LL_DMA2D_SetLineOffsetMode
748 * @param DMA2Dx DMA2D Instance
749 * @param LineOffsetMode This parameter can be one of the following values:
750 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
751 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
752 * @retval None
753 */
LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffsetMode)754 __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
755 {
756 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode);
757 }
758
759 /**
760 * @brief Return DMA2D line offset mode.
761 * @rmtoll CR LOM LL_DMA2D_GetLineOffsetMode
762 * @param DMA2Dx DMA2D Instance
763 * @retval Returned value can be one of the following values:
764 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
765 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
766 */
LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef * DMA2Dx)767 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx)
768 {
769 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM));
770 }
771 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
772
773 /**
774 * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
775 * @rmtoll OOR LO LL_DMA2D_SetLineOffset
776 * @param DMA2Dx DMA2D Instance
777 @if DMA2D_LINE_OFFSET_MODE_SUPPORT
778 * @param LineOffset Value between Min_Data=0 and Max_Data=0xFFFF
779 @else
780 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FFF
781 @endif
782 * @retval None
783 */
LL_DMA2D_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)784 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
785 {
786 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
787 }
788
789 /**
790 * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
791 * @rmtoll OOR LO LL_DMA2D_GetLineOffset
792 * @param DMA2Dx DMA2D Instance
793 @if DMA2D_LINE_OFFSET_MODE_SUPPORT
794 * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF
795 @else
796 * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF
797 @endif
798 */
LL_DMA2D_GetLineOffset(DMA2D_TypeDef * DMA2Dx)799 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
800 {
801 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
802 }
803
804 /**
805 * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
806 * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
807 * @param DMA2Dx DMA2D Instance
808 * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
809 * @retval None
810 */
LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef * DMA2Dx,uint32_t NbrOfPixelsPerLines)811 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
812 {
813 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
814 }
815
816 /**
817 * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
818 * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
819 * @param DMA2Dx DMA2D Instance
820 * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
821 */
LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef * DMA2Dx)822 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
823 {
824 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
825 }
826
827 /**
828 * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
829 * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
830 * @param DMA2Dx DMA2D Instance
831 * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
832 * @retval None
833 */
LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef * DMA2Dx,uint32_t NbrOfLines)834 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
835 {
836 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
837 }
838
839 /**
840 * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
841 * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
842 * @param DMA2Dx DMA2D Instance
843 * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
844 */
LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef * DMA2Dx)845 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
846 {
847 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
848 }
849
850 /**
851 * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
852 * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
853 * @param DMA2Dx DMA2D Instance
854 * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
855 * @retval None
856 */
LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t OutputMemoryAddress)857 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
858 {
859 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
860 }
861
862 /**
863 * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
864 * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
865 * @param DMA2Dx DMA2D Instance
866 * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
867 */
LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef * DMA2Dx)868 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
869 {
870 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
871 }
872
873 /**
874 * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
875 * @note Output color format depends on output color mode, ARGB8888, RGB888,
876 * RGB565, ARGB1555 or ARGB4444.
877 * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
878 * with respect to color mode is not done by the user code.
879 * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
880 * OCOLR GREEN LL_DMA2D_SetOutputColor\n
881 * OCOLR RED LL_DMA2D_SetOutputColor\n
882 * OCOLR ALPHA LL_DMA2D_SetOutputColor
883 * @param DMA2Dx DMA2D Instance
884 * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
885 * @retval None
886 */
LL_DMA2D_SetOutputColor(DMA2D_TypeDef * DMA2Dx,uint32_t OutputColor)887 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
888 {
889 MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
890 OutputColor);
891 }
892
893 /**
894 * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
895 * @note Alpha channel and red, green, blue color values must be retrieved from the returned
896 * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
897 * as set by @ref LL_DMA2D_SetOutputColorMode.
898 * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
899 * OCOLR GREEN LL_DMA2D_GetOutputColor\n
900 * OCOLR RED LL_DMA2D_GetOutputColor\n
901 * OCOLR ALPHA LL_DMA2D_GetOutputColor
902 * @param DMA2Dx DMA2D Instance
903 * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
904 */
LL_DMA2D_GetOutputColor(DMA2D_TypeDef * DMA2Dx)905 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
906 {
907 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
908 (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
909 }
910
911 /**
912 * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
913 * @rmtoll LWR LW LL_DMA2D_SetLineWatermark
914 * @param DMA2Dx DMA2D Instance
915 * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
916 * @retval None
917 */
LL_DMA2D_SetLineWatermark(DMA2D_TypeDef * DMA2Dx,uint32_t LineWatermark)918 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
919 {
920 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
921 }
922
923 /**
924 * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
925 * @rmtoll LWR LW LL_DMA2D_GetLineWatermark
926 * @param DMA2Dx DMA2D Instance
927 * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
928 */
LL_DMA2D_GetLineWatermark(DMA2D_TypeDef * DMA2Dx)929 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
930 {
931 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
932 }
933
934 /**
935 * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
936 * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
937 * @param DMA2Dx DMA2D Instance
938 * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
939 * @retval None
940 */
LL_DMA2D_SetDeadTime(DMA2D_TypeDef * DMA2Dx,uint32_t DeadTime)941 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
942 {
943 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
944 }
945
946 /**
947 * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
948 * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
949 * @param DMA2Dx DMA2D Instance
950 * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
951 */
LL_DMA2D_GetDeadTime(DMA2D_TypeDef * DMA2Dx)952 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
953 {
954 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
955 }
956
957 /**
958 * @brief Enable DMA2D dead time functionality.
959 * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
960 * @param DMA2Dx DMA2D Instance
961 * @retval None
962 */
LL_DMA2D_EnableDeadTime(DMA2D_TypeDef * DMA2Dx)963 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
964 {
965 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
966 }
967
968 /**
969 * @brief Disable DMA2D dead time functionality.
970 * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
971 * @param DMA2Dx DMA2D Instance
972 * @retval None
973 */
LL_DMA2D_DisableDeadTime(DMA2D_TypeDef * DMA2Dx)974 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
975 {
976 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
977 }
978
979 /**
980 * @brief Indicate if DMA2D dead time functionality is enabled.
981 * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
982 * @param DMA2Dx DMA2D Instance
983 * @retval State of bit (1 or 0).
984 */
LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef * DMA2Dx)985 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
986 {
987 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
988 }
989
990 /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
991 * @{
992 */
993
994 /**
995 * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
996 * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
997 * @param DMA2Dx DMA2D Instance
998 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
999 * @retval None
1000 */
LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t MemoryAddress)1001 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1002 {
1003 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
1004 }
1005
1006 /**
1007 * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
1008 * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
1009 * @param DMA2Dx DMA2D Instance
1010 * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1011 */
LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef * DMA2Dx)1012 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1013 {
1014 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
1015 }
1016
1017 /**
1018 * @brief Enable DMA2D foreground CLUT loading.
1019 * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
1020 * @param DMA2Dx DMA2D Instance
1021 * @retval None
1022 */
LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef * DMA2Dx)1023 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1024 {
1025 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
1026 }
1027
1028 /**
1029 * @brief Indicate if DMA2D foreground CLUT loading is enabled.
1030 * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
1031 * @param DMA2Dx DMA2D Instance
1032 * @retval State of bit (1 or 0).
1033 */
LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef * DMA2Dx)1034 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1035 {
1036 return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
1037 }
1038
1039 /**
1040 * @brief Set DMA2D foreground color mode.
1041 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
1042 * @param DMA2Dx DMA2D Instance
1043 * @param ColorMode This parameter can be one of the following values:
1044 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1045 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1046 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1047 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1048 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1049 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1050 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1051 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1052 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1053 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1054 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1055 * @retval None
1056 */
LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)1057 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1058 {
1059 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
1060 }
1061
1062 /**
1063 * @brief Return DMA2D foreground color mode.
1064 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
1065 * @param DMA2Dx DMA2D Instance
1066 * @retval Returned value can be one of the following values:
1067 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1068 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1069 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1070 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1071 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1072 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1073 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1074 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1075 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1076 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1077 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1078 */
LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef * DMA2Dx)1079 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1080 {
1081 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
1082 }
1083
1084 /**
1085 * @brief Set DMA2D foreground alpha mode.
1086 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
1087 * @param DMA2Dx DMA2D Instance
1088 * @param AphaMode This parameter can be one of the following values:
1089 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1090 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1091 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1092 * @retval None
1093 */
LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef * DMA2Dx,uint32_t AphaMode)1094 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1095 {
1096 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
1097 }
1098
1099 /**
1100 * @brief Return DMA2D foreground alpha mode.
1101 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
1102 * @param DMA2Dx DMA2D Instance
1103 * @retval Returned value can be one of the following values:
1104 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1105 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1106 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1107 */
LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef * DMA2Dx)1108 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1109 {
1110 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
1111 }
1112
1113 /**
1114 * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1115 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
1116 * @param DMA2Dx DMA2D Instance
1117 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1118 * @retval None
1119 */
LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef * DMA2Dx,uint32_t Alpha)1120 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1121 {
1122 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
1123 }
1124
1125 /**
1126 * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1127 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
1128 * @param DMA2Dx DMA2D Instance
1129 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1130 */
LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef * DMA2Dx)1131 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1132 {
1133 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
1134 }
1135
1136 /**
1137 * @brief Set DMA2D foreground Red Blue swap mode.
1138 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode
1139 * @param DMA2Dx DMA2D Instance
1140 * @param RBSwapMode This parameter can be one of the following values:
1141 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1142 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1143 * @retval None
1144 */
LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)1145 __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1146 {
1147 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
1148 }
1149
1150 /**
1151 * @brief Return DMA2D foreground Red Blue swap mode.
1152 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode
1153 * @param DMA2Dx DMA2D Instance
1154 * @retval Returned value can be one of the following values:
1155 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1156 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1157 */
LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef * DMA2Dx)1158 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1159 {
1160 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
1161 }
1162
1163 /**
1164 * @brief Set DMA2D foreground alpha inversion mode.
1165 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode
1166 * @param DMA2Dx DMA2D Instance
1167 * @param AlphaInversionMode This parameter can be one of the following values:
1168 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1169 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1170 * @retval None
1171 */
LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)1172 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1173 {
1174 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
1175 }
1176
1177 /**
1178 * @brief Return DMA2D foreground alpha inversion mode.
1179 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode
1180 * @param DMA2Dx DMA2D Instance
1181 * @retval Returned value can be one of the following values:
1182 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1183 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1184 */
LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef * DMA2Dx)1185 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1186 {
1187 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
1188 }
1189
1190 /**
1191 * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1192 * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
1193 * @param DMA2Dx DMA2D Instance
1194 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1195 * @retval None
1196 */
LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)1197 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1198 {
1199 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
1200 }
1201
1202 /**
1203 * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1204 * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
1205 * @param DMA2Dx DMA2D Instance
1206 * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
1207 */
LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef * DMA2Dx)1208 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1209 {
1210 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
1211 }
1212
1213 /**
1214 * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
1215 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
1216 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
1217 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
1218 * @param DMA2Dx DMA2D Instance
1219 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1220 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1221 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1222 * @retval None
1223 */
LL_DMA2D_FGND_SetColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red,uint32_t Green,uint32_t Blue)1224 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1225 {
1226 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
1227 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
1228 }
1229
1230 /**
1231 * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1232 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
1233 * @param DMA2Dx DMA2D Instance
1234 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1235 * @retval None
1236 */
LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red)1237 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1238 {
1239 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
1240 }
1241
1242 /**
1243 * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1244 * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
1245 * @param DMA2Dx DMA2D Instance
1246 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1247 */
LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef * DMA2Dx)1248 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1249 {
1250 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
1251 }
1252
1253 /**
1254 * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1255 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
1256 * @param DMA2Dx DMA2D Instance
1257 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1258 * @retval None
1259 */
LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef * DMA2Dx,uint32_t Green)1260 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1261 {
1262 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
1263 }
1264
1265 /**
1266 * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1267 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
1268 * @param DMA2Dx DMA2D Instance
1269 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1270 */
LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef * DMA2Dx)1271 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1272 {
1273 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
1274 }
1275
1276 /**
1277 * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1278 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
1279 * @param DMA2Dx DMA2D Instance
1280 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1281 * @retval None
1282 */
LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef * DMA2Dx,uint32_t Blue)1283 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1284 {
1285 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
1286 }
1287
1288 /**
1289 * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1290 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
1291 * @param DMA2Dx DMA2D Instance
1292 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1293 */
LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef * DMA2Dx)1294 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1295 {
1296 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
1297 }
1298
1299 /**
1300 * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1301 * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
1302 * @param DMA2Dx DMA2D Instance
1303 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1304 * @retval None
1305 */
LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTMemoryAddress)1306 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1307 {
1308 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
1309 }
1310
1311 /**
1312 * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1313 * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
1314 * @param DMA2Dx DMA2D Instance
1315 * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1316 */
LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx)1317 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1318 {
1319 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
1320 }
1321
1322 /**
1323 * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1324 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
1325 * @param DMA2Dx DMA2D Instance
1326 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1327 * @retval None
1328 */
LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTSize)1329 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1330 {
1331 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
1332 }
1333
1334 /**
1335 * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1336 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
1337 * @param DMA2Dx DMA2D Instance
1338 * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
1339 */
LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef * DMA2Dx)1340 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1341 {
1342 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
1343 }
1344
1345 /**
1346 * @brief Set DMA2D foreground CLUT color mode.
1347 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
1348 * @param DMA2Dx DMA2D Instance
1349 * @param CLUTColorMode This parameter can be one of the following values:
1350 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1351 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1352 * @retval None
1353 */
LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTColorMode)1354 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1355 {
1356 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
1357 }
1358
1359 /**
1360 * @brief Return DMA2D foreground CLUT color mode.
1361 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
1362 * @param DMA2Dx DMA2D Instance
1363 * @retval Returned value can be one of the following values:
1364 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1365 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1366 */
LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef * DMA2Dx)1367 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1368 {
1369 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
1370 }
1371
1372 /**
1373 * @}
1374 */
1375
1376 /** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
1377 * @{
1378 */
1379
1380 /**
1381 * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1382 * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
1383 * @param DMA2Dx DMA2D Instance
1384 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1385 * @retval None
1386 */
LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t MemoryAddress)1387 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1388 {
1389 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
1390 }
1391
1392 /**
1393 * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1394 * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
1395 * @param DMA2Dx DMA2D Instance
1396 * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1397 */
LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef * DMA2Dx)1398 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1399 {
1400 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
1401 }
1402
1403 /**
1404 * @brief Enable DMA2D background CLUT loading.
1405 * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
1406 * @param DMA2Dx DMA2D Instance
1407 * @retval None
1408 */
LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef * DMA2Dx)1409 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1410 {
1411 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
1412 }
1413
1414 /**
1415 * @brief Indicate if DMA2D background CLUT loading is enabled.
1416 * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
1417 * @param DMA2Dx DMA2D Instance
1418 * @retval State of bit (1 or 0).
1419 */
LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef * DMA2Dx)1420 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1421 {
1422 return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
1423 }
1424
1425 /**
1426 * @brief Set DMA2D background color mode.
1427 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
1428 * @param DMA2Dx DMA2D Instance
1429 * @param ColorMode This parameter can be one of the following values:
1430 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1431 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1432 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1433 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1434 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1435 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1436 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1437 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1438 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1439 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1440 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1441 * @retval None
1442 */
LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)1443 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1444 {
1445 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
1446 }
1447
1448 /**
1449 * @brief Return DMA2D background color mode.
1450 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
1451 * @param DMA2Dx DMA2D Instance
1452 * @retval Returned value can be one of the following values:
1453 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1454 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1455 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1456 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1457 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1458 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1459 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1460 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1461 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1462 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1463 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1464 */
LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef * DMA2Dx)1465 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1466 {
1467 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
1468 }
1469
1470 /**
1471 * @brief Set DMA2D background alpha mode.
1472 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
1473 * @param DMA2Dx DMA2D Instance
1474 * @param AphaMode This parameter can be one of the following values:
1475 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1476 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1477 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1478 * @retval None
1479 */
LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef * DMA2Dx,uint32_t AphaMode)1480 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1481 {
1482 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
1483 }
1484
1485 /**
1486 * @brief Return DMA2D background alpha mode.
1487 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
1488 * @param DMA2Dx DMA2D Instance
1489 * @retval Returned value can be one of the following values:
1490 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1491 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1492 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1493 */
LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef * DMA2Dx)1494 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1495 {
1496 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
1497 }
1498
1499 /**
1500 * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1501 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
1502 * @param DMA2Dx DMA2D Instance
1503 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1504 * @retval None
1505 */
LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef * DMA2Dx,uint32_t Alpha)1506 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1507 {
1508 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
1509 }
1510
1511 /**
1512 * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1513 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
1514 * @param DMA2Dx DMA2D Instance
1515 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1516 */
LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef * DMA2Dx)1517 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1518 {
1519 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
1520 }
1521
1522 /**
1523 * @brief Set DMA2D background Red Blue swap mode.
1524 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode
1525 * @param DMA2Dx DMA2D Instance
1526 * @param RBSwapMode This parameter can be one of the following values:
1527 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1528 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1529 * @retval None
1530 */
LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)1531 __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1532 {
1533 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
1534 }
1535
1536 /**
1537 * @brief Return DMA2D background Red Blue swap mode.
1538 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode
1539 * @param DMA2Dx DMA2D Instance
1540 * @retval Returned value can be one of the following values:
1541 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1542 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1543 */
LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef * DMA2Dx)1544 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1545 {
1546 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
1547 }
1548
1549 /**
1550 * @brief Set DMA2D background alpha inversion mode.
1551 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode
1552 * @param DMA2Dx DMA2D Instance
1553 * @param AlphaInversionMode This parameter can be one of the following values:
1554 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1555 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1556 * @retval None
1557 */
LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)1558 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1559 {
1560 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
1561 }
1562
1563 /**
1564 * @brief Return DMA2D background alpha inversion mode.
1565 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode
1566 * @param DMA2Dx DMA2D Instance
1567 * @retval Returned value can be one of the following values:
1568 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1569 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1570 */
LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef * DMA2Dx)1571 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1572 {
1573 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
1574 }
1575
1576 /**
1577 * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1578 * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
1579 * @param DMA2Dx DMA2D Instance
1580 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1581 * @retval None
1582 */
LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)1583 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1584 {
1585 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
1586 }
1587
1588 /**
1589 * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1590 * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
1591 * @param DMA2Dx DMA2D Instance
1592 * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
1593 */
LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef * DMA2Dx)1594 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1595 {
1596 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
1597 }
1598
1599 /**
1600 * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
1601 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
1602 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
1603 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
1604 * @param DMA2Dx DMA2D Instance
1605 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1606 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1607 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1608 * @retval None
1609 */
LL_DMA2D_BGND_SetColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red,uint32_t Green,uint32_t Blue)1610 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1611 {
1612 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
1613 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
1614 }
1615
1616 /**
1617 * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1618 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
1619 * @param DMA2Dx DMA2D Instance
1620 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1621 * @retval None
1622 */
LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red)1623 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1624 {
1625 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
1626 }
1627
1628 /**
1629 * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1630 * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
1631 * @param DMA2Dx DMA2D Instance
1632 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1633 */
LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef * DMA2Dx)1634 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1635 {
1636 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
1637 }
1638
1639 /**
1640 * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1641 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
1642 * @param DMA2Dx DMA2D Instance
1643 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1644 * @retval None
1645 */
LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef * DMA2Dx,uint32_t Green)1646 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1647 {
1648 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
1649 }
1650
1651 /**
1652 * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1653 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
1654 * @param DMA2Dx DMA2D Instance
1655 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1656 */
LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef * DMA2Dx)1657 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1658 {
1659 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
1660 }
1661
1662 /**
1663 * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1664 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
1665 * @param DMA2Dx DMA2D Instance
1666 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1667 * @retval None
1668 */
LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef * DMA2Dx,uint32_t Blue)1669 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1670 {
1671 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
1672 }
1673
1674 /**
1675 * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1676 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
1677 * @param DMA2Dx DMA2D Instance
1678 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1679 */
LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef * DMA2Dx)1680 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1681 {
1682 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
1683 }
1684
1685 /**
1686 * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1687 * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
1688 * @param DMA2Dx DMA2D Instance
1689 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1690 * @retval None
1691 */
LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTMemoryAddress)1692 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1693 {
1694 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
1695 }
1696
1697 /**
1698 * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1699 * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
1700 * @param DMA2Dx DMA2D Instance
1701 * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1702 */
LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx)1703 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1704 {
1705 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
1706 }
1707
1708 /**
1709 * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1710 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
1711 * @param DMA2Dx DMA2D Instance
1712 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1713 * @retval None
1714 */
LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTSize)1715 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1716 {
1717 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
1718 }
1719
1720 /**
1721 * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1722 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
1723 * @param DMA2Dx DMA2D Instance
1724 * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
1725 */
LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef * DMA2Dx)1726 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1727 {
1728 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
1729 }
1730
1731 /**
1732 * @brief Set DMA2D background CLUT color mode.
1733 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
1734 * @param DMA2Dx DMA2D Instance
1735 * @param CLUTColorMode This parameter can be one of the following values:
1736 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1737 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1738 * @retval None
1739 */
LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTColorMode)1740 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1741 {
1742 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
1743 }
1744
1745 /**
1746 * @brief Return DMA2D background CLUT color mode.
1747 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
1748 * @param DMA2Dx DMA2D Instance
1749 * @retval Returned value can be one of the following values:
1750 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1751 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1752 */
LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef * DMA2Dx)1753 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1754 {
1755 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
1756 }
1757
1758 /**
1759 * @}
1760 */
1761
1762 /**
1763 * @}
1764 */
1765
1766
1767 /** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
1768 * @{
1769 */
1770
1771 /**
1772 * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
1773 * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
1774 * @param DMA2Dx DMA2D Instance
1775 * @retval State of bit (1 or 0).
1776 */
LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef * DMA2Dx)1777 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
1778 {
1779 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
1780 }
1781
1782 /**
1783 * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
1784 * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
1785 * @param DMA2Dx DMA2D Instance
1786 * @retval State of bit (1 or 0).
1787 */
LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef * DMA2Dx)1788 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1789 {
1790 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
1791 }
1792
1793 /**
1794 * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
1795 * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
1796 * @param DMA2Dx DMA2D Instance
1797 * @retval State of bit (1 or 0).
1798 */
LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef * DMA2Dx)1799 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1800 {
1801 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
1802 }
1803
1804 /**
1805 * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
1806 * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
1807 * @param DMA2Dx DMA2D Instance
1808 * @retval State of bit (1 or 0).
1809 */
LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef * DMA2Dx)1810 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
1811 {
1812 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
1813 }
1814
1815 /**
1816 * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
1817 * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
1818 * @param DMA2Dx DMA2D Instance
1819 * @retval State of bit (1 or 0).
1820 */
LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef * DMA2Dx)1821 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
1822 {
1823 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
1824 }
1825
1826 /**
1827 * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
1828 * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
1829 * @param DMA2Dx DMA2D Instance
1830 * @retval State of bit (1 or 0).
1831 */
LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef * DMA2Dx)1832 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
1833 {
1834 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
1835 }
1836
1837 /**
1838 * @brief Clear DMA2D Configuration Error Interrupt Flag
1839 * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
1840 * @param DMA2Dx DMA2D Instance
1841 * @retval None
1842 */
LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef * DMA2Dx)1843 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
1844 {
1845 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
1846 }
1847
1848 /**
1849 * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
1850 * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
1851 * @param DMA2Dx DMA2D Instance
1852 * @retval None
1853 */
LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef * DMA2Dx)1854 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1855 {
1856 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
1857 }
1858
1859 /**
1860 * @brief Clear DMA2D CLUT Access Error Interrupt Flag
1861 * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
1862 * @param DMA2Dx DMA2D Instance
1863 * @retval None
1864 */
LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef * DMA2Dx)1865 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1866 {
1867 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
1868 }
1869
1870 /**
1871 * @brief Clear DMA2D Transfer Watermark Interrupt Flag
1872 * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
1873 * @param DMA2Dx DMA2D Instance
1874 * @retval None
1875 */
LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef * DMA2Dx)1876 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
1877 {
1878 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
1879 }
1880
1881 /**
1882 * @brief Clear DMA2D Transfer Complete Interrupt Flag
1883 * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
1884 * @param DMA2Dx DMA2D Instance
1885 * @retval None
1886 */
LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef * DMA2Dx)1887 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
1888 {
1889 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
1890 }
1891
1892 /**
1893 * @brief Clear DMA2D Transfer Error Interrupt Flag
1894 * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
1895 * @param DMA2Dx DMA2D Instance
1896 * @retval None
1897 */
LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef * DMA2Dx)1898 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
1899 {
1900 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
1901 }
1902
1903 /**
1904 * @}
1905 */
1906
1907 /** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
1908 * @{
1909 */
1910
1911 /**
1912 * @brief Enable Configuration Error Interrupt
1913 * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
1914 * @param DMA2Dx DMA2D Instance
1915 * @retval None
1916 */
LL_DMA2D_EnableIT_CE(DMA2D_TypeDef * DMA2Dx)1917 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
1918 {
1919 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1920 }
1921
1922 /**
1923 * @brief Enable CLUT Transfer Complete Interrupt
1924 * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
1925 * @param DMA2Dx DMA2D Instance
1926 * @retval None
1927 */
LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef * DMA2Dx)1928 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1929 {
1930 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1931 }
1932
1933 /**
1934 * @brief Enable CLUT Access Error Interrupt
1935 * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
1936 * @param DMA2Dx DMA2D Instance
1937 * @retval None
1938 */
LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef * DMA2Dx)1939 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
1940 {
1941 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
1942 }
1943
1944 /**
1945 * @brief Enable Transfer Watermark Interrupt
1946 * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
1947 * @param DMA2Dx DMA2D Instance
1948 * @retval None
1949 */
LL_DMA2D_EnableIT_TW(DMA2D_TypeDef * DMA2Dx)1950 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
1951 {
1952 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
1953 }
1954
1955 /**
1956 * @brief Enable Transfer Complete Interrupt
1957 * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
1958 * @param DMA2Dx DMA2D Instance
1959 * @retval None
1960 */
LL_DMA2D_EnableIT_TC(DMA2D_TypeDef * DMA2Dx)1961 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
1962 {
1963 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
1964 }
1965
1966 /**
1967 * @brief Enable Transfer Error Interrupt
1968 * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
1969 * @param DMA2Dx DMA2D Instance
1970 * @retval None
1971 */
LL_DMA2D_EnableIT_TE(DMA2D_TypeDef * DMA2Dx)1972 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
1973 {
1974 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
1975 }
1976
1977 /**
1978 * @brief Disable Configuration Error Interrupt
1979 * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
1980 * @param DMA2Dx DMA2D Instance
1981 * @retval None
1982 */
LL_DMA2D_DisableIT_CE(DMA2D_TypeDef * DMA2Dx)1983 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
1984 {
1985 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1986 }
1987
1988 /**
1989 * @brief Disable CLUT Transfer Complete Interrupt
1990 * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
1991 * @param DMA2Dx DMA2D Instance
1992 * @retval None
1993 */
LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef * DMA2Dx)1994 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1995 {
1996 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1997 }
1998
1999 /**
2000 * @brief Disable CLUT Access Error Interrupt
2001 * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
2002 * @param DMA2Dx DMA2D Instance
2003 * @retval None
2004 */
LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef * DMA2Dx)2005 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
2006 {
2007 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
2008 }
2009
2010 /**
2011 * @brief Disable Transfer Watermark Interrupt
2012 * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
2013 * @param DMA2Dx DMA2D Instance
2014 * @retval None
2015 */
LL_DMA2D_DisableIT_TW(DMA2D_TypeDef * DMA2Dx)2016 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
2017 {
2018 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
2019 }
2020
2021 /**
2022 * @brief Disable Transfer Complete Interrupt
2023 * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
2024 * @param DMA2Dx DMA2D Instance
2025 * @retval None
2026 */
LL_DMA2D_DisableIT_TC(DMA2D_TypeDef * DMA2Dx)2027 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
2028 {
2029 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
2030 }
2031
2032 /**
2033 * @brief Disable Transfer Error Interrupt
2034 * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
2035 * @param DMA2Dx DMA2D Instance
2036 * @retval None
2037 */
LL_DMA2D_DisableIT_TE(DMA2D_TypeDef * DMA2Dx)2038 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
2039 {
2040 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2041 }
2042
2043 /**
2044 * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
2045 * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
2046 * @param DMA2Dx DMA2D Instance
2047 * @retval State of bit (1 or 0).
2048 */
LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef * DMA2Dx)2049 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
2050 {
2051 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
2052 }
2053
2054 /**
2055 * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
2056 * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
2057 * @param DMA2Dx DMA2D Instance
2058 * @retval State of bit (1 or 0).
2059 */
LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef * DMA2Dx)2060 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
2061 {
2062 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
2063 }
2064
2065 /**
2066 * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
2067 * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
2068 * @param DMA2Dx DMA2D Instance
2069 * @retval State of bit (1 or 0).
2070 */
LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef * DMA2Dx)2071 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
2072 {
2073 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
2074 }
2075
2076 /**
2077 * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
2078 * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
2079 * @param DMA2Dx DMA2D Instance
2080 * @retval State of bit (1 or 0).
2081 */
LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef * DMA2Dx)2082 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
2083 {
2084 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
2085 }
2086
2087 /**
2088 * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
2089 * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
2090 * @param DMA2Dx DMA2D Instance
2091 * @retval State of bit (1 or 0).
2092 */
LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef * DMA2Dx)2093 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
2094 {
2095 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
2096 }
2097
2098 /**
2099 * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
2100 * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
2101 * @param DMA2Dx DMA2D Instance
2102 * @retval State of bit (1 or 0).
2103 */
LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef * DMA2Dx)2104 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
2105 {
2106 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
2107 }
2108
2109
2110
2111 /**
2112 * @}
2113 */
2114
2115 #if defined(USE_FULL_LL_DRIVER)
2116 /** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
2117 * @{
2118 */
2119
2120 ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
2121 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2122 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2123 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
2124 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
2125 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
2126 uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2127 uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2128 uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2129 uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2130 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
2131
2132 /**
2133 * @}
2134 */
2135 #endif /* USE_FULL_LL_DRIVER */
2136
2137 /**
2138 * @}
2139 */
2140
2141 /**
2142 * @}
2143 */
2144
2145 #endif /* defined (DMA2D) */
2146
2147 /**
2148 * @}
2149 */
2150
2151 #ifdef __cplusplus
2152 }
2153 #endif
2154
2155 #endif /* STM32L4xx_LL_DMA2D_H */
2156
2157 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2158