1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_dac.c
4 * @author MCD Application Team
5 * @brief DAC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Digital to Analog Converter (DAC) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 *
13 *
14 @verbatim
15 ==============================================================================
16 ##### DAC Peripheral features #####
17 ==============================================================================
18 [..]
19 *** DAC Channels ***
20 ====================
21 [..]
22 STM32L4 devices integrate one or two 12-bit Digital Analog Converters
23 (i.e. one or 2 channel(s))
24 1 channel : STM32L451xx STM32L452xx STM32L462xx
25 2 channels: STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx
26 STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx
27 STM32L4P5xx STM32L4Q5xx
28 STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx
29
30 When 2 channels are available, the 2 converters (i.e. channel1 & channel2)
31 can be used independently or simultaneously (dual mode):
32 (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
33 peripherals.
34 (#) Whenever present, DAC channel2 with DAC_OUT2 (PA5) as output
35 or connected to on-chip peripherals.
36
37 *** DAC Triggers ***
38 ====================
39 [..]
40 Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
41 and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
42 [..]
43 Digital to Analog conversion can be triggered by:
44 (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
45 The used pin (GPIOx_PIN_9) must be configured in input mode.
46
47 (#) Timers TRGO: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7
48 (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...)
49
50 (#) Software using DAC_TRIGGER_SOFTWARE
51
52 *** DAC Buffer mode feature ***
53 ===============================
54 [..]
55 Each DAC channel integrates an output buffer that can be used to
56 reduce the output impedance, and to drive external loads directly
57 without having to add an external operational amplifier.
58 To enable, the output buffer use
59 sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
60 [..]
61 (@) Refer to the device datasheet for more details about output
62 impedance value with and without output buffer.
63
64 *** DAC connect feature ***
65 ===============================
66 [..]
67 Each DAC channel can be connected internally.
68 To connect, use
69 sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;
70
71 *** GPIO configurations guidelines ***
72 =====================
73 [..]
74 When a DAC channel is used (ex channel1 on PA4) and the other is not
75 (ex channel2 on PA5 is configured in Analog and disabled).
76 Channel1 may disturb channel2 as coupling effect.
77 Note that there is no coupling on channel2 as soon as channel2 is turned on.
78 Coupling on adjacent channel could be avoided as follows:
79 when unused PA5 is configured as INPUT PULL-UP or DOWN.
80 PA5 is configured in ANALOG just before it is turned on.
81
82 *** DAC Sample and Hold feature ***
83 ========================
84 [..]
85 For each converter, 2 modes are supported: normal mode and
86 "sample and hold" mode (i.e. low power mode).
87 In the sample and hold mode, the DAC core converts data, then holds the
88 converted voltage on a capacitor. When not converting, the DAC cores and
89 buffer are completely turned off between samples and the DAC output is
90 tri-stated, therefore reducing the overall power consumption. A new
91 stabilization period is needed before each new conversion.
92
93 The sample and hold allow setting internal or external voltage @
94 low power consumption cost (output value can be at any given rate either
95 by CPU or DMA).
96
97 The Sample and hold block and registers uses either LSI & run in
98 several power modes: run mode, sleep mode, low power run, low power sleep
99 mode & stop1 mode.
100
101 Low power stop1 mode allows only static conversion.
102
103 To enable Sample and Hold mode
104 Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
105 RCC_LSI_ON parameters.
106
107 Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
108 & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
109 DAC_HoldTime & DAC_RefreshTime;
110
111 *** DAC calibration feature ***
112 ===================================
113 [..]
114 (#) The 2 converters (channel1 & channel2) provide calibration capabilities.
115 (++) Calibration aims at correcting some offset of output buffer.
116 (++) The DAC uses either factory calibration settings OR user defined
117 calibration (trimming) settings (i.e. trimming mode).
118 (++) The user defined settings can be figured out using self calibration
119 handled by HAL_DACEx_SelfCalibrate.
120 (++) HAL_DACEx_SelfCalibrate:
121 (+++) Runs automatically the calibration.
122 (+++) Enables the user trimming mode
123 (+++) Updates a structure with trimming values with fresh calibration
124 results.
125 The user may store the calibration results for larger
126 (ex monitoring the trimming as a function of temperature
127 for instance)
128
129 *** DAC wave generation feature ***
130 ===================================
131 [..]
132 Both DAC channels can be used to generate
133 (#) Noise wave
134 (#) Triangle wave
135
136 *** DAC data format ***
137 =======================
138 [..]
139 The DAC data format can be:
140 (#) 8-bit right alignment using DAC_ALIGN_8B_R
141 (#) 12-bit left alignment using DAC_ALIGN_12B_L
142 (#) 12-bit right alignment using DAC_ALIGN_12B_R
143
144 *** DAC data value to voltage correspondence ***
145 ================================================
146 [..]
147 The analog output voltage on each DAC channel pin is determined
148 by the following equation:
149 [..]
150 DAC_OUTx = VREF+ * DOR / 4095
151 (+) with DOR is the Data Output Register
152 [..]
153 VEF+ is the input voltage reference (refer to the device datasheet)
154 [..]
155 e.g. To set DAC_OUT1 to 0.7V, use
156 (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
157
158 *** DMA requests ***
159 =====================
160 [..]
161 A DMA1 request can be generated when an external trigger (but not a software trigger)
162 occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
163 DMA requests are mapped as following:
164 (#) When DMAMUX is NOT present:
165 DMA1 requests are mapped as following:
166 (+) DAC channel1 mapped on DMA1 request 6 / channel3
167 (+) DAC channel2 mapped on DMA1 request 5 / channel4
168 DMA2 requests are mapped as following:
169 (+) DAC channel1 mapped on DMA2 request 3 / channel4
170 (+) DAC channel2 mapped on DMA2 request 3 / channel5
171 (#) When DMAMUX is present:
172 (+) DAC channel1 mapped on DMA1/DMA2 request 6 (can be any DMA channel)
173 (+) DAC channel2 mapped on DMA1/DMA2 request 7 (can be any DMA channel)
174
175 *** High frequency interface mode ***
176 =====================================
177 [..]
178 The high frequency interface informs DAC instance about the bus frequency in use.
179 It is mandatory information for DAC (as internal timing of DAC is bus frequency dependent)
180 provided thanks to parameter DAC_HighFrequency handled in HAL_DAC_ConfigChannel () function.
181 Use of DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC value of DAC_HighFrequency is recommended
182 function figured out the correct setting.
183 The high frequency mode is same for all converters of a same DAC instance. Either same
184 parameter DAC_HighFrequency is used for all DAC converters or again self
185 DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC detection parameter.
186
187 [..]
188 (@) For Dual mode and specific signal (Triangle and noise) generation please
189 refer to Extended Features Driver description
190
191 ##### How to use this driver #####
192 ==============================================================================
193 [..]
194 (+) DAC APB clock must be enabled to get write access to DAC
195 registers using HAL_DAC_Init()
196 (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
197 (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
198 (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
199
200 *** Calibration mode IO operation ***
201 ======================================
202 [..]
203 (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
204 (+) Run the calibration using HAL_DACEx_SelfCalibrate()
205 (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
206
207 *** Polling mode IO operation ***
208 =================================
209 [..]
210 (+) Start the DAC peripheral using HAL_DAC_Start()
211 (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
212 (+) Stop the DAC peripheral using HAL_DAC_Stop()
213
214 *** DMA mode IO operation ***
215 ==============================
216 [..]
217 (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
218 of data to be transferred at each end of conversion
219 First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
220 (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
221 function is executed and user can add his own code by customization of function pointer
222 HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
223 (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
224 function is executed and user can add his own code by customization of function pointer
225 HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
226 (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
227 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
228 (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
229 HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
230 function is executed and user can add his own code by customization of function pointer
231 HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
232 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
233 (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
234
235 *** Callback registration ***
236 =============================================
237 [..]
238 The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
239 allows the user to configure dynamically the driver callbacks.
240
241 Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
242 it allows to register following callbacks:
243 (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
244 (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
245 (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
246 (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
247 (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
248 (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
249 (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
250 (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
251 (+) MspInitCallback : DAC MspInit.
252 (+) MspDeInitCallback : DAC MspdeInit.
253 This function takes as parameters the HAL peripheral handle, the Callback ID
254 and a pointer to the user callback function.
255
256 Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
257 weak (surcharged) function. It allows to reset following callbacks:
258 (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
259 (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
260 (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
261 (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
262 (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
263 (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
264 (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
265 (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
266 (+) MspInitCallback : DAC MspInit.
267 (+) MspDeInitCallback : DAC MspdeInit.
268 (+) All Callbacks
269 This function) takes as parameters the HAL peripheral handle and the Callback ID.
270
271 By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
272 all callbacks are reset to the corresponding legacy weak (surcharged) functions.
273 Exception done for MspInit and MspDeInit callbacks that are respectively
274 reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
275 and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
276 If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
277 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
278
279 Callbacks can be registered/unregistered in READY state only.
280 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
281 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
282 during the Init/DeInit.
283 In that case first register the MspInit/MspDeInit user callbacks
284 using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
285 or @ref HAL_DAC_Init function.
286
287 When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
288 not defined, the callback registering feature is not available
289 and weak (surcharged) callbacks are used.
290
291 *** DAC HAL driver macros list ***
292 =============================================
293 [..]
294 Below the list of most used macros in DAC HAL driver.
295
296 (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
297 (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
298 (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
299 (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
300
301 [..]
302 (@) You can refer to the DAC HAL driver header file for more useful macros
303
304 @endverbatim
305 ******************************************************************************
306 * @attention
307 *
308 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
309 * All rights reserved.</center></h2>
310 *
311 * This software component is licensed by ST under BSD 3-Clause license,
312 * the "License"; You may not use this file except in compliance with the
313 * License. You may obtain a copy of the License at:
314 * opensource.org/licenses/BSD-3-Clause
315 *
316 ******************************************************************************
317 */
318
319 /* Includes ------------------------------------------------------------------*/
320 #include "stm32l4xx_hal.h"
321
322 /** @addtogroup STM32L4xx_HAL_Driver
323 * @{
324 */
325
326 #ifdef HAL_DAC_MODULE_ENABLED
327 #if defined(DAC1)
328
329 /** @defgroup DAC DAC
330 * @brief DAC driver modules
331 * @{
332 */
333
334 /* Private typedef -----------------------------------------------------------*/
335 /* Private define ------------------------------------------------------------*/
336 /* Private constants ---------------------------------------------------------*/
337 /** @addtogroup DAC_Private_Constants DAC Private Constants
338 * @{
339 */
340 #define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */
341 #define HFSEL_ENABLE_THRESHOLD_80MHZ 80000000U /* 80 MHz */
342
343 /**
344 * @}
345 */
346
347 /* Private macro -------------------------------------------------------------*/
348 /* Private variables ---------------------------------------------------------*/
349 /* Private function prototypes -----------------------------------------------*/
350 /* Exported functions -------------------------------------------------------*/
351
352 /** @defgroup DAC_Exported_Functions DAC Exported Functions
353 * @{
354 */
355
356 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
357 * @brief Initialization and Configuration functions
358 *
359 @verbatim
360 ==============================================================================
361 ##### Initialization and de-initialization functions #####
362 ==============================================================================
363 [..] This section provides functions allowing to:
364 (+) Initialize and configure the DAC.
365 (+) De-initialize the DAC.
366
367 @endverbatim
368 * @{
369 */
370
371 /**
372 * @brief Initialize the DAC peripheral according to the specified parameters
373 * in the DAC_InitStruct and initialize the associated handle.
374 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
375 * the configuration information for the specified DAC.
376 * @retval HAL status
377 */
HAL_DAC_Init(DAC_HandleTypeDef * hdac)378 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
379 {
380 /* Check DAC handle */
381 if (hdac == NULL)
382 {
383 return HAL_ERROR;
384 }
385 /* Check the parameters */
386 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
387
388 if (hdac->State == HAL_DAC_STATE_RESET)
389 {
390 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
391 /* Init the DAC Callback settings */
392 hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
393 hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
394 hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
395 hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
396
397 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
398 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \
399 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
400 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
401 hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
402 hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
403 hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
404 hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
405 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
406 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
407 /* STM32L4P5xx STM32L4Q5xx */
408 /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */
409
410 if (hdac->MspInitCallback == NULL)
411 {
412 hdac->MspInitCallback = HAL_DAC_MspInit;
413 }
414 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
415
416 /* Allocate lock resource and initialize it */
417 hdac->Lock = HAL_UNLOCKED;
418
419 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
420 /* Init the low level hardware */
421 hdac->MspInitCallback(hdac);
422 #else
423 /* Init the low level hardware */
424 HAL_DAC_MspInit(hdac);
425 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
426 }
427
428 /* Initialize the DAC state*/
429 hdac->State = HAL_DAC_STATE_BUSY;
430
431 /* Set DAC error code to none */
432 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
433
434 /* Initialize the DAC state*/
435 hdac->State = HAL_DAC_STATE_READY;
436
437 /* Return function status */
438 return HAL_OK;
439 }
440
441 /**
442 * @brief Deinitialize the DAC peripheral registers to their default reset values.
443 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
444 * the configuration information for the specified DAC.
445 * @retval HAL status
446 */
HAL_DAC_DeInit(DAC_HandleTypeDef * hdac)447 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
448 {
449 /* Check DAC handle */
450 if (hdac == NULL)
451 {
452 return HAL_ERROR;
453 }
454
455 /* Check the parameters */
456 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
457
458 /* Change DAC state */
459 hdac->State = HAL_DAC_STATE_BUSY;
460
461 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
462 if (hdac->MspDeInitCallback == NULL)
463 {
464 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
465 }
466 /* DeInit the low level hardware */
467 hdac->MspDeInitCallback(hdac);
468 #else
469 /* DeInit the low level hardware */
470 HAL_DAC_MspDeInit(hdac);
471 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
472
473 /* Set DAC error code to none */
474 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
475
476 /* Change DAC state */
477 hdac->State = HAL_DAC_STATE_RESET;
478
479 /* Release Lock */
480 __HAL_UNLOCK(hdac);
481
482 /* Return function status */
483 return HAL_OK;
484 }
485
486 /**
487 * @brief Initialize the DAC MSP.
488 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
489 * the configuration information for the specified DAC.
490 * @retval None
491 */
HAL_DAC_MspInit(DAC_HandleTypeDef * hdac)492 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac)
493 {
494 /* Prevent unused argument(s) compilation warning */
495 UNUSED(hdac);
496
497 /* NOTE : This function should not be modified, when the callback is needed,
498 the HAL_DAC_MspInit could be implemented in the user file
499 */
500 }
501
502 /**
503 * @brief DeInitialize the DAC MSP.
504 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
505 * the configuration information for the specified DAC.
506 * @retval None
507 */
HAL_DAC_MspDeInit(DAC_HandleTypeDef * hdac)508 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
509 {
510 /* Prevent unused argument(s) compilation warning */
511 UNUSED(hdac);
512
513 /* NOTE : This function should not be modified, when the callback is needed,
514 the HAL_DAC_MspDeInit could be implemented in the user file
515 */
516 }
517
518 /**
519 * @}
520 */
521
522 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
523 * @brief IO operation functions
524 *
525 @verbatim
526 ==============================================================================
527 ##### IO operation functions #####
528 ==============================================================================
529 [..] This section provides functions allowing to:
530 (+) Start conversion.
531 (+) Stop conversion.
532 (+) Start conversion and enable DMA transfer.
533 (+) Stop conversion and disable DMA transfer.
534 (+) Get result of conversion.
535
536 @endverbatim
537 * @{
538 */
539
540 /**
541 * @brief Enables DAC and starts conversion of channel.
542 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
543 * the configuration information for the specified DAC.
544 * @param Channel The selected DAC channel.
545 * This parameter can be one of the following values:
546 * @arg DAC_CHANNEL_1: DAC Channel1 selected
547 * @arg DAC_CHANNEL_2: DAC Channel2 selected (when supported)
548 * @retval HAL status
549 */
HAL_DAC_Start(DAC_HandleTypeDef * hdac,uint32_t Channel)550 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
551 {
552 /* Check the parameters */
553 assert_param(IS_DAC_CHANNEL(Channel));
554
555 /* Process locked */
556 __HAL_LOCK(hdac);
557
558 /* Change DAC state */
559 hdac->State = HAL_DAC_STATE_BUSY;
560
561 /* Enable the Peripheral */
562 __HAL_DAC_ENABLE(hdac, Channel);
563
564 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
565 if (Channel == DAC_CHANNEL_1)
566 {
567 /* Check if software trigger enabled */
568 if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
569 {
570 /* Enable the selected DAC software conversion */
571 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
572 }
573 }
574 else
575 {
576 /* Check if software trigger enabled */
577 if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
578 {
579 /* Enable the selected DAC software conversion*/
580 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
581 }
582 }
583
584 #endif /* STM32L4P5xx STM32L4Q5xx STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */
585
586 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
587 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
588 if(Channel == DAC_CHANNEL_1)
589 {
590 /* Check if software trigger enabled */
591 if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_CR_TEN1)
592 {
593 /* Enable the selected DAC software conversion */
594 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
595 }
596 }
597 else
598 {
599 /* Check if software trigger enabled */
600 if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == DAC_CR_TEN2)
601 {
602 /* Enable the selected DAC software conversion*/
603 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
604 }
605 }
606 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
607 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
608
609
610 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
611 /* Check if software trigger enabled */
612 if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
613 {
614 /* Enable the selected DAC software conversion */
615 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
616 }
617 #endif /* STM32L451xx STM32L452xx STM32L462xx */
618 /* Change DAC state */
619 hdac->State = HAL_DAC_STATE_READY;
620
621 /* Process unlocked */
622 __HAL_UNLOCK(hdac);
623
624 /* Return function status */
625 return HAL_OK;
626 }
627
628 /**
629 * @brief Disables DAC and stop conversion of channel.
630 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
631 * the configuration information for the specified DAC.
632 * @param Channel The selected DAC channel.
633 * This parameter can be one of the following values:
634 * @arg DAC_CHANNEL_1: DAC Channel1 selected
635 * @arg DAC_CHANNEL_2: DAC Channel2 selected
636 * @retval HAL status
637 */
HAL_DAC_Stop(DAC_HandleTypeDef * hdac,uint32_t Channel)638 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
639 {
640 /* Check the parameters */
641 assert_param(IS_DAC_CHANNEL(Channel));
642
643 /* Disable the Peripheral */
644 __HAL_DAC_DISABLE(hdac, Channel);
645
646 /* Change DAC state */
647 hdac->State = HAL_DAC_STATE_READY;
648
649 /* Return function status */
650 return HAL_OK;
651 }
652
653 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
654 /**
655 * @brief Enables DAC and starts conversion of channel.
656 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
657 * the configuration information for the specified DAC.
658 * @param Channel The selected DAC channel.
659 * This parameter can be one of the following values:
660 * @arg DAC_CHANNEL_1: DAC Channel1 selected
661 * @param pData The destination peripheral Buffer address.
662 * @param Length The length of data to be transferred from memory to DAC peripheral
663 * @param Alignment Specifies the data alignment for DAC channel.
664 * This parameter can be one of the following values:
665 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
666 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
667 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
668 * @retval HAL status
669 */
HAL_DAC_Start_DMA(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t * pData,uint32_t Length,uint32_t Alignment)670 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
671 uint32_t Alignment)
672 {
673 HAL_StatusTypeDef status;
674 uint32_t tmpreg = 0U;
675
676 /* Check the parameters */
677 assert_param(IS_DAC_CHANNEL(Channel));
678 assert_param(IS_DAC_ALIGN(Alignment));
679
680 /* Process locked */
681 __HAL_LOCK(hdac);
682
683 /* Change DAC state */
684 hdac->State = HAL_DAC_STATE_BUSY;
685
686 /* Set the DMA transfer complete callback for channel1 */
687 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
688
689 /* Set the DMA half transfer complete callback for channel1 */
690 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
691
692 /* Set the DMA error callback for channel1 */
693 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
694
695 /* Enable the selected DAC channel1 DMA request */
696 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
697
698 /* Case of use of channel 1 */
699 switch (Alignment)
700 {
701 case DAC_ALIGN_12B_R:
702 /* Get DHR12R1 address */
703 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
704 break;
705 case DAC_ALIGN_12B_L:
706 /* Get DHR12L1 address */
707 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
708 break;
709 case DAC_ALIGN_8B_R:
710 /* Get DHR8R1 address */
711 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
712 break;
713 default:
714 break;
715 }
716
717 /* Enable the DMA channel */
718 /* Enable the DAC DMA underrun interrupt */
719 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
720
721 /* Enable the DMA channel */
722 status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
723
724 /* Process Unlocked */
725 __HAL_UNLOCK(hdac);
726
727 if (status == HAL_OK)
728 {
729 /* Enable the Peripheral */
730 __HAL_DAC_ENABLE(hdac, Channel);
731 }
732 else
733 {
734 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
735 }
736
737 /* Return function status */
738 return status;
739 }
740 #endif /* STM32L451xx STM32L452xx STM32L462xx */
741
742 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
743 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \
744 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
745 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
746
747 /**
748 * @brief Enables DAC and starts conversion of channel.
749 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
750 * the configuration information for the specified DAC.
751 * @param Channel The selected DAC channel.
752 * This parameter can be one of the following values:
753 * @arg DAC_CHANNEL_1: DAC Channel1 selected
754 * @arg DAC_CHANNEL_2: DAC Channel2 selected
755 * @param pData The destination peripheral Buffer address.
756 * @param Length The length of data to be transferred from memory to DAC peripheral
757 * @param Alignment Specifies the data alignment for DAC channel.
758 * This parameter can be one of the following values:
759 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
760 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
761 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
762 * @retval HAL status
763 */
HAL_DAC_Start_DMA(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t * pData,uint32_t Length,uint32_t Alignment)764 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
765 uint32_t Alignment)
766 {
767 HAL_StatusTypeDef status;
768 uint32_t tmpreg = 0U;
769
770 /* Check the parameters */
771 assert_param(IS_DAC_CHANNEL(Channel));
772 assert_param(IS_DAC_ALIGN(Alignment));
773
774 /* Process locked */
775 __HAL_LOCK(hdac);
776
777 /* Change DAC state */
778 hdac->State = HAL_DAC_STATE_BUSY;
779
780 if (Channel == DAC_CHANNEL_1)
781 {
782 /* Set the DMA transfer complete callback for channel1 */
783 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
784
785 /* Set the DMA half transfer complete callback for channel1 */
786 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
787
788 /* Set the DMA error callback for channel1 */
789 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
790
791 /* Enable the selected DAC channel1 DMA request */
792 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
793
794 /* Case of use of channel 1 */
795 switch (Alignment)
796 {
797 case DAC_ALIGN_12B_R:
798 /* Get DHR12R1 address */
799 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
800 break;
801 case DAC_ALIGN_12B_L:
802 /* Get DHR12L1 address */
803 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
804 break;
805 case DAC_ALIGN_8B_R:
806 /* Get DHR8R1 address */
807 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
808 break;
809 default:
810 break;
811 }
812 }
813 else
814 {
815 /* Set the DMA transfer complete callback for channel2 */
816 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
817
818 /* Set the DMA half transfer complete callback for channel2 */
819 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
820
821 /* Set the DMA error callback for channel2 */
822 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
823
824 /* Enable the selected DAC channel2 DMA request */
825 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
826
827 /* Case of use of channel 2 */
828 switch (Alignment)
829 {
830 case DAC_ALIGN_12B_R:
831 /* Get DHR12R2 address */
832 tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
833 break;
834 case DAC_ALIGN_12B_L:
835 /* Get DHR12L2 address */
836 tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
837 break;
838 case DAC_ALIGN_8B_R:
839 /* Get DHR8R2 address */
840 tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
841 break;
842 default:
843 break;
844 }
845 }
846
847 /* Enable the DMA channel */
848 if (Channel == DAC_CHANNEL_1)
849 {
850 /* Enable the DAC DMA underrun interrupt */
851 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
852
853 /* Enable the DMA channel */
854 status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
855 }
856 else
857 {
858 /* Enable the DAC DMA underrun interrupt */
859 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
860
861 /* Enable the DMA channel */
862 status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
863 }
864
865 /* Process Unlocked */
866 __HAL_UNLOCK(hdac);
867
868 if (status == HAL_OK)
869 {
870 /* Enable the Peripheral */
871 __HAL_DAC_ENABLE(hdac, Channel);
872 }
873 else
874 {
875 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
876 }
877
878 /* Return function status */
879 return status;
880 }
881 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
882 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
883 /* STM32L4P5xx STM32L4Q5xx */
884 /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */
885
886 /**
887 * @brief Disables DAC and stop conversion of channel.
888 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
889 * the configuration information for the specified DAC.
890 * @param Channel The selected DAC channel.
891 * This parameter can be one of the following values:
892 * @arg DAC_CHANNEL_1: DAC Channel1 selected
893 * @arg DAC_CHANNEL_2: DAC Channel2 selected
894 * @retval HAL status
895 */
HAL_DAC_Stop_DMA(DAC_HandleTypeDef * hdac,uint32_t Channel)896 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
897 {
898 HAL_StatusTypeDef status;
899
900 /* Check the parameters */
901 assert_param(IS_DAC_CHANNEL(Channel));
902
903 /* Disable the selected DAC channel DMA request */
904 hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));
905
906 /* Disable the Peripheral */
907 __HAL_DAC_DISABLE(hdac, Channel);
908
909 /* Disable the DMA channel */
910 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
911 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \
912 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
913 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
914 /* Channel1 is used */
915 if (Channel == DAC_CHANNEL_1)
916 {
917 /* Disable the DMA channel */
918 status = HAL_DMA_Abort(hdac->DMA_Handle1);
919
920 /* Disable the DAC DMA underrun interrupt */
921 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
922 }
923 else /* Channel2 is used for */
924 {
925 /* Disable the DMA channel */
926 status = HAL_DMA_Abort(hdac->DMA_Handle2);
927
928 /* Disable the DAC DMA underrun interrupt */
929 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
930 }
931 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
932 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
933 /* STM32L4P5xx STM32L4Q5xx */
934 /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */
935
936 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
937 /* Disable the DMA channel */
938 status = HAL_DMA_Abort(hdac->DMA_Handle1);
939
940 /* Disable the DAC DMA underrun interrupt */
941 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
942 #endif /* STM32L451xx STM32L452xx STM32L462xx */
943
944 /* Check if DMA Channel effectively disabled */
945 if (status != HAL_OK)
946 {
947 /* Update DAC state machine to error */
948 hdac->State = HAL_DAC_STATE_ERROR;
949 }
950 else
951 {
952 /* Change DAC state */
953 hdac->State = HAL_DAC_STATE_READY;
954 }
955
956 /* Return function status */
957 return status;
958 }
959
960 /* DAC channel 2 is available on top of DAC channel 1 in */
961 /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
962 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
963
964 /**
965 * @brief Handles DAC interrupt request
966 * This function uses the interruption of DMA
967 * underrun.
968 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
969 * the configuration information for the specified DAC.
970 * @retval None
971 */
HAL_DAC_IRQHandler(DAC_HandleTypeDef * hdac)972 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
973 {
974 if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
975 {
976 /* Check underrun flag of DAC channel 1 */
977 if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
978 {
979 /* Change DAC state to error state */
980 hdac->State = HAL_DAC_STATE_ERROR;
981
982 /* Set DAC error code to chanel1 DMA underrun error */
983 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
984
985 /* Clear the underrun flag */
986 __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
987
988 /* Disable the selected DAC channel1 DMA request */
989 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
990
991 /* Error callback */
992 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
993 hdac->DMAUnderrunCallbackCh1(hdac);
994 #else
995 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
996 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
997 }
998 }
999 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
1000 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \
1001 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
1002 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
1003 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
1004 {
1005 /* Check underrun flag of DAC channel 2 */
1006 if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
1007 {
1008 /* Change DAC state to error state */
1009 hdac->State = HAL_DAC_STATE_ERROR;
1010
1011 /* Set DAC error code to channel2 DMA underrun error */
1012 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
1013
1014 /* Clear the underrun flag */
1015 __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
1016
1017 /* Disable the selected DAC channel2 DMA request */
1018 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
1019
1020 /* Error callback */
1021 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1022 hdac->DMAUnderrunCallbackCh2(hdac);
1023 #else
1024 HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
1025 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1026 }
1027 }
1028 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
1029 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
1030 /* STM32L4P5xx STM32L4Q5xx */
1031 /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */
1032 }
1033
1034 /**
1035 * @brief Set the specified data holding register value for DAC channel.
1036 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1037 * the configuration information for the specified DAC.
1038 * @param Channel The selected DAC channel.
1039 * This parameter can be one of the following values:
1040 * @arg DAC_CHANNEL_1: DAC Channel1 selected
1041 * @arg DAC_CHANNEL_2: DAC Channel2 selected
1042 * @param Alignment Specifies the data alignment.
1043 * This parameter can be one of the following values:
1044 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
1045 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
1046 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
1047 * @param Data Data to be loaded in the selected data holding register.
1048 * @retval HAL status
1049 */
HAL_DAC_SetValue(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t Alignment,uint32_t Data)1050 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
1051 {
1052 __IO uint32_t tmp = 0;
1053
1054 /* Check the parameters */
1055 assert_param(IS_DAC_CHANNEL(Channel));
1056 assert_param(IS_DAC_ALIGN(Alignment));
1057 assert_param(IS_DAC_DATA(Data));
1058
1059 tmp = (uint32_t)hdac->Instance;
1060 if (Channel == DAC_CHANNEL_1)
1061 {
1062 tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
1063 }
1064 else
1065 {
1066 tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
1067 }
1068
1069 /* Set the DAC channel selected data holding register */
1070 *(__IO uint32_t *) tmp = Data;
1071
1072 /* Return function status */
1073 return HAL_OK;
1074 }
1075
1076 /**
1077 * @brief Conversion complete callback in non-blocking mode for Channel1
1078 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1079 * the configuration information for the specified DAC.
1080 * @retval None
1081 */
HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef * hdac)1082 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac)
1083 {
1084 /* Prevent unused argument(s) compilation warning */
1085 UNUSED(hdac);
1086
1087 /* NOTE : This function should not be modified, when the callback is needed,
1088 the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
1089 */
1090 }
1091
1092 /**
1093 * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1
1094 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1095 * the configuration information for the specified DAC.
1096 * @retval None
1097 */
HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef * hdac)1098 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac)
1099 {
1100 /* Prevent unused argument(s) compilation warning */
1101 UNUSED(hdac);
1102
1103 /* NOTE : This function should not be modified, when the callback is needed,
1104 the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
1105 */
1106 }
1107
1108 /**
1109 * @brief Error DAC callback for Channel1.
1110 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1111 * the configuration information for the specified DAC.
1112 * @retval None
1113 */
HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef * hdac)1114 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
1115 {
1116 /* Prevent unused argument(s) compilation warning */
1117 UNUSED(hdac);
1118
1119 /* NOTE : This function should not be modified, when the callback is needed,
1120 the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
1121 */
1122 }
1123
1124 /**
1125 * @brief DMA underrun DAC callback for channel1.
1126 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1127 * the configuration information for the specified DAC.
1128 * @retval None
1129 */
HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef * hdac)1130 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
1131 {
1132 /* Prevent unused argument(s) compilation warning */
1133 UNUSED(hdac);
1134
1135 /* NOTE : This function should not be modified, when the callback is needed,
1136 the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
1137 */
1138 }
1139
1140 /**
1141 * @}
1142 */
1143
1144 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
1145 * @brief Peripheral Control functions
1146 *
1147 @verbatim
1148 ==============================================================================
1149 ##### Peripheral Control functions #####
1150 ==============================================================================
1151 [..] This section provides functions allowing to:
1152 (+) Configure channels.
1153 (+) Set the specified data holding register value for DAC channel.
1154
1155 @endverbatim
1156 * @{
1157 */
1158
1159 /**
1160 * @brief Returns the last data output value of the selected DAC channel.
1161 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1162 * the configuration information for the specified DAC.
1163 * @param Channel The selected DAC channel.
1164 * This parameter can be one of the following values:
1165 * @arg DAC_CHANNEL_1: DAC Channel1 selected
1166 * @arg DAC_CHANNEL_2: DAC Channel2 selected
1167 * @retval The selected DAC channel data output value.
1168 */
HAL_DAC_GetValue(DAC_HandleTypeDef * hdac,uint32_t Channel)1169 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
1170 {
1171 /* Check the parameters */
1172 assert_param(IS_DAC_CHANNEL(Channel));
1173
1174 /* Returns the DAC channel data output register value */
1175 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
1176 /* Prevent unused argument(s) compilation warning if no assert_param check */
1177 UNUSED(Channel);
1178
1179 return hdac->Instance->DOR1;
1180 #endif /* STM32L451xx STM32L452xx STM32L462xx */
1181
1182 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
1183 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \
1184 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
1185 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
1186 if(Channel == DAC_CHANNEL_1)
1187 {
1188 return hdac->Instance->DOR1;
1189 }
1190 else
1191 {
1192 return hdac->Instance->DOR2;
1193 }
1194 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
1195 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
1196 /* STM32L4P5xx STM32L4Q5xx */
1197 /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */
1198 }
1199
1200 /**
1201 * @brief Configures the selected DAC channel.
1202 * @note By calling this function, the high frequency interface mode (HFSEL bits)
1203 * will be set. This parameter scope is the DAC instance. As the function
1204 * is called for each channel, the @ref DAC_HighFrequency of @arg sConfig
1205 * must be the same at each call.
1206 * (or DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC self detect).
1207 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1208 * the configuration information for the specified DAC.
1209 * @param sConfig DAC configuration structure.
1210 * @param Channel The selected DAC channel.
1211 * This parameter can be one of the following values:
1212 * @arg DAC_CHANNEL_1: DAC Channel1 selected
1213 * @arg DAC_CHANNEL_2: DAC Channel2 selected (Whenever present)
1214 * @retval HAL status
1215 */
HAL_DAC_ConfigChannel(DAC_HandleTypeDef * hdac,DAC_ChannelConfTypeDef * sConfig,uint32_t Channel)1216 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
1217 {
1218 uint32_t tmpreg1;
1219 uint32_t tmpreg2;
1220 uint32_t tickstart = 0U;
1221 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
1222 uint32_t hclkfreq;
1223 #endif /* STM32L4P5xx STM32L4Q5xx STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */
1224
1225 /* Check the DAC parameters */
1226 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
1227 assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency));
1228 #endif /* STM32L4P5xx STM32L4Q5xx STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */
1229 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
1230 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
1231 assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
1232 assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
1233 if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
1234 {
1235 assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
1236 }
1237 assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
1238 if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
1239 {
1240 assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
1241 assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
1242 assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
1243 }
1244 assert_param(IS_DAC_CHANNEL(Channel));
1245
1246 /* Process locked */
1247 __HAL_LOCK(hdac);
1248
1249 /* Change DAC state */
1250 hdac->State = HAL_DAC_STATE_BUSY;
1251
1252 if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
1253 /* Sample on old configuration */
1254 {
1255 /* SampleTime */
1256 if (Channel == DAC_CHANNEL_1)
1257 {
1258 /* Get timeout */
1259 tickstart = HAL_GetTick();
1260
1261 /* SHSR1 can be written when BWST1 is cleared */
1262 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
1263 {
1264 /* Check for the Timeout */
1265 if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
1266 {
1267 /* Update error code */
1268 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
1269
1270 /* Change the DMA state */
1271 hdac->State = HAL_DAC_STATE_TIMEOUT;
1272
1273 return HAL_TIMEOUT;
1274 }
1275 }
1276 HAL_Delay(1);
1277 hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
1278 }
1279 #if !defined (STM32L451xx) & !defined (STM32L452xx) & !defined (STM32L462xx)
1280 else /* Channel 2 */
1281 {
1282 /* SHSR2 can be written when BWST2 is cleared */
1283
1284 while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
1285 {
1286 /* Check for the Timeout */
1287 if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
1288 {
1289 /* Update error code */
1290 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
1291
1292 /* Change the DMA state */
1293 hdac->State = HAL_DAC_STATE_TIMEOUT;
1294
1295 return HAL_TIMEOUT;
1296 }
1297 }
1298 HAL_Delay(1U);
1299 hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
1300 }
1301 #endif /* STM32L451xx STM32L452xx STM32L462xx */
1302
1303 /* HoldTime */
1304 MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
1305 /* RefreshTime */
1306 MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
1307 }
1308
1309 if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
1310 /* USER TRIMMING */
1311 {
1312 /* Get the DAC CCR value */
1313 tmpreg1 = hdac->Instance->CCR;
1314 /* Clear trimming value */
1315 tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL));
1316 /* Configure for the selected trimming offset */
1317 tmpreg2 = sConfig->DAC_TrimmingValue;
1318 /* Calculate CCR register value depending on DAC_Channel */
1319 tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
1320 /* Write to DAC CCR */
1321 hdac->Instance->CCR = tmpreg1;
1322 }
1323 /* else factory trimming is used (factory setting are available at reset)*/
1324 /* SW Nothing has nothing to do */
1325
1326 /* Get the DAC MCR value */
1327 tmpreg1 = hdac->Instance->MCR;
1328 /* Clear DAC_MCR_MODEx bits */
1329 tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
1330 /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
1331 tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral);
1332 /* Calculate MCR register value depending on DAC_Channel */
1333 tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
1334 /* Write to DAC MCR */
1335 hdac->Instance->MCR = tmpreg1;
1336
1337 /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
1338 CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
1339
1340 /* Get the DAC CR value */
1341 tmpreg1 = hdac->Instance->CR;
1342 /* Clear TENx, TSELx, WAVEx and MAMPx bits */
1343 tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
1344 /* Configure for the selected DAC channel: trigger */
1345 /* Set TSELx and TENx bits according to DAC_Trigger value */
1346 tmpreg2 = sConfig->DAC_Trigger;
1347 /* Calculate CR register value depending on DAC_Channel */
1348 tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
1349 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
1350 if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ == sConfig->DAC_HighFrequency)
1351 {
1352 tmpreg1 |= DAC_CR_HFSEL;
1353 }
1354 else
1355 {
1356 if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE == sConfig->DAC_HighFrequency)
1357 {
1358 tmpreg1 &= ~(DAC_CR_HFSEL);
1359 }
1360 else /* Automatic selection */
1361 {
1362 hclkfreq = HAL_RCC_GetHCLKFreq();
1363 if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ)
1364 {
1365 /* High frequency enable when HCLK frequency higher than 80 */
1366 tmpreg1 |= DAC_CR_HFSEL;
1367 }
1368 else
1369 {
1370 /* High frequency disable when HCLK frequency higher than 80 */
1371 tmpreg1 &= ~(DAC_CR_HFSEL);
1372 }
1373 }
1374 }
1375
1376 #endif /* STM32L4P5xx STM32L4Q5xx STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */
1377
1378 /* Write to DAC CR */
1379 hdac->Instance->CR = tmpreg1;
1380 /* Disable wave generation */
1381 hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL));
1382
1383 /* Change DAC state */
1384 hdac->State = HAL_DAC_STATE_READY;
1385
1386 /* Process unlocked */
1387 __HAL_UNLOCK(hdac);
1388
1389 /* Return function status */
1390 return HAL_OK;
1391 }
1392
1393 /**
1394 * @}
1395 */
1396
1397 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
1398 * @brief Peripheral State and Errors functions
1399 *
1400 @verbatim
1401 ==============================================================================
1402 ##### Peripheral State and Errors functions #####
1403 ==============================================================================
1404 [..]
1405 This subsection provides functions allowing to
1406 (+) Check the DAC state.
1407 (+) Check the DAC Errors.
1408
1409 @endverbatim
1410 * @{
1411 */
1412
1413 /**
1414 * @brief return the DAC handle state
1415 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1416 * the configuration information for the specified DAC.
1417 * @retval HAL state
1418 */
HAL_DAC_GetState(DAC_HandleTypeDef * hdac)1419 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
1420 {
1421 /* Return DAC handle state */
1422 return hdac->State;
1423 }
1424
1425
1426 /**
1427 * @brief Return the DAC error code
1428 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1429 * the configuration information for the specified DAC.
1430 * @retval DAC Error Code
1431 */
HAL_DAC_GetError(DAC_HandleTypeDef * hdac)1432 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
1433 {
1434 return hdac->ErrorCode;
1435 }
1436
1437 /**
1438 * @}
1439 */
1440
1441 /**
1442 * @}
1443 */
1444
1445 /** @addtogroup DAC_Exported_Functions
1446 * @{
1447 */
1448
1449 /** @addtogroup DAC_Exported_Functions_Group1
1450 * @{
1451 */
1452 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1453 /**
1454 * @brief Register a User DAC Callback
1455 * To be used instead of the weak (surcharged) predefined callback
1456 * @param hdac DAC handle
1457 * @param CallbackID ID of the callback to be registered
1458 * This parameter can be one of the following values:
1459 * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
1460 * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
1461 * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
1462 * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
1463 * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
1464 * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
1465 * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
1466 * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
1467 * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
1468 * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
1469 * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
1470 *
1471 * @param pCallback pointer to the Callback function
1472 * @retval status
1473 */
HAL_DAC_RegisterCallback(DAC_HandleTypeDef * hdac,HAL_DAC_CallbackIDTypeDef CallbackID,pDAC_CallbackTypeDef pCallback)1474 HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
1475 pDAC_CallbackTypeDef pCallback)
1476 {
1477 HAL_StatusTypeDef status = HAL_OK;
1478
1479 if (pCallback == NULL)
1480 {
1481 /* Update the error code */
1482 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1483 return HAL_ERROR;
1484 }
1485
1486 /* Process locked */
1487 __HAL_LOCK(hdac);
1488
1489 if (hdac->State == HAL_DAC_STATE_READY)
1490 {
1491 switch (CallbackID)
1492 {
1493 case HAL_DAC_CH1_COMPLETE_CB_ID :
1494 hdac->ConvCpltCallbackCh1 = pCallback;
1495 break;
1496 case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
1497 hdac->ConvHalfCpltCallbackCh1 = pCallback;
1498 break;
1499 case HAL_DAC_CH1_ERROR_ID :
1500 hdac->ErrorCallbackCh1 = pCallback;
1501 break;
1502 case HAL_DAC_CH1_UNDERRUN_CB_ID :
1503 hdac->DMAUnderrunCallbackCh1 = pCallback;
1504 break;
1505 case HAL_DAC_CH2_COMPLETE_CB_ID :
1506 hdac->ConvCpltCallbackCh2 = pCallback;
1507 break;
1508 case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
1509 hdac->ConvHalfCpltCallbackCh2 = pCallback;
1510 break;
1511 case HAL_DAC_CH2_ERROR_ID :
1512 hdac->ErrorCallbackCh2 = pCallback;
1513 break;
1514 case HAL_DAC_CH2_UNDERRUN_CB_ID :
1515 hdac->DMAUnderrunCallbackCh2 = pCallback;
1516 break;
1517 case HAL_DAC_MSPINIT_CB_ID :
1518 hdac->MspInitCallback = pCallback;
1519 break;
1520 case HAL_DAC_MSPDEINIT_CB_ID :
1521 hdac->MspDeInitCallback = pCallback;
1522 break;
1523 default :
1524 /* Update the error code */
1525 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1526 /* update return status */
1527 status = HAL_ERROR;
1528 break;
1529 }
1530 }
1531 else if (hdac->State == HAL_DAC_STATE_RESET)
1532 {
1533 switch (CallbackID)
1534 {
1535 case HAL_DAC_MSPINIT_CB_ID :
1536 hdac->MspInitCallback = pCallback;
1537 break;
1538 case HAL_DAC_MSPDEINIT_CB_ID :
1539 hdac->MspDeInitCallback = pCallback;
1540 break;
1541 default :
1542 /* Update the error code */
1543 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1544 /* update return status */
1545 status = HAL_ERROR;
1546 break;
1547 }
1548 }
1549 else
1550 {
1551 /* Update the error code */
1552 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1553 /* update return status */
1554 status = HAL_ERROR;
1555 }
1556
1557 /* Release Lock */
1558 __HAL_UNLOCK(hdac);
1559 return status;
1560 }
1561
1562 /**
1563 * @brief Unregister a User DAC Callback
1564 * DAC Callback is redirected to the weak (surcharged) predefined callback
1565 * @param hdac DAC handle
1566 * @param CallbackID ID of the callback to be unregistered
1567 * This parameter can be one of the following values:
1568 * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID
1569 * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
1570 * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
1571 * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
1572 * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
1573 * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
1574 * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
1575 * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
1576 * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
1577 * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
1578 * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks
1579 * @retval status
1580 */
HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef * hdac,HAL_DAC_CallbackIDTypeDef CallbackID)1581 HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
1582 {
1583 HAL_StatusTypeDef status = HAL_OK;
1584
1585 /* Process locked */
1586 __HAL_LOCK(hdac);
1587
1588 if (hdac->State == HAL_DAC_STATE_READY)
1589 {
1590 switch (CallbackID)
1591 {
1592 case HAL_DAC_CH1_COMPLETE_CB_ID :
1593 hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
1594 break;
1595 case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
1596 hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
1597 break;
1598 case HAL_DAC_CH1_ERROR_ID :
1599 hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
1600 break;
1601 case HAL_DAC_CH1_UNDERRUN_CB_ID :
1602 hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
1603 break;
1604 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
1605 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \
1606 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
1607 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
1608 case HAL_DAC_CH2_COMPLETE_CB_ID :
1609 hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
1610 break;
1611 case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
1612 hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
1613 break;
1614 case HAL_DAC_CH2_ERROR_ID :
1615 hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
1616 break;
1617 case HAL_DAC_CH2_UNDERRUN_CB_ID :
1618 hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
1619 break;
1620 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
1621 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
1622 /* STM32L4P5xx STM32L4Q5xx */
1623 /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */
1624 case HAL_DAC_MSPINIT_CB_ID :
1625 hdac->MspInitCallback = HAL_DAC_MspInit;
1626 break;
1627 case HAL_DAC_MSPDEINIT_CB_ID :
1628 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
1629 break;
1630 case HAL_DAC_ALL_CB_ID :
1631 hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
1632 hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
1633 hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
1634 hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
1635 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
1636 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \
1637 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
1638 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
1639 hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
1640 hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
1641 hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
1642 hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
1643 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
1644 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */
1645 /* STM32L4P5xx STM32L4Q5xx */
1646 /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */
1647 hdac->MspInitCallback = HAL_DAC_MspInit;
1648 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
1649 break;
1650 default :
1651 /* Update the error code */
1652 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1653 /* update return status */
1654 status = HAL_ERROR;
1655 break;
1656 }
1657 }
1658 else if (hdac->State == HAL_DAC_STATE_RESET)
1659 {
1660 switch (CallbackID)
1661 {
1662 case HAL_DAC_MSPINIT_CB_ID :
1663 hdac->MspInitCallback = HAL_DAC_MspInit;
1664 break;
1665 case HAL_DAC_MSPDEINIT_CB_ID :
1666 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
1667 break;
1668 default :
1669 /* Update the error code */
1670 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1671 /* update return status */
1672 status = HAL_ERROR;
1673 break;
1674 }
1675 }
1676 else
1677 {
1678 /* Update the error code */
1679 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1680 /* update return status */
1681 status = HAL_ERROR;
1682 }
1683
1684 /* Release Lock */
1685 __HAL_UNLOCK(hdac);
1686 return status;
1687 }
1688 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1689
1690 /**
1691 * @}
1692 */
1693
1694 /**
1695 * @}
1696 */
1697
1698 /** @addtogroup DAC_Private_Functions
1699 * @{
1700 */
1701
1702 /**
1703 * @brief DMA conversion complete callback.
1704 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1705 * the configuration information for the specified DMA module.
1706 * @retval None
1707 */
DAC_DMAConvCpltCh1(DMA_HandleTypeDef * hdma)1708 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
1709 {
1710 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1711
1712 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1713 hdac->ConvCpltCallbackCh1(hdac);
1714 #else
1715 HAL_DAC_ConvCpltCallbackCh1(hdac);
1716 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1717
1718 hdac->State = HAL_DAC_STATE_READY;
1719 }
1720
1721 /**
1722 * @brief DMA half transfer complete callback.
1723 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1724 * the configuration information for the specified DMA module.
1725 * @retval None
1726 */
DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef * hdma)1727 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
1728 {
1729 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1730 /* Conversion complete callback */
1731 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1732 hdac->ConvHalfCpltCallbackCh1(hdac);
1733 #else
1734 HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
1735 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1736 }
1737
1738 /**
1739 * @brief DMA error callback
1740 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1741 * the configuration information for the specified DMA module.
1742 * @retval None
1743 */
DAC_DMAErrorCh1(DMA_HandleTypeDef * hdma)1744 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
1745 {
1746 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1747
1748 /* Set DAC error code to DMA error */
1749 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
1750
1751 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1752 hdac->ErrorCallbackCh1(hdac);
1753 #else
1754 HAL_DAC_ErrorCallbackCh1(hdac);
1755 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1756
1757 hdac->State = HAL_DAC_STATE_READY;
1758 }
1759
1760 /**
1761 * @}
1762 */
1763
1764 /**
1765 * @}
1766 */
1767
1768 #endif /* DAC1 */
1769
1770 #endif /* HAL_DAC_MODULE_ENABLED */
1771
1772 /**
1773 * @}
1774 */
1775
1776 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1777