1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 The SPI HAL driver can be used as follows:
19
20 (#) Declare a SPI_HandleTypeDef handle structure, for example:
21 SPI_HandleTypeDef hspi;
22
23 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
24 (##) Enable the SPIx interface clock
25 (##) SPI pins configuration
26 (+++) Enable the clock for the SPI GPIOs
27 (+++) Configure these SPI pins as alternate function push-pull
28 (##) NVIC configuration if you need to use interrupt process
29 (+++) Configure the SPIx interrupt priority
30 (+++) Enable the NVIC SPI IRQ handle
31 (##) DMA Configuration if you need to use DMA process
32 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
33 (+++) Enable the DMAx clock
34 (+++) Configure the DMA handle parameters
35 (+++) Configure the DMA Tx or Rx Stream/Channel
36 (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
38
39 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
40 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
41
42 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
43 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
44 by calling the customized HAL_SPI_MspInit() API.
45 [..]
46 Circular mode restriction:
47 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
48 (##) Master 2Lines RxOnly
49 (##) Master 1Line Rx
50 (#) The CRC feature is not managed when the DMA circular mode is enabled
51 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
52 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
53 [..]
54 Master Receive mode restriction:
55 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
56 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
57 does not initiate a new transfer the following procedure has to be respected:
58 (##) HAL_SPI_DeInit()
59 (##) HAL_SPI_Init()
60 [..]
61 Callback registration:
62
63 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
64 allows the user to configure dynamically the driver callbacks.
65 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
66
67 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
68 (+) TxCpltCallback : SPI Tx Completed callback
69 (+) RxCpltCallback : SPI Rx Completed callback
70 (+) TxRxCpltCallback : SPI TxRx Completed callback
71 (+) TxHalfCpltCallback : SPI Tx Half Completed callback
72 (+) RxHalfCpltCallback : SPI Rx Half Completed callback
73 (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
74 (+) ErrorCallback : SPI Error callback
75 (+) AbortCpltCallback : SPI Abort callback
76 (+) MspInitCallback : SPI Msp Init callback
77 (+) MspDeInitCallback : SPI Msp DeInit callback
78 This function takes as parameters the HAL peripheral handle, the Callback ID
79 and a pointer to the user callback function.
80
81
82 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
83 weak function.
84 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
85 and the Callback ID.
86 This function allows to reset following callbacks:
87 (+) TxCpltCallback : SPI Tx Completed callback
88 (+) RxCpltCallback : SPI Rx Completed callback
89 (+) TxRxCpltCallback : SPI TxRx Completed callback
90 (+) TxHalfCpltCallback : SPI Tx Half Completed callback
91 (+) RxHalfCpltCallback : SPI Rx Half Completed callback
92 (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
93 (+) ErrorCallback : SPI Error callback
94 (+) AbortCpltCallback : SPI Abort callback
95 (+) MspInitCallback : SPI Msp Init callback
96 (+) MspDeInitCallback : SPI Msp DeInit callback
97
98 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
99 all callbacks are set to the corresponding weak functions:
100 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
101 Exception done for MspInit and MspDeInit functions that are
102 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
103 these callbacks are null (not registered beforehand).
104 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
105 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
106
107 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
108 Exception done MspInit/MspDeInit functions that can be registered/unregistered
109 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
110 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
111 Then, the user first registers the MspInit/MspDeInit user callbacks
112 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
113 or HAL_SPI_Init() function.
114
115 When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
116 not defined, the callback registering feature is not available
117 and weak (surcharged) callbacks are used.
118
119 [..]
120 Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
121 the following table resume the max SPI frequency reached with data size 8bits/16bits,
122 according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
123
124 @endverbatim
125
126 Additional table :
127
128 DataSize = SPI_DATASIZE_8BIT:
129 +----------------------------------------------------------------------------------------------+
130 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
131 | Process | Tranfert mode |---------------------|----------------------|----------------------|
132 | | | Master | Slave | Master | Slave | Master | Slave |
133 |==============================================================================================|
134 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
135 | X |----------------|----------|----------|-----------|----------|-----------|----------|
136 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
137 | R |----------------|----------|----------|-----------|----------|-----------|----------|
138 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
139 |=========|================|==========|==========|===========|==========|===========|==========|
140 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
141 | |----------------|----------|----------|-----------|----------|-----------|----------|
142 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
143 | X |----------------|----------|----------|-----------|----------|-----------|----------|
144 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
145 |=========|================|==========|==========|===========|==========|===========|==========|
146 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
147 | |----------------|----------|----------|-----------|----------|-----------|----------|
148 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
149 | X |----------------|----------|----------|-----------|----------|-----------|----------|
150 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
151 +----------------------------------------------------------------------------------------------+
152
153 DataSize = SPI_DATASIZE_16BIT:
154 +----------------------------------------------------------------------------------------------+
155 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
156 | Process | Tranfert mode |---------------------|----------------------|----------------------|
157 | | | Master | Slave | Master | Slave | Master | Slave |
158 |==============================================================================================|
159 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
160 | X |----------------|----------|----------|-----------|----------|-----------|----------|
161 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
162 | R |----------------|----------|----------|-----------|----------|-----------|----------|
163 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
164 |=========|================|==========|==========|===========|==========|===========|==========|
165 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
166 | |----------------|----------|----------|-----------|----------|-----------|----------|
167 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
168 | X |----------------|----------|----------|-----------|----------|-----------|----------|
169 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
170 |=========|================|==========|==========|===========|==========|===========|==========|
171 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
172 | |----------------|----------|----------|-----------|----------|-----------|----------|
173 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
174 | X |----------------|----------|----------|-----------|----------|-----------|----------|
175 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
176 +----------------------------------------------------------------------------------------------+
177 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
178 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
179 @note
180 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
181 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
182 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
183
184 ******************************************************************************
185 * @attention
186 *
187 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
188 * All rights reserved.</center></h2>
189 *
190 * This software component is licensed by ST under BSD 3-Clause license,
191 * the "License"; You may not use this file except in compliance with the
192 * License. You may obtain a copy of the License at:
193 * opensource.org/licenses/BSD-3-Clause
194 *
195 ******************************************************************************
196 */
197
198 /* Includes ------------------------------------------------------------------*/
199 #include "stm32l4xx_hal.h"
200
201 /** @addtogroup STM32L4xx_HAL_Driver
202 * @{
203 */
204
205 /** @defgroup SPI SPI
206 * @brief SPI HAL module driver
207 * @{
208 */
209 #ifdef HAL_SPI_MODULE_ENABLED
210
211 /* Private typedef -----------------------------------------------------------*/
212 /* Private defines -----------------------------------------------------------*/
213 /** @defgroup SPI_Private_Constants SPI Private Constants
214 * @{
215 */
216 #define SPI_DEFAULT_TIMEOUT 100U
217 /**
218 * @}
219 */
220
221 /* Private macros ------------------------------------------------------------*/
222 /* Private variables ---------------------------------------------------------*/
223 /* Private function prototypes -----------------------------------------------*/
224 /** @defgroup SPI_Private_Functions SPI Private Functions
225 * @{
226 */
227 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
228 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
229 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
230 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
231 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
232 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
233 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
234 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
235 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
236 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
237 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
238 uint32_t Timeout, uint32_t Tickstart);
239 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
240 uint32_t Timeout, uint32_t Tickstart);
241 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
242 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
243 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
244 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
245 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
246 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
247 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
248 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
249 #if (USE_SPI_CRC != 0U)
250 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
251 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
252 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
253 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
254 #endif /* USE_SPI_CRC */
255 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
256 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
257 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
258 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
259 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
260 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
261 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
262 /**
263 * @}
264 */
265
266 /* Exported functions --------------------------------------------------------*/
267 /** @defgroup SPI_Exported_Functions SPI Exported Functions
268 * @{
269 */
270
271 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
272 * @brief Initialization and Configuration functions
273 *
274 @verbatim
275 ===============================================================================
276 ##### Initialization and de-initialization functions #####
277 ===============================================================================
278 [..] This subsection provides a set of functions allowing to initialize and
279 de-initialize the SPIx peripheral:
280
281 (+) User must implement HAL_SPI_MspInit() function in which he configures
282 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
283
284 (+) Call the function HAL_SPI_Init() to configure the selected device with
285 the selected configuration:
286 (++) Mode
287 (++) Direction
288 (++) Data Size
289 (++) Clock Polarity and Phase
290 (++) NSS Management
291 (++) BaudRate Prescaler
292 (++) FirstBit
293 (++) TIMode
294 (++) CRC Calculation
295 (++) CRC Polynomial if CRC enabled
296 (++) CRC Length, used only with Data8 and Data16
297 (++) FIFO reception threshold
298
299 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
300 of the selected SPIx peripheral.
301
302 @endverbatim
303 * @{
304 */
305
306 /**
307 * @brief Initialize the SPI according to the specified parameters
308 * in the SPI_InitTypeDef and initialize the associated handle.
309 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
310 * the configuration information for SPI module.
311 * @retval HAL status
312 */
HAL_SPI_Init(SPI_HandleTypeDef * hspi)313 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
314 {
315 uint32_t frxth;
316
317 /* Check the SPI handle allocation */
318 if (hspi == NULL)
319 {
320 return HAL_ERROR;
321 }
322
323 /* Check the parameters */
324 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
325 assert_param(IS_SPI_MODE(hspi->Init.Mode));
326 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
327 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
328 assert_param(IS_SPI_NSS(hspi->Init.NSS));
329 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
330 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
331 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
332 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
333 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
334 {
335 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
336 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
337 }
338 #if (USE_SPI_CRC != 0U)
339 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
340 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
341 {
342 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
343 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
344 }
345 #else
346 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
347 #endif /* USE_SPI_CRC */
348
349 if (hspi->State == HAL_SPI_STATE_RESET)
350 {
351 /* Allocate lock resource and initialize it */
352 hspi->Lock = HAL_UNLOCKED;
353
354 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
355 /* Init the SPI Callback settings */
356 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
357 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
358 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
359 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
360 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
361 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
362 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
363 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
364
365 if (hspi->MspInitCallback == NULL)
366 {
367 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
368 }
369
370 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
371 hspi->MspInitCallback(hspi);
372 #else
373 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
374 HAL_SPI_MspInit(hspi);
375 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
376 }
377
378 hspi->State = HAL_SPI_STATE_BUSY;
379
380 /* Disable the selected SPI peripheral */
381 __HAL_SPI_DISABLE(hspi);
382
383 /* Align by default the rs fifo threshold on the data size */
384 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
385 {
386 frxth = SPI_RXFIFO_THRESHOLD_HF;
387 }
388 else
389 {
390 frxth = SPI_RXFIFO_THRESHOLD_QF;
391 }
392
393 /* CRC calculation is valid only for 16Bit and 8 Bit */
394 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
395 {
396 /* CRC must be disabled */
397 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
398 }
399
400 /* Align the CRC Length on the data size */
401 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
402 {
403 /* CRC Length aligned on the data size : value set by default */
404 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
405 {
406 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
407 }
408 else
409 {
410 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
411 }
412 }
413
414 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
415 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
416 Communication speed, First bit and CRC calculation state */
417 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
418 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
419 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
420 #if (USE_SPI_CRC != 0U)
421 /* Configure : CRC Length */
422 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
423 {
424 hspi->Instance->CR1 |= SPI_CR1_CRCL;
425 }
426 #endif /* USE_SPI_CRC */
427
428 /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
429 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
430 hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
431
432 #if (USE_SPI_CRC != 0U)
433 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
434 /* Configure : CRC Polynomial */
435 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
436 {
437 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
438 }
439 #endif /* USE_SPI_CRC */
440
441 #if defined(SPI_I2SCFGR_I2SMOD)
442 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
443 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
444 #endif /* SPI_I2SCFGR_I2SMOD */
445
446 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
447 hspi->State = HAL_SPI_STATE_READY;
448
449 return HAL_OK;
450 }
451
452 /**
453 * @brief De-Initialize the SPI peripheral.
454 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
455 * the configuration information for SPI module.
456 * @retval HAL status
457 */
HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)458 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
459 {
460 /* Check the SPI handle allocation */
461 if (hspi == NULL)
462 {
463 return HAL_ERROR;
464 }
465
466 /* Check SPI Instance parameter */
467 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
468
469 hspi->State = HAL_SPI_STATE_BUSY;
470
471 /* Disable the SPI Peripheral Clock */
472 __HAL_SPI_DISABLE(hspi);
473
474 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
475 if (hspi->MspDeInitCallback == NULL)
476 {
477 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
478 }
479
480 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
481 hspi->MspDeInitCallback(hspi);
482 #else
483 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
484 HAL_SPI_MspDeInit(hspi);
485 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
486
487 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
488 hspi->State = HAL_SPI_STATE_RESET;
489
490 /* Release Lock */
491 __HAL_UNLOCK(hspi);
492
493 return HAL_OK;
494 }
495
496 /**
497 * @brief Initialize the SPI MSP.
498 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
499 * the configuration information for SPI module.
500 * @retval None
501 */
HAL_SPI_MspInit(SPI_HandleTypeDef * hspi)502 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
503 {
504 /* Prevent unused argument(s) compilation warning */
505 UNUSED(hspi);
506
507 /* NOTE : This function should not be modified, when the callback is needed,
508 the HAL_SPI_MspInit should be implemented in the user file
509 */
510 }
511
512 /**
513 * @brief De-Initialize the SPI MSP.
514 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
515 * the configuration information for SPI module.
516 * @retval None
517 */
HAL_SPI_MspDeInit(SPI_HandleTypeDef * hspi)518 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
519 {
520 /* Prevent unused argument(s) compilation warning */
521 UNUSED(hspi);
522
523 /* NOTE : This function should not be modified, when the callback is needed,
524 the HAL_SPI_MspDeInit should be implemented in the user file
525 */
526 }
527
528 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
529 /**
530 * @brief Register a User SPI Callback
531 * To be used instead of the weak predefined callback
532 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
533 * the configuration information for the specified SPI.
534 * @param CallbackID ID of the callback to be registered
535 * @param pCallback pointer to the Callback function
536 * @retval HAL status
537 */
HAL_SPI_RegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID,pSPI_CallbackTypeDef pCallback)538 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
539 {
540 HAL_StatusTypeDef status = HAL_OK;
541
542 if (pCallback == NULL)
543 {
544 /* Update the error code */
545 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
546
547 return HAL_ERROR;
548 }
549 /* Process locked */
550 __HAL_LOCK(hspi);
551
552 if (HAL_SPI_STATE_READY == hspi->State)
553 {
554 switch (CallbackID)
555 {
556 case HAL_SPI_TX_COMPLETE_CB_ID :
557 hspi->TxCpltCallback = pCallback;
558 break;
559
560 case HAL_SPI_RX_COMPLETE_CB_ID :
561 hspi->RxCpltCallback = pCallback;
562 break;
563
564 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
565 hspi->TxRxCpltCallback = pCallback;
566 break;
567
568 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
569 hspi->TxHalfCpltCallback = pCallback;
570 break;
571
572 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
573 hspi->RxHalfCpltCallback = pCallback;
574 break;
575
576 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
577 hspi->TxRxHalfCpltCallback = pCallback;
578 break;
579
580 case HAL_SPI_ERROR_CB_ID :
581 hspi->ErrorCallback = pCallback;
582 break;
583
584 case HAL_SPI_ABORT_CB_ID :
585 hspi->AbortCpltCallback = pCallback;
586 break;
587
588 case HAL_SPI_MSPINIT_CB_ID :
589 hspi->MspInitCallback = pCallback;
590 break;
591
592 case HAL_SPI_MSPDEINIT_CB_ID :
593 hspi->MspDeInitCallback = pCallback;
594 break;
595
596 default :
597 /* Update the error code */
598 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
599
600 /* Return error status */
601 status = HAL_ERROR;
602 break;
603 }
604 }
605 else if (HAL_SPI_STATE_RESET == hspi->State)
606 {
607 switch (CallbackID)
608 {
609 case HAL_SPI_MSPINIT_CB_ID :
610 hspi->MspInitCallback = pCallback;
611 break;
612
613 case HAL_SPI_MSPDEINIT_CB_ID :
614 hspi->MspDeInitCallback = pCallback;
615 break;
616
617 default :
618 /* Update the error code */
619 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
620
621 /* Return error status */
622 status = HAL_ERROR;
623 break;
624 }
625 }
626 else
627 {
628 /* Update the error code */
629 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
630
631 /* Return error status */
632 status = HAL_ERROR;
633 }
634
635 /* Release Lock */
636 __HAL_UNLOCK(hspi);
637 return status;
638 }
639
640 /**
641 * @brief Unregister an SPI Callback
642 * SPI callback is redirected to the weak predefined callback
643 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
644 * the configuration information for the specified SPI.
645 * @param CallbackID ID of the callback to be unregistered
646 * @retval HAL status
647 */
HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID)648 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
649 {
650 HAL_StatusTypeDef status = HAL_OK;
651
652 /* Process locked */
653 __HAL_LOCK(hspi);
654
655 if (HAL_SPI_STATE_READY == hspi->State)
656 {
657 switch (CallbackID)
658 {
659 case HAL_SPI_TX_COMPLETE_CB_ID :
660 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
661 break;
662
663 case HAL_SPI_RX_COMPLETE_CB_ID :
664 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
665 break;
666
667 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
668 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
669 break;
670
671 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
672 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
673 break;
674
675 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
676 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
677 break;
678
679 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
680 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
681 break;
682
683 case HAL_SPI_ERROR_CB_ID :
684 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
685 break;
686
687 case HAL_SPI_ABORT_CB_ID :
688 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
689 break;
690
691 case HAL_SPI_MSPINIT_CB_ID :
692 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
693 break;
694
695 case HAL_SPI_MSPDEINIT_CB_ID :
696 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
697 break;
698
699 default :
700 /* Update the error code */
701 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
702
703 /* Return error status */
704 status = HAL_ERROR;
705 break;
706 }
707 }
708 else if (HAL_SPI_STATE_RESET == hspi->State)
709 {
710 switch (CallbackID)
711 {
712 case HAL_SPI_MSPINIT_CB_ID :
713 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
714 break;
715
716 case HAL_SPI_MSPDEINIT_CB_ID :
717 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
718 break;
719
720 default :
721 /* Update the error code */
722 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
723
724 /* Return error status */
725 status = HAL_ERROR;
726 break;
727 }
728 }
729 else
730 {
731 /* Update the error code */
732 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
733
734 /* Return error status */
735 status = HAL_ERROR;
736 }
737
738 /* Release Lock */
739 __HAL_UNLOCK(hspi);
740 return status;
741 }
742 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
743 /**
744 * @}
745 */
746
747 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
748 * @brief Data transfers functions
749 *
750 @verbatim
751 ==============================================================================
752 ##### IO operation functions #####
753 ===============================================================================
754 [..]
755 This subsection provides a set of functions allowing to manage the SPI
756 data transfers.
757
758 [..] The SPI supports master and slave mode :
759
760 (#) There are two modes of transfer:
761 (++) Blocking mode: The communication is performed in polling mode.
762 The HAL status of all data processing is returned by the same function
763 after finishing transfer.
764 (++) No-Blocking mode: The communication is performed using Interrupts
765 or DMA, These APIs return the HAL status.
766 The end of the data processing will be indicated through the
767 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
768 using DMA mode.
769 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
770 will be executed respectively at the end of the transmit or Receive process
771 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
772
773 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
774 exist for 1Line (simplex) and 2Lines (full duplex) modes.
775
776 @endverbatim
777 * @{
778 */
779
780 /**
781 * @brief Transmit an amount of data in blocking mode.
782 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
783 * the configuration information for SPI module.
784 * @param pData pointer to data buffer
785 * @param Size amount of data to be sent
786 * @param Timeout Timeout duration
787 * @retval HAL status
788 */
HAL_SPI_Transmit(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)789 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
790 {
791 uint32_t tickstart;
792 HAL_StatusTypeDef errorcode = HAL_OK;
793 uint16_t initial_TxXferCount;
794
795 /* Check Direction parameter */
796 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
797
798 /* Process Locked */
799 __HAL_LOCK(hspi);
800
801 /* Init tickstart for timeout management*/
802 tickstart = HAL_GetTick();
803 initial_TxXferCount = Size;
804
805 if (hspi->State != HAL_SPI_STATE_READY)
806 {
807 errorcode = HAL_BUSY;
808 goto error;
809 }
810
811 if ((pData == NULL) || (Size == 0U))
812 {
813 errorcode = HAL_ERROR;
814 goto error;
815 }
816
817 /* Set the transaction information */
818 hspi->State = HAL_SPI_STATE_BUSY_TX;
819 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
820 hspi->pTxBuffPtr = (uint8_t *)pData;
821 hspi->TxXferSize = Size;
822 hspi->TxXferCount = Size;
823
824 /*Init field not used in handle to zero */
825 hspi->pRxBuffPtr = (uint8_t *)NULL;
826 hspi->RxXferSize = 0U;
827 hspi->RxXferCount = 0U;
828 hspi->TxISR = NULL;
829 hspi->RxISR = NULL;
830
831 /* Configure communication direction : 1Line */
832 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
833 {
834 SPI_1LINE_TX(hspi);
835 }
836
837 #if (USE_SPI_CRC != 0U)
838 /* Reset CRC Calculation */
839 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
840 {
841 SPI_RESET_CRC(hspi);
842 }
843 #endif /* USE_SPI_CRC */
844
845 /* Check if the SPI is already enabled */
846 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
847 {
848 /* Enable SPI peripheral */
849 __HAL_SPI_ENABLE(hspi);
850 }
851
852 /* Transmit data in 16 Bit mode */
853 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
854 {
855 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
856 {
857 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
858 hspi->pTxBuffPtr += sizeof(uint16_t);
859 hspi->TxXferCount--;
860 }
861 /* Transmit data in 16 Bit mode */
862 while (hspi->TxXferCount > 0U)
863 {
864 /* Wait until TXE flag is set to send data */
865 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
866 {
867 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
868 hspi->pTxBuffPtr += sizeof(uint16_t);
869 hspi->TxXferCount--;
870 }
871 else
872 {
873 /* Timeout management */
874 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
875 {
876 errorcode = HAL_TIMEOUT;
877 goto error;
878 }
879 }
880 }
881 }
882 /* Transmit data in 8 Bit mode */
883 else
884 {
885 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
886 {
887 if (hspi->TxXferCount > 1U)
888 {
889 /* write on the data register in packing mode */
890 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
891 hspi->pTxBuffPtr += sizeof(uint16_t);
892 hspi->TxXferCount -= 2U;
893 }
894 else
895 {
896 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
897 hspi->pTxBuffPtr ++;
898 hspi->TxXferCount--;
899 }
900 }
901 while (hspi->TxXferCount > 0U)
902 {
903 /* Wait until TXE flag is set to send data */
904 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
905 {
906 if (hspi->TxXferCount > 1U)
907 {
908 /* write on the data register in packing mode */
909 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
910 hspi->pTxBuffPtr += sizeof(uint16_t);
911 hspi->TxXferCount -= 2U;
912 }
913 else
914 {
915 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
916 hspi->pTxBuffPtr++;
917 hspi->TxXferCount--;
918 }
919 }
920 else
921 {
922 /* Timeout management */
923 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
924 {
925 errorcode = HAL_TIMEOUT;
926 goto error;
927 }
928 }
929 }
930 }
931 #if (USE_SPI_CRC != 0U)
932 /* Enable CRC Transmission */
933 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
934 {
935 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
936 }
937 #endif /* USE_SPI_CRC */
938
939 /* Check the end of the transaction */
940 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
941 {
942 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
943 }
944
945 /* Clear overrun flag in 2 Lines communication mode because received is not read */
946 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
947 {
948 __HAL_SPI_CLEAR_OVRFLAG(hspi);
949 }
950
951 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
952 {
953 errorcode = HAL_ERROR;
954 }
955
956 error:
957 hspi->State = HAL_SPI_STATE_READY;
958 /* Process Unlocked */
959 __HAL_UNLOCK(hspi);
960 return errorcode;
961 }
962
963 /**
964 * @brief Receive an amount of data in blocking mode.
965 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
966 * the configuration information for SPI module.
967 * @param pData pointer to data buffer
968 * @param Size amount of data to be received
969 * @param Timeout Timeout duration
970 * @retval HAL status
971 */
HAL_SPI_Receive(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)972 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
973 {
974 uint32_t tickstart;
975 HAL_StatusTypeDef errorcode = HAL_OK;
976
977 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
978 {
979 hspi->State = HAL_SPI_STATE_BUSY_RX;
980 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
981 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
982 }
983
984 /* Process Locked */
985 __HAL_LOCK(hspi);
986
987 /* Init tickstart for timeout management*/
988 tickstart = HAL_GetTick();
989
990 if (hspi->State != HAL_SPI_STATE_READY)
991 {
992 errorcode = HAL_BUSY;
993 goto error;
994 }
995
996 if ((pData == NULL) || (Size == 0U))
997 {
998 errorcode = HAL_ERROR;
999 goto error;
1000 }
1001
1002 /* Set the transaction information */
1003 hspi->State = HAL_SPI_STATE_BUSY_RX;
1004 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1005 hspi->pRxBuffPtr = (uint8_t *)pData;
1006 hspi->RxXferSize = Size;
1007 hspi->RxXferCount = Size;
1008
1009 /*Init field not used in handle to zero */
1010 hspi->pTxBuffPtr = (uint8_t *)NULL;
1011 hspi->TxXferSize = 0U;
1012 hspi->TxXferCount = 0U;
1013 hspi->RxISR = NULL;
1014 hspi->TxISR = NULL;
1015
1016 #if (USE_SPI_CRC != 0U)
1017 /* Reset CRC Calculation */
1018 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1019 {
1020 SPI_RESET_CRC(hspi);
1021 /* this is done to handle the CRCNEXT before the latest data */
1022 hspi->RxXferCount--;
1023 }
1024 #endif /* USE_SPI_CRC */
1025
1026 /* Set the Rx Fifo threshold */
1027 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1028 {
1029 /* Set RX Fifo threshold according the reception data length: 16bit */
1030 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1031 }
1032 else
1033 {
1034 /* Set RX Fifo threshold according the reception data length: 8bit */
1035 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1036 }
1037
1038 /* Configure communication direction: 1Line */
1039 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1040 {
1041 SPI_1LINE_RX(hspi);
1042 }
1043
1044 /* Check if the SPI is already enabled */
1045 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1046 {
1047 /* Enable SPI peripheral */
1048 __HAL_SPI_ENABLE(hspi);
1049 }
1050
1051 /* Receive data in 8 Bit mode */
1052 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
1053 {
1054 /* Transfer loop */
1055 while (hspi->RxXferCount > 0U)
1056 {
1057 /* Check the RXNE flag */
1058 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1059 {
1060 /* read the received data */
1061 (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1062 hspi->pRxBuffPtr += sizeof(uint8_t);
1063 hspi->RxXferCount--;
1064 }
1065 else
1066 {
1067 /* Timeout management */
1068 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1069 {
1070 errorcode = HAL_TIMEOUT;
1071 goto error;
1072 }
1073 }
1074 }
1075 }
1076 else
1077 {
1078 /* Transfer loop */
1079 while (hspi->RxXferCount > 0U)
1080 {
1081 /* Check the RXNE flag */
1082 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1083 {
1084 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1085 hspi->pRxBuffPtr += sizeof(uint16_t);
1086 hspi->RxXferCount--;
1087 }
1088 else
1089 {
1090 /* Timeout management */
1091 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1092 {
1093 errorcode = HAL_TIMEOUT;
1094 goto error;
1095 }
1096 }
1097 }
1098 }
1099
1100 #if (USE_SPI_CRC != 0U)
1101 /* Handle the CRC Transmission */
1102 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1103 {
1104 /* freeze the CRC before the latest data */
1105 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1106
1107 /* Read the latest data */
1108 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1109 {
1110 /* the latest data has not been received */
1111 errorcode = HAL_TIMEOUT;
1112 goto error;
1113 }
1114
1115 /* Receive last data in 16 Bit mode */
1116 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1117 {
1118 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1119 }
1120 /* Receive last data in 8 Bit mode */
1121 else
1122 {
1123 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1124 }
1125
1126 /* Wait the CRC data */
1127 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1128 {
1129 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1130 errorcode = HAL_TIMEOUT;
1131 goto error;
1132 }
1133
1134 /* Read CRC to Flush DR and RXNE flag */
1135 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1136 {
1137 /* Read 16bit CRC */
1138 READ_REG(hspi->Instance->DR);
1139 }
1140 else
1141 {
1142 /* Read 8bit CRC */
1143 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1144
1145 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1146 {
1147 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1148 {
1149 /* Error on the CRC reception */
1150 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1151 errorcode = HAL_TIMEOUT;
1152 goto error;
1153 }
1154 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1155 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1156 }
1157 }
1158 }
1159 #endif /* USE_SPI_CRC */
1160
1161 /* Check the end of the transaction */
1162 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1163 {
1164 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1165 }
1166
1167 #if (USE_SPI_CRC != 0U)
1168 /* Check if CRC error occurred */
1169 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1170 {
1171 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1172 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1173 }
1174 #endif /* USE_SPI_CRC */
1175
1176 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1177 {
1178 errorcode = HAL_ERROR;
1179 }
1180
1181 error :
1182 hspi->State = HAL_SPI_STATE_READY;
1183 __HAL_UNLOCK(hspi);
1184 return errorcode;
1185 }
1186
1187 /**
1188 * @brief Transmit and Receive an amount of data in blocking mode.
1189 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1190 * the configuration information for SPI module.
1191 * @param pTxData pointer to transmission data buffer
1192 * @param pRxData pointer to reception data buffer
1193 * @param Size amount of data to be sent and received
1194 * @param Timeout Timeout duration
1195 * @retval HAL status
1196 */
HAL_SPI_TransmitReceive(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size,uint32_t Timeout)1197 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1198 uint32_t Timeout)
1199 {
1200 uint16_t initial_TxXferCount;
1201 uint16_t initial_RxXferCount;
1202 uint32_t tmp_mode;
1203 HAL_SPI_StateTypeDef tmp_state;
1204 uint32_t tickstart;
1205 #if (USE_SPI_CRC != 0U)
1206 uint32_t spi_cr1;
1207 uint32_t spi_cr2;
1208 #endif /* USE_SPI_CRC */
1209
1210 /* Variable used to alternate Rx and Tx during transfer */
1211 uint32_t txallowed = 1U;
1212 HAL_StatusTypeDef errorcode = HAL_OK;
1213
1214 /* Check Direction parameter */
1215 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1216
1217 /* Process Locked */
1218 __HAL_LOCK(hspi);
1219
1220 /* Init tickstart for timeout management*/
1221 tickstart = HAL_GetTick();
1222
1223 /* Init temporary variables */
1224 tmp_state = hspi->State;
1225 tmp_mode = hspi->Init.Mode;
1226 initial_TxXferCount = Size;
1227 initial_RxXferCount = Size;
1228 #if (USE_SPI_CRC != 0U)
1229 spi_cr1 = READ_REG(hspi->Instance->CR1);
1230 spi_cr2 = READ_REG(hspi->Instance->CR2);
1231 #endif /* USE_SPI_CRC */
1232
1233 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1234 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1235 {
1236 errorcode = HAL_BUSY;
1237 goto error;
1238 }
1239
1240 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1241 {
1242 errorcode = HAL_ERROR;
1243 goto error;
1244 }
1245
1246 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1247 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1248 {
1249 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1250 }
1251
1252 /* Set the transaction information */
1253 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1254 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1255 hspi->RxXferCount = Size;
1256 hspi->RxXferSize = Size;
1257 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1258 hspi->TxXferCount = Size;
1259 hspi->TxXferSize = Size;
1260
1261 /*Init field not used in handle to zero */
1262 hspi->RxISR = NULL;
1263 hspi->TxISR = NULL;
1264
1265 #if (USE_SPI_CRC != 0U)
1266 /* Reset CRC Calculation */
1267 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1268 {
1269 SPI_RESET_CRC(hspi);
1270 }
1271 #endif /* USE_SPI_CRC */
1272
1273 /* Set the Rx Fifo threshold */
1274 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
1275 {
1276 /* Set fiforxthreshold according the reception data length: 16bit */
1277 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1278 }
1279 else
1280 {
1281 /* Set fiforxthreshold according the reception data length: 8bit */
1282 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1283 }
1284
1285 /* Check if the SPI is already enabled */
1286 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1287 {
1288 /* Enable SPI peripheral */
1289 __HAL_SPI_ENABLE(hspi);
1290 }
1291
1292 /* Transmit and Receive data in 16 Bit mode */
1293 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1294 {
1295 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1296 {
1297 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1298 hspi->pTxBuffPtr += sizeof(uint16_t);
1299 hspi->TxXferCount--;
1300 }
1301 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1302 {
1303 /* Check TXE flag */
1304 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1305 {
1306 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1307 hspi->pTxBuffPtr += sizeof(uint16_t);
1308 hspi->TxXferCount--;
1309 /* Next Data is a reception (Rx). Tx not allowed */
1310 txallowed = 0U;
1311
1312 #if (USE_SPI_CRC != 0U)
1313 /* Enable CRC Transmission */
1314 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1315 {
1316 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1317 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1318 {
1319 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1320 }
1321 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1322 }
1323 #endif /* USE_SPI_CRC */
1324 }
1325
1326 /* Check RXNE flag */
1327 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1328 {
1329 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1330 hspi->pRxBuffPtr += sizeof(uint16_t);
1331 hspi->RxXferCount--;
1332 /* Next Data is a Transmission (Tx). Tx is allowed */
1333 txallowed = 1U;
1334 }
1335 if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
1336 {
1337 errorcode = HAL_TIMEOUT;
1338 goto error;
1339 }
1340 }
1341 }
1342 /* Transmit and Receive data in 8 Bit mode */
1343 else
1344 {
1345 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1346 {
1347 if (hspi->TxXferCount > 1U)
1348 {
1349 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1350 hspi->pTxBuffPtr += sizeof(uint16_t);
1351 hspi->TxXferCount -= 2U;
1352 }
1353 else
1354 {
1355 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1356 hspi->pTxBuffPtr++;
1357 hspi->TxXferCount--;
1358 }
1359 }
1360 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1361 {
1362 /* Check TXE flag */
1363 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1364 {
1365 if (hspi->TxXferCount > 1U)
1366 {
1367 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1368 hspi->pTxBuffPtr += sizeof(uint16_t);
1369 hspi->TxXferCount -= 2U;
1370 }
1371 else
1372 {
1373 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1374 hspi->pTxBuffPtr++;
1375 hspi->TxXferCount--;
1376 }
1377 /* Next Data is a reception (Rx). Tx not allowed */
1378 txallowed = 0U;
1379
1380 #if (USE_SPI_CRC != 0U)
1381 /* Enable CRC Transmission */
1382 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1383 {
1384 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1385 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1386 {
1387 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1388 }
1389 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1390 }
1391 #endif /* USE_SPI_CRC */
1392 }
1393
1394 /* Wait until RXNE flag is reset */
1395 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1396 {
1397 if (hspi->RxXferCount > 1U)
1398 {
1399 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1400 hspi->pRxBuffPtr += sizeof(uint16_t);
1401 hspi->RxXferCount -= 2U;
1402 if (hspi->RxXferCount <= 1U)
1403 {
1404 /* Set RX Fifo threshold before to switch on 8 bit data size */
1405 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1406 }
1407 }
1408 else
1409 {
1410 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1411 hspi->pRxBuffPtr++;
1412 hspi->RxXferCount--;
1413 }
1414 /* Next Data is a Transmission (Tx). Tx is allowed */
1415 txallowed = 1U;
1416 }
1417 if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1418 {
1419 errorcode = HAL_TIMEOUT;
1420 goto error;
1421 }
1422 }
1423 }
1424
1425 #if (USE_SPI_CRC != 0U)
1426 /* Read CRC from DR to close CRC calculation process */
1427 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1428 {
1429 /* Wait until TXE flag */
1430 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1431 {
1432 /* Error on the CRC reception */
1433 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1434 errorcode = HAL_TIMEOUT;
1435 goto error;
1436 }
1437 /* Read CRC */
1438 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1439 {
1440 /* Read 16bit CRC */
1441 READ_REG(hspi->Instance->DR);
1442 }
1443 else
1444 {
1445 /* Read 8bit CRC */
1446 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1447
1448 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
1449 {
1450 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1451 {
1452 /* Error on the CRC reception */
1453 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1454 errorcode = HAL_TIMEOUT;
1455 goto error;
1456 }
1457 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1458 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1459 }
1460 }
1461 }
1462
1463 /* Check if CRC error occurred */
1464 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1465 {
1466 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1467 /* Clear CRC Flag */
1468 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1469
1470 errorcode = HAL_ERROR;
1471 }
1472 #endif /* USE_SPI_CRC */
1473
1474 /* Check the end of the transaction */
1475 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1476 {
1477 errorcode = HAL_ERROR;
1478 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1479 }
1480
1481 error :
1482 hspi->State = HAL_SPI_STATE_READY;
1483 __HAL_UNLOCK(hspi);
1484 return errorcode;
1485 }
1486
1487 /**
1488 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1489 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1490 * the configuration information for SPI module.
1491 * @param pData pointer to data buffer
1492 * @param Size amount of data to be sent
1493 * @retval HAL status
1494 */
HAL_SPI_Transmit_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1495 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1496 {
1497 HAL_StatusTypeDef errorcode = HAL_OK;
1498
1499 /* Check Direction parameter */
1500 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1501
1502 /* Process Locked */
1503 __HAL_LOCK(hspi);
1504
1505 if ((pData == NULL) || (Size == 0U))
1506 {
1507 errorcode = HAL_ERROR;
1508 goto error;
1509 }
1510
1511 if (hspi->State != HAL_SPI_STATE_READY)
1512 {
1513 errorcode = HAL_BUSY;
1514 goto error;
1515 }
1516
1517 /* Set the transaction information */
1518 hspi->State = HAL_SPI_STATE_BUSY_TX;
1519 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1520 hspi->pTxBuffPtr = (uint8_t *)pData;
1521 hspi->TxXferSize = Size;
1522 hspi->TxXferCount = Size;
1523
1524 /* Init field not used in handle to zero */
1525 hspi->pRxBuffPtr = (uint8_t *)NULL;
1526 hspi->RxXferSize = 0U;
1527 hspi->RxXferCount = 0U;
1528 hspi->RxISR = NULL;
1529
1530 /* Set the function for IT treatment */
1531 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1532 {
1533 hspi->TxISR = SPI_TxISR_16BIT;
1534 }
1535 else
1536 {
1537 hspi->TxISR = SPI_TxISR_8BIT;
1538 }
1539
1540 /* Configure communication direction : 1Line */
1541 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1542 {
1543 SPI_1LINE_TX(hspi);
1544 }
1545
1546 #if (USE_SPI_CRC != 0U)
1547 /* Reset CRC Calculation */
1548 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1549 {
1550 SPI_RESET_CRC(hspi);
1551 }
1552 #endif /* USE_SPI_CRC */
1553
1554 /* Enable TXE and ERR interrupt */
1555 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1556
1557
1558 /* Check if the SPI is already enabled */
1559 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1560 {
1561 /* Enable SPI peripheral */
1562 __HAL_SPI_ENABLE(hspi);
1563 }
1564
1565 error :
1566 __HAL_UNLOCK(hspi);
1567 return errorcode;
1568 }
1569
1570 /**
1571 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1572 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1573 * the configuration information for SPI module.
1574 * @param pData pointer to data buffer
1575 * @param Size amount of data to be sent
1576 * @retval HAL status
1577 */
HAL_SPI_Receive_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1578 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1579 {
1580 HAL_StatusTypeDef errorcode = HAL_OK;
1581
1582 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1583 {
1584 hspi->State = HAL_SPI_STATE_BUSY_RX;
1585 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1586 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1587 }
1588
1589 /* Process Locked */
1590 __HAL_LOCK(hspi);
1591
1592 if (hspi->State != HAL_SPI_STATE_READY)
1593 {
1594 errorcode = HAL_BUSY;
1595 goto error;
1596 }
1597
1598 if ((pData == NULL) || (Size == 0U))
1599 {
1600 errorcode = HAL_ERROR;
1601 goto error;
1602 }
1603
1604 /* Set the transaction information */
1605 hspi->State = HAL_SPI_STATE_BUSY_RX;
1606 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1607 hspi->pRxBuffPtr = (uint8_t *)pData;
1608 hspi->RxXferSize = Size;
1609 hspi->RxXferCount = Size;
1610
1611 /* Init field not used in handle to zero */
1612 hspi->pTxBuffPtr = (uint8_t *)NULL;
1613 hspi->TxXferSize = 0U;
1614 hspi->TxXferCount = 0U;
1615 hspi->TxISR = NULL;
1616
1617 /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
1618 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1619 {
1620 /* Set RX Fifo threshold according the reception data length: 16 bit */
1621 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1622 hspi->RxISR = SPI_RxISR_16BIT;
1623 }
1624 else
1625 {
1626 /* Set RX Fifo threshold according the reception data length: 8 bit */
1627 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1628 hspi->RxISR = SPI_RxISR_8BIT;
1629 }
1630
1631 /* Configure communication direction : 1Line */
1632 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1633 {
1634 SPI_1LINE_RX(hspi);
1635 }
1636
1637 #if (USE_SPI_CRC != 0U)
1638 /* Reset CRC Calculation */
1639 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1640 {
1641 hspi->CRCSize = 1U;
1642 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1643 {
1644 hspi->CRCSize = 2U;
1645 }
1646 SPI_RESET_CRC(hspi);
1647 }
1648 else
1649 {
1650 hspi->CRCSize = 0U;
1651 }
1652 #endif /* USE_SPI_CRC */
1653
1654 /* Enable TXE and ERR interrupt */
1655 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1656
1657 /* Note : The SPI must be enabled after unlocking current process
1658 to avoid the risk of SPI interrupt handle execution before current
1659 process unlock */
1660
1661 /* Check if the SPI is already enabled */
1662 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1663 {
1664 /* Enable SPI peripheral */
1665 __HAL_SPI_ENABLE(hspi);
1666 }
1667
1668 error :
1669 /* Process Unlocked */
1670 __HAL_UNLOCK(hspi);
1671 return errorcode;
1672 }
1673
1674 /**
1675 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1676 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1677 * the configuration information for SPI module.
1678 * @param pTxData pointer to transmission data buffer
1679 * @param pRxData pointer to reception data buffer
1680 * @param Size amount of data to be sent and received
1681 * @retval HAL status
1682 */
HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1683 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1684 {
1685 uint32_t tmp_mode;
1686 HAL_SPI_StateTypeDef tmp_state;
1687 HAL_StatusTypeDef errorcode = HAL_OK;
1688
1689 /* Check Direction parameter */
1690 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1691
1692 /* Process locked */
1693 __HAL_LOCK(hspi);
1694
1695 /* Init temporary variables */
1696 tmp_state = hspi->State;
1697 tmp_mode = hspi->Init.Mode;
1698
1699 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1700 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1701 {
1702 errorcode = HAL_BUSY;
1703 goto error;
1704 }
1705
1706 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1707 {
1708 errorcode = HAL_ERROR;
1709 goto error;
1710 }
1711
1712 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1713 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1714 {
1715 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1716 }
1717
1718 /* Set the transaction information */
1719 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1720 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1721 hspi->TxXferSize = Size;
1722 hspi->TxXferCount = Size;
1723 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1724 hspi->RxXferSize = Size;
1725 hspi->RxXferCount = Size;
1726
1727 /* Set the function for IT treatment */
1728 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1729 {
1730 hspi->RxISR = SPI_2linesRxISR_16BIT;
1731 hspi->TxISR = SPI_2linesTxISR_16BIT;
1732 }
1733 else
1734 {
1735 hspi->RxISR = SPI_2linesRxISR_8BIT;
1736 hspi->TxISR = SPI_2linesTxISR_8BIT;
1737 }
1738
1739 #if (USE_SPI_CRC != 0U)
1740 /* Reset CRC Calculation */
1741 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1742 {
1743 hspi->CRCSize = 1U;
1744 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1745 {
1746 hspi->CRCSize = 2U;
1747 }
1748 SPI_RESET_CRC(hspi);
1749 }
1750 else
1751 {
1752 hspi->CRCSize = 0U;
1753 }
1754 #endif /* USE_SPI_CRC */
1755
1756 /* Check if packing mode is enabled and if there is more than 2 data to receive */
1757 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
1758 {
1759 /* Set RX Fifo threshold according the reception data length: 16 bit */
1760 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1761 }
1762 else
1763 {
1764 /* Set RX Fifo threshold according the reception data length: 8 bit */
1765 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1766 }
1767
1768 /* Enable TXE, RXNE and ERR interrupt */
1769 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1770
1771 /* Check if the SPI is already enabled */
1772 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1773 {
1774 /* Enable SPI peripheral */
1775 __HAL_SPI_ENABLE(hspi);
1776 }
1777
1778 error :
1779 /* Process Unlocked */
1780 __HAL_UNLOCK(hspi);
1781 return errorcode;
1782 }
1783
1784 /**
1785 * @brief Transmit an amount of data in non-blocking mode with DMA.
1786 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1787 * the configuration information for SPI module.
1788 * @param pData pointer to data buffer
1789 * @param Size amount of data to be sent
1790 * @retval HAL status
1791 */
HAL_SPI_Transmit_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1792 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1793 {
1794 HAL_StatusTypeDef errorcode = HAL_OK;
1795
1796 /* Check tx dma handle */
1797 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1798
1799 /* Check Direction parameter */
1800 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1801
1802 /* Process Locked */
1803 __HAL_LOCK(hspi);
1804
1805 if (hspi->State != HAL_SPI_STATE_READY)
1806 {
1807 errorcode = HAL_BUSY;
1808 goto error;
1809 }
1810
1811 if ((pData == NULL) || (Size == 0U))
1812 {
1813 errorcode = HAL_ERROR;
1814 goto error;
1815 }
1816
1817 /* Set the transaction information */
1818 hspi->State = HAL_SPI_STATE_BUSY_TX;
1819 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1820 hspi->pTxBuffPtr = (uint8_t *)pData;
1821 hspi->TxXferSize = Size;
1822 hspi->TxXferCount = Size;
1823
1824 /* Init field not used in handle to zero */
1825 hspi->pRxBuffPtr = (uint8_t *)NULL;
1826 hspi->TxISR = NULL;
1827 hspi->RxISR = NULL;
1828 hspi->RxXferSize = 0U;
1829 hspi->RxXferCount = 0U;
1830
1831 /* Configure communication direction : 1Line */
1832 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1833 {
1834 SPI_1LINE_TX(hspi);
1835 }
1836
1837 #if (USE_SPI_CRC != 0U)
1838 /* Reset CRC Calculation */
1839 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1840 {
1841 SPI_RESET_CRC(hspi);
1842 }
1843 #endif /* USE_SPI_CRC */
1844
1845 /* Set the SPI TxDMA Half transfer complete callback */
1846 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1847
1848 /* Set the SPI TxDMA transfer complete callback */
1849 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1850
1851 /* Set the DMA error callback */
1852 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1853
1854 /* Set the DMA AbortCpltCallback */
1855 hspi->hdmatx->XferAbortCallback = NULL;
1856
1857 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1858 /* Packing mode is enabled only if the DMA setting is HALWORD */
1859 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1860 {
1861 /* Check the even/odd of the data size + crc if enabled */
1862 if ((hspi->TxXferCount & 0x1U) == 0U)
1863 {
1864 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1865 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
1866 }
1867 else
1868 {
1869 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1870 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
1871 }
1872 }
1873
1874 /* Enable the Tx DMA Stream/Channel */
1875 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))
1876 {
1877 /* Update SPI error code */
1878 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1879 errorcode = HAL_ERROR;
1880
1881 hspi->State = HAL_SPI_STATE_READY;
1882 goto error;
1883 }
1884
1885 /* Check if the SPI is already enabled */
1886 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1887 {
1888 /* Enable SPI peripheral */
1889 __HAL_SPI_ENABLE(hspi);
1890 }
1891
1892 /* Enable the SPI Error Interrupt Bit */
1893 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1894
1895 /* Enable Tx DMA Request */
1896 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1897
1898 error :
1899 /* Process Unlocked */
1900 __HAL_UNLOCK(hspi);
1901 return errorcode;
1902 }
1903
1904 /**
1905 * @brief Receive an amount of data in non-blocking mode with DMA.
1906 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
1907 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1908 * the configuration information for SPI module.
1909 * @param pData pointer to data buffer
1910 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1911 * @param Size amount of data to be sent
1912 * @retval HAL status
1913 */
HAL_SPI_Receive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1914 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1915 {
1916 HAL_StatusTypeDef errorcode = HAL_OK;
1917
1918 /* Check rx dma handle */
1919 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1920
1921 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1922 {
1923 hspi->State = HAL_SPI_STATE_BUSY_RX;
1924
1925 /* Check tx dma handle */
1926 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1927
1928 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1929 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1930 }
1931
1932 /* Process Locked */
1933 __HAL_LOCK(hspi);
1934
1935 if (hspi->State != HAL_SPI_STATE_READY)
1936 {
1937 errorcode = HAL_BUSY;
1938 goto error;
1939 }
1940
1941 if ((pData == NULL) || (Size == 0U))
1942 {
1943 errorcode = HAL_ERROR;
1944 goto error;
1945 }
1946
1947 /* Set the transaction information */
1948 hspi->State = HAL_SPI_STATE_BUSY_RX;
1949 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1950 hspi->pRxBuffPtr = (uint8_t *)pData;
1951 hspi->RxXferSize = Size;
1952 hspi->RxXferCount = Size;
1953
1954 /*Init field not used in handle to zero */
1955 hspi->RxISR = NULL;
1956 hspi->TxISR = NULL;
1957 hspi->TxXferSize = 0U;
1958 hspi->TxXferCount = 0U;
1959
1960 /* Configure communication direction : 1Line */
1961 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1962 {
1963 SPI_1LINE_RX(hspi);
1964 }
1965
1966 #if (USE_SPI_CRC != 0U)
1967 /* Reset CRC Calculation */
1968 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1969 {
1970 SPI_RESET_CRC(hspi);
1971 }
1972 #endif /* USE_SPI_CRC */
1973
1974
1975 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
1976 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1977 {
1978 /* Set RX Fifo threshold according the reception data length: 16bit */
1979 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1980 }
1981 else
1982 {
1983 /* Set RX Fifo threshold according the reception data length: 8bit */
1984 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1985
1986 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
1987 {
1988 /* Set RX Fifo threshold according the reception data length: 16bit */
1989 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1990
1991 if ((hspi->RxXferCount & 0x1U) == 0x0U)
1992 {
1993 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
1994 hspi->RxXferCount = hspi->RxXferCount >> 1U;
1995 }
1996 else
1997 {
1998 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
1999 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2000 }
2001 }
2002 }
2003
2004 /* Set the SPI RxDMA Half transfer complete callback */
2005 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2006
2007 /* Set the SPI Rx DMA transfer complete callback */
2008 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2009
2010 /* Set the DMA error callback */
2011 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2012
2013 /* Set the DMA AbortCpltCallback */
2014 hspi->hdmarx->XferAbortCallback = NULL;
2015
2016 /* Enable the Rx DMA Stream/Channel */
2017 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
2018 {
2019 /* Update SPI error code */
2020 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2021 errorcode = HAL_ERROR;
2022
2023 hspi->State = HAL_SPI_STATE_READY;
2024 goto error;
2025 }
2026
2027 /* Check if the SPI is already enabled */
2028 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2029 {
2030 /* Enable SPI peripheral */
2031 __HAL_SPI_ENABLE(hspi);
2032 }
2033
2034 /* Enable the SPI Error Interrupt Bit */
2035 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2036
2037 /* Enable Rx DMA Request */
2038 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2039
2040 error:
2041 /* Process Unlocked */
2042 __HAL_UNLOCK(hspi);
2043 return errorcode;
2044 }
2045
2046 /**
2047 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
2048 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2049 * the configuration information for SPI module.
2050 * @param pTxData pointer to transmission data buffer
2051 * @param pRxData pointer to reception data buffer
2052 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
2053 * @param Size amount of data to be sent
2054 * @retval HAL status
2055 */
HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)2056 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
2057 uint16_t Size)
2058 {
2059 uint32_t tmp_mode;
2060 HAL_SPI_StateTypeDef tmp_state;
2061 HAL_StatusTypeDef errorcode = HAL_OK;
2062
2063 /* Check rx & tx dma handles */
2064 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
2065 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
2066
2067 /* Check Direction parameter */
2068 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
2069
2070 /* Process locked */
2071 __HAL_LOCK(hspi);
2072
2073 /* Init temporary variables */
2074 tmp_state = hspi->State;
2075 tmp_mode = hspi->Init.Mode;
2076
2077 if (!((tmp_state == HAL_SPI_STATE_READY) ||
2078 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
2079 {
2080 errorcode = HAL_BUSY;
2081 goto error;
2082 }
2083
2084 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
2085 {
2086 errorcode = HAL_ERROR;
2087 goto error;
2088 }
2089
2090 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
2091 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
2092 {
2093 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
2094 }
2095
2096 /* Set the transaction information */
2097 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2098 hspi->pTxBuffPtr = (uint8_t *)pTxData;
2099 hspi->TxXferSize = Size;
2100 hspi->TxXferCount = Size;
2101 hspi->pRxBuffPtr = (uint8_t *)pRxData;
2102 hspi->RxXferSize = Size;
2103 hspi->RxXferCount = Size;
2104
2105 /* Init field not used in handle to zero */
2106 hspi->RxISR = NULL;
2107 hspi->TxISR = NULL;
2108
2109 #if (USE_SPI_CRC != 0U)
2110 /* Reset CRC Calculation */
2111 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2112 {
2113 SPI_RESET_CRC(hspi);
2114 }
2115 #endif /* USE_SPI_CRC */
2116
2117 /* Reset the threshold bit */
2118 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
2119
2120 /* The packing mode management is enabled by the DMA settings according the spi data size */
2121 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2122 {
2123 /* Set fiforxthreshold according the reception data length: 16bit */
2124 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2125 }
2126 else
2127 {
2128 /* Set RX Fifo threshold according the reception data length: 8bit */
2129 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2130
2131 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2132 {
2133 if ((hspi->TxXferSize & 0x1U) == 0x0U)
2134 {
2135 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2136 hspi->TxXferCount = hspi->TxXferCount >> 1U;
2137 }
2138 else
2139 {
2140 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2141 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
2142 }
2143 }
2144
2145 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2146 {
2147 /* Set RX Fifo threshold according the reception data length: 16bit */
2148 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2149
2150 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2151 {
2152 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2153 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2154 }
2155 else
2156 {
2157 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2158 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2159 }
2160 }
2161 }
2162
2163 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
2164 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
2165 {
2166 /* Set the SPI Rx DMA Half transfer complete callback */
2167 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2168 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2169 }
2170 else
2171 {
2172 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
2173 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
2174 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
2175 }
2176
2177 /* Set the DMA error callback */
2178 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2179
2180 /* Set the DMA AbortCpltCallback */
2181 hspi->hdmarx->XferAbortCallback = NULL;
2182
2183 /* Enable the Rx DMA Stream/Channel */
2184 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
2185 {
2186 /* Update SPI error code */
2187 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2188 errorcode = HAL_ERROR;
2189
2190 hspi->State = HAL_SPI_STATE_READY;
2191 goto error;
2192 }
2193
2194 /* Enable Rx DMA Request */
2195 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2196
2197 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
2198 is performed in DMA reception complete callback */
2199 hspi->hdmatx->XferHalfCpltCallback = NULL;
2200 hspi->hdmatx->XferCpltCallback = NULL;
2201 hspi->hdmatx->XferErrorCallback = NULL;
2202 hspi->hdmatx->XferAbortCallback = NULL;
2203
2204 /* Enable the Tx DMA Stream/Channel */
2205 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))
2206 {
2207 /* Update SPI error code */
2208 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2209 errorcode = HAL_ERROR;
2210
2211 hspi->State = HAL_SPI_STATE_READY;
2212 goto error;
2213 }
2214
2215 /* Check if the SPI is already enabled */
2216 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2217 {
2218 /* Enable SPI peripheral */
2219 __HAL_SPI_ENABLE(hspi);
2220 }
2221 /* Enable the SPI Error Interrupt Bit */
2222 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2223
2224 /* Enable Tx DMA Request */
2225 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2226
2227 error :
2228 /* Process Unlocked */
2229 __HAL_UNLOCK(hspi);
2230 return errorcode;
2231 }
2232
2233 /**
2234 * @brief Abort ongoing transfer (blocking mode).
2235 * @param hspi SPI handle.
2236 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2237 * started in Interrupt or DMA mode.
2238 * This procedure performs following operations :
2239 * - Disable SPI Interrupts (depending of transfer direction)
2240 * - Disable the DMA transfer in the peripheral register (if enabled)
2241 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2242 * - Set handle State to READY
2243 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2244 * @retval HAL status
2245 */
HAL_SPI_Abort(SPI_HandleTypeDef * hspi)2246 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2247 {
2248 HAL_StatusTypeDef errorcode;
2249 __IO uint32_t count, resetcount;
2250
2251 /* Initialized local variable */
2252 errorcode = HAL_OK;
2253 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2254 count = resetcount;
2255
2256 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2257 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2258
2259 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
2260 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2261 {
2262 hspi->TxISR = SPI_AbortTx_ISR;
2263 /* Wait HAL_SPI_STATE_ABORT state */
2264 do
2265 {
2266 if (count == 0U)
2267 {
2268 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2269 break;
2270 }
2271 count--;
2272 }
2273 while (hspi->State != HAL_SPI_STATE_ABORT);
2274 /* Reset Timeout Counter */
2275 count = resetcount;
2276 }
2277
2278 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2279 {
2280 hspi->RxISR = SPI_AbortRx_ISR;
2281 /* Wait HAL_SPI_STATE_ABORT state */
2282 do
2283 {
2284 if (count == 0U)
2285 {
2286 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2287 break;
2288 }
2289 count--;
2290 }
2291 while (hspi->State != HAL_SPI_STATE_ABORT);
2292 /* Reset Timeout Counter */
2293 count = resetcount;
2294 }
2295
2296 /* Disable the SPI DMA Tx request if enabled */
2297 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2298 {
2299 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2300 if (hspi->hdmatx != NULL)
2301 {
2302 /* Set the SPI DMA Abort callback :
2303 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2304 hspi->hdmatx->XferAbortCallback = NULL;
2305
2306 /* Abort DMA Tx Handle linked to SPI Peripheral */
2307 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2308 {
2309 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2310 }
2311
2312 /* Disable Tx DMA Request */
2313 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2314
2315 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2316 {
2317 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2318 }
2319
2320 /* Disable SPI Peripheral */
2321 __HAL_SPI_DISABLE(hspi);
2322
2323 /* Empty the FRLVL fifo */
2324 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2325 {
2326 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2327 }
2328 }
2329 }
2330
2331 /* Disable the SPI DMA Rx request if enabled */
2332 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2333 {
2334 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2335 if (hspi->hdmarx != NULL)
2336 {
2337 /* Set the SPI DMA Abort callback :
2338 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2339 hspi->hdmarx->XferAbortCallback = NULL;
2340
2341 /* Abort DMA Rx Handle linked to SPI Peripheral */
2342 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2343 {
2344 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2345 }
2346
2347 /* Disable peripheral */
2348 __HAL_SPI_DISABLE(hspi);
2349
2350 /* Control the BSY flag */
2351 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2352 {
2353 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2354 }
2355
2356 /* Empty the FRLVL fifo */
2357 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2358 {
2359 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2360 }
2361
2362 /* Disable Rx DMA Request */
2363 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2364 }
2365 }
2366 /* Reset Tx and Rx transfer counters */
2367 hspi->RxXferCount = 0U;
2368 hspi->TxXferCount = 0U;
2369
2370 /* Check error during Abort procedure */
2371 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2372 {
2373 /* return HAL_Error in case of error during Abort procedure */
2374 errorcode = HAL_ERROR;
2375 }
2376 else
2377 {
2378 /* Reset errorCode */
2379 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2380 }
2381
2382 /* Clear the Error flags in the SR register */
2383 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2384 __HAL_SPI_CLEAR_FREFLAG(hspi);
2385
2386 /* Restore hspi->state to ready */
2387 hspi->State = HAL_SPI_STATE_READY;
2388
2389 return errorcode;
2390 }
2391
2392 /**
2393 * @brief Abort ongoing transfer (Interrupt mode).
2394 * @param hspi SPI handle.
2395 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2396 * started in Interrupt or DMA mode.
2397 * This procedure performs following operations :
2398 * - Disable SPI Interrupts (depending of transfer direction)
2399 * - Disable the DMA transfer in the peripheral register (if enabled)
2400 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2401 * - Set handle State to READY
2402 * - At abort completion, call user abort complete callback
2403 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2404 * considered as completed only when user abort complete callback is executed (not when exiting function).
2405 * @retval HAL status
2406 */
HAL_SPI_Abort_IT(SPI_HandleTypeDef * hspi)2407 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2408 {
2409 HAL_StatusTypeDef errorcode;
2410 uint32_t abortcplt ;
2411 __IO uint32_t count, resetcount;
2412
2413 /* Initialized local variable */
2414 errorcode = HAL_OK;
2415 abortcplt = 1U;
2416 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2417 count = resetcount;
2418
2419 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2420 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2421
2422 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2423 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2424 {
2425 hspi->TxISR = SPI_AbortTx_ISR;
2426 /* Wait HAL_SPI_STATE_ABORT state */
2427 do
2428 {
2429 if (count == 0U)
2430 {
2431 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2432 break;
2433 }
2434 count--;
2435 }
2436 while (hspi->State != HAL_SPI_STATE_ABORT);
2437 /* Reset Timeout Counter */
2438 count = resetcount;
2439 }
2440
2441 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2442 {
2443 hspi->RxISR = SPI_AbortRx_ISR;
2444 /* Wait HAL_SPI_STATE_ABORT state */
2445 do
2446 {
2447 if (count == 0U)
2448 {
2449 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2450 break;
2451 }
2452 count--;
2453 }
2454 while (hspi->State != HAL_SPI_STATE_ABORT);
2455 /* Reset Timeout Counter */
2456 count = resetcount;
2457 }
2458
2459 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2460 before any call to DMA Abort functions */
2461 /* DMA Tx Handle is valid */
2462 if (hspi->hdmatx != NULL)
2463 {
2464 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2465 Otherwise, set it to NULL */
2466 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2467 {
2468 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2469 }
2470 else
2471 {
2472 hspi->hdmatx->XferAbortCallback = NULL;
2473 }
2474 }
2475 /* DMA Rx Handle is valid */
2476 if (hspi->hdmarx != NULL)
2477 {
2478 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2479 Otherwise, set it to NULL */
2480 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2481 {
2482 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2483 }
2484 else
2485 {
2486 hspi->hdmarx->XferAbortCallback = NULL;
2487 }
2488 }
2489
2490 /* Disable the SPI DMA Tx request if enabled */
2491 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2492 {
2493 /* Abort the SPI DMA Tx Stream/Channel */
2494 if (hspi->hdmatx != NULL)
2495 {
2496 /* Abort DMA Tx Handle linked to SPI Peripheral */
2497 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2498 {
2499 hspi->hdmatx->XferAbortCallback = NULL;
2500 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2501 }
2502 else
2503 {
2504 abortcplt = 0U;
2505 }
2506 }
2507 }
2508 /* Disable the SPI DMA Rx request if enabled */
2509 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2510 {
2511 /* Abort the SPI DMA Rx Stream/Channel */
2512 if (hspi->hdmarx != NULL)
2513 {
2514 /* Abort DMA Rx Handle linked to SPI Peripheral */
2515 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2516 {
2517 hspi->hdmarx->XferAbortCallback = NULL;
2518 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2519 }
2520 else
2521 {
2522 abortcplt = 0U;
2523 }
2524 }
2525 }
2526
2527 if (abortcplt == 1U)
2528 {
2529 /* Reset Tx and Rx transfer counters */
2530 hspi->RxXferCount = 0U;
2531 hspi->TxXferCount = 0U;
2532
2533 /* Check error during Abort procedure */
2534 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2535 {
2536 /* return HAL_Error in case of error during Abort procedure */
2537 errorcode = HAL_ERROR;
2538 }
2539 else
2540 {
2541 /* Reset errorCode */
2542 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2543 }
2544
2545 /* Clear the Error flags in the SR register */
2546 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2547 __HAL_SPI_CLEAR_FREFLAG(hspi);
2548
2549 /* Restore hspi->State to Ready */
2550 hspi->State = HAL_SPI_STATE_READY;
2551
2552 /* As no DMA to be aborted, call directly user Abort complete callback */
2553 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2554 hspi->AbortCpltCallback(hspi);
2555 #else
2556 HAL_SPI_AbortCpltCallback(hspi);
2557 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2558 }
2559
2560 return errorcode;
2561 }
2562
2563 /**
2564 * @brief Pause the DMA Transfer.
2565 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2566 * the configuration information for the specified SPI module.
2567 * @retval HAL status
2568 */
HAL_SPI_DMAPause(SPI_HandleTypeDef * hspi)2569 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2570 {
2571 /* Process Locked */
2572 __HAL_LOCK(hspi);
2573
2574 /* Disable the SPI DMA Tx & Rx requests */
2575 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2576
2577 /* Process Unlocked */
2578 __HAL_UNLOCK(hspi);
2579
2580 return HAL_OK;
2581 }
2582
2583 /**
2584 * @brief Resume the DMA Transfer.
2585 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2586 * the configuration information for the specified SPI module.
2587 * @retval HAL status
2588 */
HAL_SPI_DMAResume(SPI_HandleTypeDef * hspi)2589 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2590 {
2591 /* Process Locked */
2592 __HAL_LOCK(hspi);
2593
2594 /* Enable the SPI DMA Tx & Rx requests */
2595 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2596
2597 /* Process Unlocked */
2598 __HAL_UNLOCK(hspi);
2599
2600 return HAL_OK;
2601 }
2602
2603 /**
2604 * @brief Stop the DMA Transfer.
2605 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2606 * the configuration information for the specified SPI module.
2607 * @retval HAL status
2608 */
HAL_SPI_DMAStop(SPI_HandleTypeDef * hspi)2609 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2610 {
2611 HAL_StatusTypeDef errorcode = HAL_OK;
2612 /* The Lock is not implemented on this API to allow the user application
2613 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2614 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2615 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2616 */
2617
2618 /* Abort the SPI DMA tx Stream/Channel */
2619 if (hspi->hdmatx != NULL)
2620 {
2621 if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2622 {
2623 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2624 errorcode = HAL_ERROR;
2625 }
2626 }
2627 /* Abort the SPI DMA rx Stream/Channel */
2628 if (hspi->hdmarx != NULL)
2629 {
2630 if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2631 {
2632 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2633 errorcode = HAL_ERROR;
2634 }
2635 }
2636
2637 /* Disable the SPI DMA Tx & Rx requests */
2638 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2639 hspi->State = HAL_SPI_STATE_READY;
2640 return errorcode;
2641 }
2642
2643 /**
2644 * @brief Handle SPI interrupt request.
2645 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2646 * the configuration information for the specified SPI module.
2647 * @retval None
2648 */
HAL_SPI_IRQHandler(SPI_HandleTypeDef * hspi)2649 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2650 {
2651 uint32_t itsource = hspi->Instance->CR2;
2652 uint32_t itflag = hspi->Instance->SR;
2653
2654 /* SPI in mode Receiver ----------------------------------------------------*/
2655 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2656 (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2657 {
2658 hspi->RxISR(hspi);
2659 return;
2660 }
2661
2662 /* SPI in mode Transmitter -------------------------------------------------*/
2663 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2664 {
2665 hspi->TxISR(hspi);
2666 return;
2667 }
2668
2669 /* SPI in Error Treatment --------------------------------------------------*/
2670 if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2671 {
2672 /* SPI Overrun error interrupt occurred ----------------------------------*/
2673 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2674 {
2675 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2676 {
2677 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2678 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2679 }
2680 else
2681 {
2682 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2683 return;
2684 }
2685 }
2686
2687 /* SPI Mode Fault error interrupt occurred -------------------------------*/
2688 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2689 {
2690 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2691 __HAL_SPI_CLEAR_MODFFLAG(hspi);
2692 }
2693
2694 /* SPI Frame error interrupt occurred ------------------------------------*/
2695 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
2696 {
2697 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2698 __HAL_SPI_CLEAR_FREFLAG(hspi);
2699 }
2700
2701 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2702 {
2703 /* Disable all interrupts */
2704 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2705
2706 hspi->State = HAL_SPI_STATE_READY;
2707 /* Disable the SPI DMA requests if enabled */
2708 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2709 {
2710 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2711
2712 /* Abort the SPI DMA Rx channel */
2713 if (hspi->hdmarx != NULL)
2714 {
2715 /* Set the SPI DMA Abort callback :
2716 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2717 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2718 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2719 {
2720 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2721 }
2722 }
2723 /* Abort the SPI DMA Tx channel */
2724 if (hspi->hdmatx != NULL)
2725 {
2726 /* Set the SPI DMA Abort callback :
2727 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2728 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2729 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2730 {
2731 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2732 }
2733 }
2734 }
2735 else
2736 {
2737 /* Call user error callback */
2738 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2739 hspi->ErrorCallback(hspi);
2740 #else
2741 HAL_SPI_ErrorCallback(hspi);
2742 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2743 }
2744 }
2745 return;
2746 }
2747 }
2748
2749 /**
2750 * @brief Tx Transfer completed callback.
2751 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2752 * the configuration information for SPI module.
2753 * @retval None
2754 */
HAL_SPI_TxCpltCallback(SPI_HandleTypeDef * hspi)2755 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2756 {
2757 /* Prevent unused argument(s) compilation warning */
2758 UNUSED(hspi);
2759
2760 /* NOTE : This function should not be modified, when the callback is needed,
2761 the HAL_SPI_TxCpltCallback should be implemented in the user file
2762 */
2763 }
2764
2765 /**
2766 * @brief Rx Transfer completed callback.
2767 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2768 * the configuration information for SPI module.
2769 * @retval None
2770 */
HAL_SPI_RxCpltCallback(SPI_HandleTypeDef * hspi)2771 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2772 {
2773 /* Prevent unused argument(s) compilation warning */
2774 UNUSED(hspi);
2775
2776 /* NOTE : This function should not be modified, when the callback is needed,
2777 the HAL_SPI_RxCpltCallback should be implemented in the user file
2778 */
2779 }
2780
2781 /**
2782 * @brief Tx and Rx Transfer completed callback.
2783 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2784 * the configuration information for SPI module.
2785 * @retval None
2786 */
HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef * hspi)2787 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2788 {
2789 /* Prevent unused argument(s) compilation warning */
2790 UNUSED(hspi);
2791
2792 /* NOTE : This function should not be modified, when the callback is needed,
2793 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2794 */
2795 }
2796
2797 /**
2798 * @brief Tx Half Transfer completed callback.
2799 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2800 * the configuration information for SPI module.
2801 * @retval None
2802 */
HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef * hspi)2803 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2804 {
2805 /* Prevent unused argument(s) compilation warning */
2806 UNUSED(hspi);
2807
2808 /* NOTE : This function should not be modified, when the callback is needed,
2809 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2810 */
2811 }
2812
2813 /**
2814 * @brief Rx Half Transfer completed callback.
2815 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2816 * the configuration information for SPI module.
2817 * @retval None
2818 */
HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef * hspi)2819 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2820 {
2821 /* Prevent unused argument(s) compilation warning */
2822 UNUSED(hspi);
2823
2824 /* NOTE : This function should not be modified, when the callback is needed,
2825 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2826 */
2827 }
2828
2829 /**
2830 * @brief Tx and Rx Half Transfer callback.
2831 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2832 * the configuration information for SPI module.
2833 * @retval None
2834 */
HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef * hspi)2835 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2836 {
2837 /* Prevent unused argument(s) compilation warning */
2838 UNUSED(hspi);
2839
2840 /* NOTE : This function should not be modified, when the callback is needed,
2841 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2842 */
2843 }
2844
2845 /**
2846 * @brief SPI error callback.
2847 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2848 * the configuration information for SPI module.
2849 * @retval None
2850 */
HAL_SPI_ErrorCallback(SPI_HandleTypeDef * hspi)2851 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2852 {
2853 /* Prevent unused argument(s) compilation warning */
2854 UNUSED(hspi);
2855
2856 /* NOTE : This function should not be modified, when the callback is needed,
2857 the HAL_SPI_ErrorCallback should be implemented in the user file
2858 */
2859 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2860 and user can use HAL_SPI_GetError() API to check the latest error occurred
2861 */
2862 }
2863
2864 /**
2865 * @brief SPI Abort Complete callback.
2866 * @param hspi SPI handle.
2867 * @retval None
2868 */
HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef * hspi)2869 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2870 {
2871 /* Prevent unused argument(s) compilation warning */
2872 UNUSED(hspi);
2873
2874 /* NOTE : This function should not be modified, when the callback is needed,
2875 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2876 */
2877 }
2878
2879 /**
2880 * @}
2881 */
2882
2883 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2884 * @brief SPI control functions
2885 *
2886 @verbatim
2887 ===============================================================================
2888 ##### Peripheral State and Errors functions #####
2889 ===============================================================================
2890 [..]
2891 This subsection provides a set of functions allowing to control the SPI.
2892 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
2893 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
2894 @endverbatim
2895 * @{
2896 */
2897
2898 /**
2899 * @brief Return the SPI handle state.
2900 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2901 * the configuration information for SPI module.
2902 * @retval SPI state
2903 */
HAL_SPI_GetState(SPI_HandleTypeDef * hspi)2904 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2905 {
2906 /* Return SPI handle state */
2907 return hspi->State;
2908 }
2909
2910 /**
2911 * @brief Return the SPI error code.
2912 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2913 * the configuration information for SPI module.
2914 * @retval SPI error code in bitmap format
2915 */
HAL_SPI_GetError(SPI_HandleTypeDef * hspi)2916 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
2917 {
2918 /* Return SPI ErrorCode */
2919 return hspi->ErrorCode;
2920 }
2921
2922 /**
2923 * @}
2924 */
2925
2926 /**
2927 * @}
2928 */
2929
2930 /** @addtogroup SPI_Private_Functions
2931 * @brief Private functions
2932 * @{
2933 */
2934
2935 /**
2936 * @brief DMA SPI transmit process complete callback.
2937 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2938 * the configuration information for the specified DMA module.
2939 * @retval None
2940 */
SPI_DMATransmitCplt(DMA_HandleTypeDef * hdma)2941 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
2942 {
2943 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2944 uint32_t tickstart;
2945
2946 /* Init tickstart for timeout management*/
2947 tickstart = HAL_GetTick();
2948
2949 /* DMA Normal Mode */
2950 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2951 {
2952 /* Disable ERR interrupt */
2953 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2954
2955 /* Disable Tx DMA Request */
2956 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2957
2958 /* Check the end of the transaction */
2959 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2960 {
2961 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2962 }
2963
2964 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
2965 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
2966 {
2967 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2968 }
2969
2970 hspi->TxXferCount = 0U;
2971 hspi->State = HAL_SPI_STATE_READY;
2972
2973 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2974 {
2975 /* Call user error callback */
2976 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2977 hspi->ErrorCallback(hspi);
2978 #else
2979 HAL_SPI_ErrorCallback(hspi);
2980 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2981 return;
2982 }
2983 }
2984 /* Call user Tx complete callback */
2985 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2986 hspi->TxCpltCallback(hspi);
2987 #else
2988 HAL_SPI_TxCpltCallback(hspi);
2989 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2990 }
2991
2992 /**
2993 * @brief DMA SPI receive process complete callback.
2994 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2995 * the configuration information for the specified DMA module.
2996 * @retval None
2997 */
SPI_DMAReceiveCplt(DMA_HandleTypeDef * hdma)2998 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
2999 {
3000 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3001 uint32_t tickstart;
3002
3003 /* Init tickstart for timeout management*/
3004 tickstart = HAL_GetTick();
3005
3006 /* DMA Normal Mode */
3007 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3008 {
3009 /* Disable ERR interrupt */
3010 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3011
3012 #if (USE_SPI_CRC != 0U)
3013 /* CRC handling */
3014 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3015 {
3016 /* Wait until RXNE flag */
3017 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3018 {
3019 /* Error on the CRC reception */
3020 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3021 }
3022 /* Read CRC */
3023 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
3024 {
3025 /* Read 16bit CRC */
3026 READ_REG(hspi->Instance->DR);
3027 }
3028 else
3029 {
3030 /* Read 8bit CRC */
3031 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3032
3033 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
3034 {
3035 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3036 {
3037 /* Error on the CRC reception */
3038 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3039 }
3040 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
3041 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3042 }
3043 }
3044 }
3045 #endif /* USE_SPI_CRC */
3046
3047 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
3048 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3049
3050 /* Check the end of the transaction */
3051 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3052 {
3053 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
3054 }
3055
3056 hspi->RxXferCount = 0U;
3057 hspi->State = HAL_SPI_STATE_READY;
3058
3059 #if (USE_SPI_CRC != 0U)
3060 /* Check if CRC error occurred */
3061 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3062 {
3063 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3064 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3065 }
3066 #endif /* USE_SPI_CRC */
3067
3068 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3069 {
3070 /* Call user error callback */
3071 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3072 hspi->ErrorCallback(hspi);
3073 #else
3074 HAL_SPI_ErrorCallback(hspi);
3075 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3076 return;
3077 }
3078 }
3079 /* Call user Rx complete callback */
3080 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3081 hspi->RxCpltCallback(hspi);
3082 #else
3083 HAL_SPI_RxCpltCallback(hspi);
3084 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3085 }
3086
3087 /**
3088 * @brief DMA SPI transmit receive process complete callback.
3089 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3090 * the configuration information for the specified DMA module.
3091 * @retval None
3092 */
SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef * hdma)3093 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3094 {
3095 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3096 uint32_t tickstart;
3097
3098 /* Init tickstart for timeout management*/
3099 tickstart = HAL_GetTick();
3100
3101 /* DMA Normal Mode */
3102 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3103 {
3104 /* Disable ERR interrupt */
3105 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3106
3107 #if (USE_SPI_CRC != 0U)
3108 /* CRC handling */
3109 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3110 {
3111 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
3112 {
3113 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
3114 tickstart) != HAL_OK)
3115 {
3116 /* Error on the CRC reception */
3117 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3118 }
3119 /* Read CRC to Flush DR and RXNE flag */
3120 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3121 }
3122 else
3123 {
3124 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3125 {
3126 /* Error on the CRC reception */
3127 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3128 }
3129 /* Read CRC to Flush DR and RXNE flag */
3130 READ_REG(hspi->Instance->DR);
3131 }
3132 }
3133 #endif /* USE_SPI_CRC */
3134
3135 /* Check the end of the transaction */
3136 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3137 {
3138 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3139 }
3140
3141 /* Disable Rx/Tx DMA Request */
3142 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3143
3144 hspi->TxXferCount = 0U;
3145 hspi->RxXferCount = 0U;
3146 hspi->State = HAL_SPI_STATE_READY;
3147
3148 #if (USE_SPI_CRC != 0U)
3149 /* Check if CRC error occurred */
3150 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3151 {
3152 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3153 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3154 }
3155 #endif /* USE_SPI_CRC */
3156
3157 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3158 {
3159 /* Call user error callback */
3160 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3161 hspi->ErrorCallback(hspi);
3162 #else
3163 HAL_SPI_ErrorCallback(hspi);
3164 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3165 return;
3166 }
3167 }
3168 /* Call user TxRx complete callback */
3169 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3170 hspi->TxRxCpltCallback(hspi);
3171 #else
3172 HAL_SPI_TxRxCpltCallback(hspi);
3173 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3174 }
3175
3176 /**
3177 * @brief DMA SPI half transmit process complete callback.
3178 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3179 * the configuration information for the specified DMA module.
3180 * @retval None
3181 */
SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef * hdma)3182 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
3183 {
3184 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3185
3186 /* Call user Tx half complete callback */
3187 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3188 hspi->TxHalfCpltCallback(hspi);
3189 #else
3190 HAL_SPI_TxHalfCpltCallback(hspi);
3191 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3192 }
3193
3194 /**
3195 * @brief DMA SPI half receive process complete callback
3196 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3197 * the configuration information for the specified DMA module.
3198 * @retval None
3199 */
SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef * hdma)3200 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
3201 {
3202 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3203
3204 /* Call user Rx half complete callback */
3205 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3206 hspi->RxHalfCpltCallback(hspi);
3207 #else
3208 HAL_SPI_RxHalfCpltCallback(hspi);
3209 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3210 }
3211
3212 /**
3213 * @brief DMA SPI half transmit receive process complete callback.
3214 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3215 * the configuration information for the specified DMA module.
3216 * @retval None
3217 */
SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef * hdma)3218 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3219 {
3220 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3221
3222 /* Call user TxRx half complete callback */
3223 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3224 hspi->TxRxHalfCpltCallback(hspi);
3225 #else
3226 HAL_SPI_TxRxHalfCpltCallback(hspi);
3227 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3228 }
3229
3230 /**
3231 * @brief DMA SPI communication error callback.
3232 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3233 * the configuration information for the specified DMA module.
3234 * @retval None
3235 */
SPI_DMAError(DMA_HandleTypeDef * hdma)3236 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
3237 {
3238 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3239
3240 /* Stop the disable DMA transfer on SPI side */
3241 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3242
3243 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3244 hspi->State = HAL_SPI_STATE_READY;
3245 /* Call user error callback */
3246 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3247 hspi->ErrorCallback(hspi);
3248 #else
3249 HAL_SPI_ErrorCallback(hspi);
3250 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3251 }
3252
3253 /**
3254 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
3255 * (To be called at end of DMA Abort procedure following error occurrence).
3256 * @param hdma DMA handle.
3257 * @retval None
3258 */
SPI_DMAAbortOnError(DMA_HandleTypeDef * hdma)3259 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3260 {
3261 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3262 hspi->RxXferCount = 0U;
3263 hspi->TxXferCount = 0U;
3264
3265 /* Call user error callback */
3266 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3267 hspi->ErrorCallback(hspi);
3268 #else
3269 HAL_SPI_ErrorCallback(hspi);
3270 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3271 }
3272
3273 /**
3274 * @brief DMA SPI Tx communication abort callback, when initiated by user
3275 * (To be called at end of DMA Tx Abort procedure following user abort request).
3276 * @note When this callback is executed, User Abort complete call back is called only if no
3277 * Abort still ongoing for Rx DMA Handle.
3278 * @param hdma DMA handle.
3279 * @retval None
3280 */
SPI_DMATxAbortCallback(DMA_HandleTypeDef * hdma)3281 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3282 {
3283 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3284
3285 hspi->hdmatx->XferAbortCallback = NULL;
3286
3287 /* Disable Tx DMA Request */
3288 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3289
3290 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3291 {
3292 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3293 }
3294
3295 /* Disable SPI Peripheral */
3296 __HAL_SPI_DISABLE(hspi);
3297
3298 /* Empty the FRLVL fifo */
3299 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3300 {
3301 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3302 }
3303
3304 /* Check if an Abort process is still ongoing */
3305 if (hspi->hdmarx != NULL)
3306 {
3307 if (hspi->hdmarx->XferAbortCallback != NULL)
3308 {
3309 return;
3310 }
3311 }
3312
3313 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3314 hspi->RxXferCount = 0U;
3315 hspi->TxXferCount = 0U;
3316
3317 /* Check no error during Abort procedure */
3318 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3319 {
3320 /* Reset errorCode */
3321 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3322 }
3323
3324 /* Clear the Error flags in the SR register */
3325 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3326 __HAL_SPI_CLEAR_FREFLAG(hspi);
3327
3328 /* Restore hspi->State to Ready */
3329 hspi->State = HAL_SPI_STATE_READY;
3330
3331 /* Call user Abort complete callback */
3332 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3333 hspi->AbortCpltCallback(hspi);
3334 #else
3335 HAL_SPI_AbortCpltCallback(hspi);
3336 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3337 }
3338
3339 /**
3340 * @brief DMA SPI Rx communication abort callback, when initiated by user
3341 * (To be called at end of DMA Rx Abort procedure following user abort request).
3342 * @note When this callback is executed, User Abort complete call back is called only if no
3343 * Abort still ongoing for Tx DMA Handle.
3344 * @param hdma DMA handle.
3345 * @retval None
3346 */
SPI_DMARxAbortCallback(DMA_HandleTypeDef * hdma)3347 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3348 {
3349 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3350
3351 /* Disable SPI Peripheral */
3352 __HAL_SPI_DISABLE(hspi);
3353
3354 hspi->hdmarx->XferAbortCallback = NULL;
3355
3356 /* Disable Rx DMA Request */
3357 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3358
3359 /* Control the BSY flag */
3360 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3361 {
3362 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3363 }
3364
3365 /* Empty the FRLVL fifo */
3366 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3367 {
3368 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3369 }
3370
3371 /* Check if an Abort process is still ongoing */
3372 if (hspi->hdmatx != NULL)
3373 {
3374 if (hspi->hdmatx->XferAbortCallback != NULL)
3375 {
3376 return;
3377 }
3378 }
3379
3380 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3381 hspi->RxXferCount = 0U;
3382 hspi->TxXferCount = 0U;
3383
3384 /* Check no error during Abort procedure */
3385 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3386 {
3387 /* Reset errorCode */
3388 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3389 }
3390
3391 /* Clear the Error flags in the SR register */
3392 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3393 __HAL_SPI_CLEAR_FREFLAG(hspi);
3394
3395 /* Restore hspi->State to Ready */
3396 hspi->State = HAL_SPI_STATE_READY;
3397
3398 /* Call user Abort complete callback */
3399 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3400 hspi->AbortCpltCallback(hspi);
3401 #else
3402 HAL_SPI_AbortCpltCallback(hspi);
3403 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3404 }
3405
3406 /**
3407 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3408 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3409 * the configuration information for SPI module.
3410 * @retval None
3411 */
SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3412 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3413 {
3414 /* Receive data in packing mode */
3415 if (hspi->RxXferCount > 1U)
3416 {
3417 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3418 hspi->pRxBuffPtr += sizeof(uint16_t);
3419 hspi->RxXferCount -= 2U;
3420 if (hspi->RxXferCount == 1U)
3421 {
3422 /* Set RX Fifo threshold according the reception data length: 8bit */
3423 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3424 }
3425 }
3426 /* Receive data in 8 Bit mode */
3427 else
3428 {
3429 *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3430 hspi->pRxBuffPtr++;
3431 hspi->RxXferCount--;
3432 }
3433
3434 /* Check end of the reception */
3435 if (hspi->RxXferCount == 0U)
3436 {
3437 #if (USE_SPI_CRC != 0U)
3438 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3439 {
3440 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3441 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
3442 return;
3443 }
3444 #endif /* USE_SPI_CRC */
3445
3446 /* Disable RXNE and ERR interrupt */
3447 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3448
3449 if (hspi->TxXferCount == 0U)
3450 {
3451 SPI_CloseRxTx_ISR(hspi);
3452 }
3453 }
3454 }
3455
3456 #if (USE_SPI_CRC != 0U)
3457 /**
3458 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3459 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3460 * the configuration information for SPI module.
3461 * @retval None
3462 */
SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3463 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3464 {
3465 /* Read 8bit CRC to flush Data Regsiter */
3466 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3467
3468 hspi->CRCSize--;
3469
3470 /* Check end of the reception */
3471 if (hspi->CRCSize == 0U)
3472 {
3473 /* Disable RXNE and ERR interrupt */
3474 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3475
3476 if (hspi->TxXferCount == 0U)
3477 {
3478 SPI_CloseRxTx_ISR(hspi);
3479 }
3480 }
3481 }
3482 #endif /* USE_SPI_CRC */
3483
3484 /**
3485 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3486 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3487 * the configuration information for SPI module.
3488 * @retval None
3489 */
SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3490 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3491 {
3492 /* Transmit data in packing Bit mode */
3493 if (hspi->TxXferCount >= 2U)
3494 {
3495 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3496 hspi->pTxBuffPtr += sizeof(uint16_t);
3497 hspi->TxXferCount -= 2U;
3498 }
3499 /* Transmit data in 8 Bit mode */
3500 else
3501 {
3502 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3503 hspi->pTxBuffPtr++;
3504 hspi->TxXferCount--;
3505 }
3506
3507 /* Check the end of the transmission */
3508 if (hspi->TxXferCount == 0U)
3509 {
3510 #if (USE_SPI_CRC != 0U)
3511 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3512 {
3513 /* Set CRC Next Bit to send CRC */
3514 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3515 /* Disable TXE interrupt */
3516 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3517 return;
3518 }
3519 #endif /* USE_SPI_CRC */
3520
3521 /* Disable TXE interrupt */
3522 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3523
3524 if (hspi->RxXferCount == 0U)
3525 {
3526 SPI_CloseRxTx_ISR(hspi);
3527 }
3528 }
3529 }
3530
3531 /**
3532 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3533 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3534 * the configuration information for SPI module.
3535 * @retval None
3536 */
SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3537 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3538 {
3539 /* Receive data in 16 Bit mode */
3540 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3541 hspi->pRxBuffPtr += sizeof(uint16_t);
3542 hspi->RxXferCount--;
3543
3544 if (hspi->RxXferCount == 0U)
3545 {
3546 #if (USE_SPI_CRC != 0U)
3547 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3548 {
3549 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
3550 return;
3551 }
3552 #endif /* USE_SPI_CRC */
3553
3554 /* Disable RXNE interrupt */
3555 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3556
3557 if (hspi->TxXferCount == 0U)
3558 {
3559 SPI_CloseRxTx_ISR(hspi);
3560 }
3561 }
3562 }
3563
3564 #if (USE_SPI_CRC != 0U)
3565 /**
3566 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3567 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3568 * the configuration information for SPI module.
3569 * @retval None
3570 */
SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3571 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3572 {
3573 /* Read 16bit CRC to flush Data Regsiter */
3574 READ_REG(hspi->Instance->DR);
3575
3576 /* Disable RXNE interrupt */
3577 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3578
3579 SPI_CloseRxTx_ISR(hspi);
3580 }
3581 #endif /* USE_SPI_CRC */
3582
3583 /**
3584 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3585 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3586 * the configuration information for SPI module.
3587 * @retval None
3588 */
SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3589 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3590 {
3591 /* Transmit data in 16 Bit mode */
3592 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3593 hspi->pTxBuffPtr += sizeof(uint16_t);
3594 hspi->TxXferCount--;
3595
3596 /* Enable CRC Transmission */
3597 if (hspi->TxXferCount == 0U)
3598 {
3599 #if (USE_SPI_CRC != 0U)
3600 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3601 {
3602 /* Set CRC Next Bit to send CRC */
3603 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3604 /* Disable TXE interrupt */
3605 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3606 return;
3607 }
3608 #endif /* USE_SPI_CRC */
3609
3610 /* Disable TXE interrupt */
3611 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3612
3613 if (hspi->RxXferCount == 0U)
3614 {
3615 SPI_CloseRxTx_ISR(hspi);
3616 }
3617 }
3618 }
3619
3620 #if (USE_SPI_CRC != 0U)
3621 /**
3622 * @brief Manage the CRC 8-bit receive in Interrupt context.
3623 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3624 * the configuration information for SPI module.
3625 * @retval None
3626 */
SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3627 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3628 {
3629 /* Read 8bit CRC to flush Data Register */
3630 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3631
3632 hspi->CRCSize--;
3633
3634 if (hspi->CRCSize == 0U)
3635 {
3636 SPI_CloseRx_ISR(hspi);
3637 }
3638 }
3639 #endif /* USE_SPI_CRC */
3640
3641 /**
3642 * @brief Manage the receive 8-bit in Interrupt context.
3643 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3644 * the configuration information for SPI module.
3645 * @retval None
3646 */
SPI_RxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3647 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3648 {
3649 *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3650 hspi->pRxBuffPtr++;
3651 hspi->RxXferCount--;
3652
3653 #if (USE_SPI_CRC != 0U)
3654 /* Enable CRC Transmission */
3655 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3656 {
3657 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3658 }
3659 #endif /* USE_SPI_CRC */
3660
3661 if (hspi->RxXferCount == 0U)
3662 {
3663 #if (USE_SPI_CRC != 0U)
3664 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3665 {
3666 hspi->RxISR = SPI_RxISR_8BITCRC;
3667 return;
3668 }
3669 #endif /* USE_SPI_CRC */
3670 SPI_CloseRx_ISR(hspi);
3671 }
3672 }
3673
3674 #if (USE_SPI_CRC != 0U)
3675 /**
3676 * @brief Manage the CRC 16-bit receive in Interrupt context.
3677 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3678 * the configuration information for SPI module.
3679 * @retval None
3680 */
SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3681 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3682 {
3683 /* Read 16bit CRC to flush Data Register */
3684 READ_REG(hspi->Instance->DR);
3685
3686 /* Disable RXNE and ERR interrupt */
3687 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3688
3689 SPI_CloseRx_ISR(hspi);
3690 }
3691 #endif /* USE_SPI_CRC */
3692
3693 /**
3694 * @brief Manage the 16-bit receive in Interrupt context.
3695 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3696 * the configuration information for SPI module.
3697 * @retval None
3698 */
SPI_RxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3699 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3700 {
3701 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3702 hspi->pRxBuffPtr += sizeof(uint16_t);
3703 hspi->RxXferCount--;
3704
3705 #if (USE_SPI_CRC != 0U)
3706 /* Enable CRC Transmission */
3707 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3708 {
3709 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3710 }
3711 #endif /* USE_SPI_CRC */
3712
3713 if (hspi->RxXferCount == 0U)
3714 {
3715 #if (USE_SPI_CRC != 0U)
3716 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3717 {
3718 hspi->RxISR = SPI_RxISR_16BITCRC;
3719 return;
3720 }
3721 #endif /* USE_SPI_CRC */
3722 SPI_CloseRx_ISR(hspi);
3723 }
3724 }
3725
3726 /**
3727 * @brief Handle the data 8-bit transmit in Interrupt mode.
3728 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3729 * the configuration information for SPI module.
3730 * @retval None
3731 */
SPI_TxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3732 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3733 {
3734 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3735 hspi->pTxBuffPtr++;
3736 hspi->TxXferCount--;
3737
3738 if (hspi->TxXferCount == 0U)
3739 {
3740 #if (USE_SPI_CRC != 0U)
3741 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3742 {
3743 /* Enable CRC Transmission */
3744 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3745 }
3746 #endif /* USE_SPI_CRC */
3747 SPI_CloseTx_ISR(hspi);
3748 }
3749 }
3750
3751 /**
3752 * @brief Handle the data 16-bit transmit in Interrupt mode.
3753 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3754 * the configuration information for SPI module.
3755 * @retval None
3756 */
SPI_TxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3757 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3758 {
3759 /* Transmit data in 16 Bit mode */
3760 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3761 hspi->pTxBuffPtr += sizeof(uint16_t);
3762 hspi->TxXferCount--;
3763
3764 if (hspi->TxXferCount == 0U)
3765 {
3766 #if (USE_SPI_CRC != 0U)
3767 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3768 {
3769 /* Enable CRC Transmission */
3770 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3771 }
3772 #endif /* USE_SPI_CRC */
3773 SPI_CloseTx_ISR(hspi);
3774 }
3775 }
3776
3777 /**
3778 * @brief Handle SPI Communication Timeout.
3779 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3780 * the configuration information for SPI module.
3781 * @param Flag SPI flag to check
3782 * @param State flag state to check
3783 * @param Timeout Timeout duration
3784 * @param Tickstart tick start value
3785 * @retval HAL status
3786 */
SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Flag,FlagStatus State,uint32_t Timeout,uint32_t Tickstart)3787 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3788 uint32_t Timeout, uint32_t Tickstart)
3789 {
3790 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3791 {
3792 if (Timeout != HAL_MAX_DELAY)
3793 {
3794 if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
3795 {
3796 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3797 on both master and slave sides in order to resynchronize the master
3798 and slave for their respective CRC calculation */
3799
3800 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3801 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3802
3803 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3804 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3805 {
3806 /* Disable SPI peripheral */
3807 __HAL_SPI_DISABLE(hspi);
3808 }
3809
3810 /* Reset CRC Calculation */
3811 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3812 {
3813 SPI_RESET_CRC(hspi);
3814 }
3815
3816 hspi->State = HAL_SPI_STATE_READY;
3817
3818 /* Process Unlocked */
3819 __HAL_UNLOCK(hspi);
3820
3821 return HAL_TIMEOUT;
3822 }
3823 }
3824 }
3825
3826 return HAL_OK;
3827 }
3828
3829 /**
3830 * @brief Handle SPI FIFO Communication Timeout.
3831 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3832 * the configuration information for SPI module.
3833 * @param Fifo Fifo to check
3834 * @param State Fifo state to check
3835 * @param Timeout Timeout duration
3836 * @param Tickstart tick start value
3837 * @retval HAL status
3838 */
SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Fifo,uint32_t State,uint32_t Timeout,uint32_t Tickstart)3839 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
3840 uint32_t Timeout, uint32_t Tickstart)
3841 {
3842 while ((hspi->Instance->SR & Fifo) != State)
3843 {
3844 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
3845 {
3846 /* Read 8bit CRC to flush Data Register */
3847 READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
3848 }
3849
3850 if (Timeout != HAL_MAX_DELAY)
3851 {
3852 if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
3853 {
3854 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3855 on both master and slave sides in order to resynchronize the master
3856 and slave for their respective CRC calculation */
3857
3858 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3859 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3860
3861 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3862 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3863 {
3864 /* Disable SPI peripheral */
3865 __HAL_SPI_DISABLE(hspi);
3866 }
3867
3868 /* Reset CRC Calculation */
3869 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3870 {
3871 SPI_RESET_CRC(hspi);
3872 }
3873
3874 hspi->State = HAL_SPI_STATE_READY;
3875
3876 /* Process Unlocked */
3877 __HAL_UNLOCK(hspi);
3878
3879 return HAL_TIMEOUT;
3880 }
3881 }
3882 }
3883
3884 return HAL_OK;
3885 }
3886
3887 /**
3888 * @brief Handle the check of the RX transaction complete.
3889 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3890 * the configuration information for SPI module.
3891 * @param Timeout Timeout duration
3892 * @param Tickstart tick start value
3893 * @retval HAL status
3894 */
SPI_EndRxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)3895 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
3896 {
3897 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3898 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3899 {
3900 /* Disable SPI peripheral */
3901 __HAL_SPI_DISABLE(hspi);
3902 }
3903
3904 /* Control the BSY flag */
3905 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3906 {
3907 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3908 return HAL_TIMEOUT;
3909 }
3910
3911 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3912 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3913 {
3914 /* Empty the FRLVL fifo */
3915 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
3916 {
3917 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3918 return HAL_TIMEOUT;
3919 }
3920 }
3921 return HAL_OK;
3922 }
3923
3924 /**
3925 * @brief Handle the check of the RXTX or TX transaction complete.
3926 * @param hspi SPI handle
3927 * @param Timeout Timeout duration
3928 * @param Tickstart tick start value
3929 * @retval HAL status
3930 */
SPI_EndRxTxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)3931 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
3932 {
3933 /* Control if the TX fifo is empty */
3934 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
3935 {
3936 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3937 return HAL_TIMEOUT;
3938 }
3939
3940 /* Control the BSY flag */
3941 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3942 {
3943 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3944 return HAL_TIMEOUT;
3945 }
3946
3947 /* Control if the RX fifo is empty */
3948 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
3949 {
3950 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3951 return HAL_TIMEOUT;
3952 }
3953
3954 return HAL_OK;
3955 }
3956
3957 /**
3958 * @brief Handle the end of the RXTX transaction.
3959 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3960 * the configuration information for SPI module.
3961 * @retval None
3962 */
SPI_CloseRxTx_ISR(SPI_HandleTypeDef * hspi)3963 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
3964 {
3965 uint32_t tickstart;
3966
3967 /* Init tickstart for timeout managment*/
3968 tickstart = HAL_GetTick();
3969
3970 /* Disable ERR interrupt */
3971 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3972
3973 /* Check the end of the transaction */
3974 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3975 {
3976 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3977 }
3978
3979 #if (USE_SPI_CRC != 0U)
3980 /* Check if CRC error occurred */
3981 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
3982 {
3983 hspi->State = HAL_SPI_STATE_READY;
3984 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3985 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3986 /* Call user error callback */
3987 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3988 hspi->ErrorCallback(hspi);
3989 #else
3990 HAL_SPI_ErrorCallback(hspi);
3991 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3992 }
3993 else
3994 {
3995 #endif /* USE_SPI_CRC */
3996 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
3997 {
3998 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
3999 {
4000 hspi->State = HAL_SPI_STATE_READY;
4001 /* Call user Rx complete callback */
4002 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4003 hspi->RxCpltCallback(hspi);
4004 #else
4005 HAL_SPI_RxCpltCallback(hspi);
4006 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4007 }
4008 else
4009 {
4010 hspi->State = HAL_SPI_STATE_READY;
4011 /* Call user TxRx complete callback */
4012 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4013 hspi->TxRxCpltCallback(hspi);
4014 #else
4015 HAL_SPI_TxRxCpltCallback(hspi);
4016 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4017 }
4018 }
4019 else
4020 {
4021 hspi->State = HAL_SPI_STATE_READY;
4022 /* Call user error callback */
4023 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4024 hspi->ErrorCallback(hspi);
4025 #else
4026 HAL_SPI_ErrorCallback(hspi);
4027 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4028 }
4029 #if (USE_SPI_CRC != 0U)
4030 }
4031 #endif /* USE_SPI_CRC */
4032 }
4033
4034 /**
4035 * @brief Handle the end of the RX transaction.
4036 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4037 * the configuration information for SPI module.
4038 * @retval None
4039 */
SPI_CloseRx_ISR(SPI_HandleTypeDef * hspi)4040 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
4041 {
4042 /* Disable RXNE and ERR interrupt */
4043 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
4044
4045 /* Check the end of the transaction */
4046 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4047 {
4048 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4049 }
4050 hspi->State = HAL_SPI_STATE_READY;
4051
4052 #if (USE_SPI_CRC != 0U)
4053 /* Check if CRC error occurred */
4054 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4055 {
4056 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4057 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4058 /* Call user error callback */
4059 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4060 hspi->ErrorCallback(hspi);
4061 #else
4062 HAL_SPI_ErrorCallback(hspi);
4063 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4064 }
4065 else
4066 {
4067 #endif /* USE_SPI_CRC */
4068 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4069 {
4070 /* Call user Rx complete callback */
4071 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4072 hspi->RxCpltCallback(hspi);
4073 #else
4074 HAL_SPI_RxCpltCallback(hspi);
4075 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4076 }
4077 else
4078 {
4079 /* Call user error callback */
4080 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4081 hspi->ErrorCallback(hspi);
4082 #else
4083 HAL_SPI_ErrorCallback(hspi);
4084 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4085 }
4086 #if (USE_SPI_CRC != 0U)
4087 }
4088 #endif /* USE_SPI_CRC */
4089 }
4090
4091 /**
4092 * @brief Handle the end of the TX transaction.
4093 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4094 * the configuration information for SPI module.
4095 * @retval None
4096 */
SPI_CloseTx_ISR(SPI_HandleTypeDef * hspi)4097 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
4098 {
4099 uint32_t tickstart;
4100
4101 /* Init tickstart for timeout management*/
4102 tickstart = HAL_GetTick();
4103
4104 /* Disable TXE and ERR interrupt */
4105 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
4106
4107 /* Check the end of the transaction */
4108 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4109 {
4110 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4111 }
4112
4113 /* Clear overrun flag in 2 Lines communication mode because received is not read */
4114 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
4115 {
4116 __HAL_SPI_CLEAR_OVRFLAG(hspi);
4117 }
4118
4119 hspi->State = HAL_SPI_STATE_READY;
4120 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
4121 {
4122 /* Call user error callback */
4123 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4124 hspi->ErrorCallback(hspi);
4125 #else
4126 HAL_SPI_ErrorCallback(hspi);
4127 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4128 }
4129 else
4130 {
4131 /* Call user Rx complete callback */
4132 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4133 hspi->TxCpltCallback(hspi);
4134 #else
4135 HAL_SPI_TxCpltCallback(hspi);
4136 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4137 }
4138 }
4139
4140 /**
4141 * @brief Handle abort a Rx transaction.
4142 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4143 * the configuration information for SPI module.
4144 * @retval None
4145 */
SPI_AbortRx_ISR(SPI_HandleTypeDef * hspi)4146 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
4147 {
4148 __IO uint32_t count;
4149
4150 /* Disable SPI Peripheral */
4151 __HAL_SPI_DISABLE(hspi);
4152
4153 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4154
4155 /* Disable RXNEIE interrupt */
4156 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4157
4158 /* Check RXNEIE is disabled */
4159 do
4160 {
4161 if (count == 0U)
4162 {
4163 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4164 break;
4165 }
4166 count--;
4167 }
4168 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4169
4170 /* Control the BSY flag */
4171 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4172 {
4173 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4174 }
4175
4176 /* Empty the FRLVL fifo */
4177 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4178 {
4179 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4180 }
4181
4182 hspi->State = HAL_SPI_STATE_ABORT;
4183 }
4184
4185 /**
4186 * @brief Handle abort a Tx or Rx/Tx transaction.
4187 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4188 * the configuration information for SPI module.
4189 * @retval None
4190 */
SPI_AbortTx_ISR(SPI_HandleTypeDef * hspi)4191 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
4192 {
4193 __IO uint32_t count;
4194
4195 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4196
4197 /* Disable TXEIE interrupt */
4198 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
4199
4200 /* Check TXEIE is disabled */
4201 do
4202 {
4203 if (count == 0U)
4204 {
4205 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4206 break;
4207 }
4208 count--;
4209 }
4210 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
4211
4212 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4213 {
4214 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4215 }
4216
4217 /* Disable SPI Peripheral */
4218 __HAL_SPI_DISABLE(hspi);
4219
4220 /* Empty the FRLVL fifo */
4221 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4222 {
4223 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4224 }
4225
4226 /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
4227 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
4228 {
4229 /* Disable RXNEIE interrupt */
4230 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4231
4232 /* Check RXNEIE is disabled */
4233 do
4234 {
4235 if (count == 0U)
4236 {
4237 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4238 break;
4239 }
4240 count--;
4241 }
4242 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4243
4244 /* Control the BSY flag */
4245 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4246 {
4247 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4248 }
4249
4250 /* Empty the FRLVL fifo */
4251 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4252 {
4253 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4254 }
4255 }
4256 hspi->State = HAL_SPI_STATE_ABORT;
4257 }
4258
4259 /**
4260 * @}
4261 */
4262
4263 #endif /* HAL_SPI_MODULE_ENABLED */
4264
4265 /**
4266 * @}
4267 */
4268
4269 /**
4270 * @}
4271 */
4272
4273 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4274