1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_sram.c
4 * @author MCD Application Team
5 * @brief SRAM HAL module driver.
6 * This file provides a generic firmware to drive SRAM memories
7 * mounted as external device.
8 *
9 @verbatim
10 ==============================================================================
11 ##### How to use this driver #####
12 ==============================================================================
13 [..]
14 This driver is a generic layered driver which contains a set of APIs used to
15 control SRAM memories. It uses the FMC layer functions to interface
16 with SRAM devices.
17 The following sequence should be followed to configure the FMC to interface
18 with SRAM/PSRAM memories:
19
20 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
21 SRAM_HandleTypeDef hsram; and:
22
23 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
24 values of the structure member.
25
26 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
27 base register instance for NOR or SRAM device
28
29 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
30 base register instance for NOR or SRAM extended mode
31
32 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
33 mode timings; for example:
34 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
35 and fill its fields with the allowed values of the structure member.
36
37 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
38 performs the following sequence:
39
40 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
41 (##) Control register configuration using the FMC NORSRAM interface function
42 FMC_NORSRAM_Init()
43 (##) Timing register configuration using the FMC NORSRAM interface function
44 FMC_NORSRAM_Timing_Init()
45 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
46 FMC_NORSRAM_Extended_Timing_Init()
47 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
48
49 (#) At this stage you can perform read/write accesses from/to the memory connected
50 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
51 following APIs:
52 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
53 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
54
55 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
56 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
57
58 (#) You can continuously monitor the SRAM device HAL state by calling the function
59 HAL_SRAM_GetState()
60
61 *** Callback registration ***
62 =============================================
63 [..]
64 The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
65 allows the user to configure dynamically the driver callbacks.
66
67 Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
68 it allows to register following callbacks:
69 (+) MspInitCallback : SRAM MspInit.
70 (+) MspDeInitCallback : SRAM MspDeInit.
71 This function takes as parameters the HAL peripheral handle, the Callback ID
72 and a pointer to the user callback function.
73
74 Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
75 weak (surcharged) function. It allows to reset following callbacks:
76 (+) MspInitCallback : SRAM MspInit.
77 (+) MspDeInitCallback : SRAM MspDeInit.
78 This function) takes as parameters the HAL peripheral handle and the Callback ID.
79
80 By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
81 all callbacks are reset to the corresponding legacy weak (surcharged) functions.
82 Exception done for MspInit and MspDeInit callbacks that are respectively
83 reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
84 and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
85 If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
86 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
87
88 Callbacks can be registered/unregistered in READY state only.
89 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
90 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
91 during the Init/DeInit.
92 In that case first register the MspInit/MspDeInit user callbacks
93 using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
94 or @ref HAL_SRAM_Init function.
95
96 When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
97 not defined, the callback registering feature is not available
98 and weak (surcharged) callbacks are used.
99
100 @endverbatim
101 ******************************************************************************
102 * @attention
103 *
104 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
105 * All rights reserved.</center></h2>
106 *
107 * This software component is licensed by ST under BSD 3-Clause license,
108 * the "License"; You may not use this file except in compliance with the
109 * License. You may obtain a copy of the License at:
110 * opensource.org/licenses/BSD-3-Clause
111 *
112 ******************************************************************************
113 */
114
115 /* Includes ------------------------------------------------------------------*/
116 #include "stm32l4xx_hal.h"
117
118 #if defined FMC_BANK1
119
120 /** @addtogroup STM32L4xx_HAL_Driver
121 * @{
122 */
123
124 #ifdef HAL_SRAM_MODULE_ENABLED
125
126 /** @defgroup SRAM SRAM
127 * @brief SRAM driver modules
128 * @{
129 */
130
131 /**
132 @cond 0
133 */
134 /* Private typedef -----------------------------------------------------------*/
135 /* Private define ------------------------------------------------------------*/
136 /* Private macro -------------------------------------------------------------*/
137 /* Private variables ---------------------------------------------------------*/
138 /* Private function prototypes -----------------------------------------------*/
139 static void SRAM_DMACplt (DMA_HandleTypeDef *hdma);
140 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
141 static void SRAM_DMAError (DMA_HandleTypeDef *hdma);
142 /**
143 @endcond
144 */
145
146 /* Exported functions --------------------------------------------------------*/
147
148 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
149 * @{
150 */
151
152 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
153 * @brief Initialization and Configuration functions.
154 *
155 @verbatim
156 ==============================================================================
157 ##### SRAM Initialization and de_initialization functions #####
158 ==============================================================================
159 [..] This section provides functions allowing to initialize/de-initialize
160 the SRAM memory
161
162 @endverbatim
163 * @{
164 */
165
166 /**
167 * @brief Performs the SRAM device initialization sequence
168 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
169 * the configuration information for SRAM module.
170 * @param Timing Pointer to SRAM control timing structure
171 * @param ExtTiming Pointer to SRAM extended mode timing structure
172 * @retval HAL status
173 */
HAL_SRAM_Init(SRAM_HandleTypeDef * hsram,FMC_NORSRAM_TimingTypeDef * Timing,FMC_NORSRAM_TimingTypeDef * ExtTiming)174 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
175 {
176 /* Check the SRAM handle parameter */
177 if (hsram == NULL)
178 {
179 return HAL_ERROR;
180 }
181
182 if (hsram->State == HAL_SRAM_STATE_RESET)
183 {
184 /* Allocate lock resource and initialize it */
185 hsram->Lock = HAL_UNLOCKED;
186
187 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
188 if(hsram->MspInitCallback == NULL)
189 {
190 hsram->MspInitCallback = HAL_SRAM_MspInit;
191 }
192 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
193 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
194
195 /* Init the low level hardware */
196 hsram->MspInitCallback(hsram);
197 #else
198 /* Initialize the low level hardware (MSP) */
199 HAL_SRAM_MspInit(hsram);
200 #endif
201 }
202
203 /* Initialize SRAM control Interface */
204 (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
205
206 /* Initialize SRAM timing Interface */
207 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
208
209 /* Initialize SRAM extended mode timing Interface */
210 (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
211
212 /* Enable the NORSRAM device */
213 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
214
215 /* Initialize the SRAM controller state */
216 hsram->State = HAL_SRAM_STATE_READY;
217
218 return HAL_OK;
219 }
220
221 /**
222 * @brief Performs the SRAM device De-initialization sequence.
223 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
224 * the configuration information for SRAM module.
225 * @retval HAL status
226 */
HAL_SRAM_DeInit(SRAM_HandleTypeDef * hsram)227 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
228 {
229 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
230 if(hsram->MspDeInitCallback == NULL)
231 {
232 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
233 }
234
235 /* DeInit the low level hardware */
236 hsram->MspDeInitCallback(hsram);
237 #else
238 /* De-Initialize the low level hardware (MSP) */
239 HAL_SRAM_MspDeInit(hsram);
240 #endif
241
242 /* Configure the SRAM registers with their reset values */
243 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
244
245 /* Reset the SRAM controller state */
246 hsram->State = HAL_SRAM_STATE_RESET;
247
248 /* Release Lock */
249 __HAL_UNLOCK(hsram);
250
251 return HAL_OK;
252 }
253
254 /**
255 * @brief SRAM MSP Init.
256 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
257 * the configuration information for SRAM module.
258 * @retval None
259 */
HAL_SRAM_MspInit(SRAM_HandleTypeDef * hsram)260 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
261 {
262 /* Prevent unused argument(s) compilation warning */
263 UNUSED(hsram);
264
265 /* NOTE : This function Should not be modified, when the callback is needed,
266 the HAL_SRAM_MspInit could be implemented in the user file
267 */
268 }
269
270 /**
271 * @brief SRAM MSP DeInit.
272 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
273 * the configuration information for SRAM module.
274 * @retval None
275 */
HAL_SRAM_MspDeInit(SRAM_HandleTypeDef * hsram)276 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
277 {
278 /* Prevent unused argument(s) compilation warning */
279 UNUSED(hsram);
280
281 /* NOTE : This function Should not be modified, when the callback is needed,
282 the HAL_SRAM_MspDeInit could be implemented in the user file
283 */
284 }
285
286 /**
287 * @brief DMA transfer complete callback.
288 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
289 * the configuration information for SRAM module.
290 * @retval None
291 */
HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef * hdma)292 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
293 {
294 /* Prevent unused argument(s) compilation warning */
295 UNUSED(hdma);
296
297 /* NOTE : This function Should not be modified, when the callback is needed,
298 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
299 */
300 }
301
302 /**
303 * @brief DMA transfer complete error callback.
304 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
305 * the configuration information for SRAM module.
306 * @retval None
307 */
HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef * hdma)308 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
309 {
310 /* Prevent unused argument(s) compilation warning */
311 UNUSED(hdma);
312
313 /* NOTE : This function Should not be modified, when the callback is needed,
314 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
315 */
316 }
317
318 /**
319 * @}
320 */
321
322 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
323 * @brief Input Output and memory control functions
324 *
325 @verbatim
326 ==============================================================================
327 ##### SRAM Input and Output functions #####
328 ==============================================================================
329 [..]
330 This section provides functions allowing to use and control the SRAM memory
331
332 @endverbatim
333 * @{
334 */
335
336 /**
337 * @brief Reads 8-bit buffer from SRAM memory.
338 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
339 * the configuration information for SRAM module.
340 * @param pAddress Pointer to read start address
341 * @param pDstBuffer Pointer to destination buffer
342 * @param BufferSize Size of the buffer to read from memory
343 * @retval HAL status
344 */
HAL_SRAM_Read_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)345 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
346 {
347 uint32_t size;
348 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
349 uint8_t * pdestbuff = pDstBuffer;
350 HAL_SRAM_StateTypeDef state = hsram->State;
351
352 /* Check the SRAM controller state */
353 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
354 {
355 /* Process Locked */
356 __HAL_LOCK(hsram);
357
358 /* Update the SRAM controller state */
359 hsram->State = HAL_SRAM_STATE_BUSY;
360
361 /* Read data from memory */
362 for (size = BufferSize; size != 0U; size--)
363 {
364 *pdestbuff = *psramaddress;
365 pdestbuff++;
366 psramaddress++;
367 }
368
369 /* Update the SRAM controller state */
370 hsram->State = state;
371
372 /* Process unlocked */
373 __HAL_UNLOCK(hsram);
374 }
375 else
376 {
377 return HAL_ERROR;
378 }
379
380 return HAL_OK;
381 }
382
383 /**
384 * @brief Writes 8-bit buffer to SRAM memory.
385 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
386 * the configuration information for SRAM module.
387 * @param pAddress Pointer to write start address
388 * @param pSrcBuffer Pointer to source buffer to write
389 * @param BufferSize Size of the buffer to write to memory
390 * @retval HAL status
391 */
HAL_SRAM_Write_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)392 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
393 {
394 uint32_t size;
395 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
396 uint8_t * psrcbuff = pSrcBuffer;
397
398 /* Check the SRAM controller state */
399 if (hsram->State == HAL_SRAM_STATE_READY)
400 {
401 /* Process Locked */
402 __HAL_LOCK(hsram);
403
404 /* Update the SRAM controller state */
405 hsram->State = HAL_SRAM_STATE_BUSY;
406
407 /* Write data to memory */
408 for (size = BufferSize; size != 0U; size--)
409 {
410 *psramaddress = *psrcbuff;
411 psrcbuff++;
412 psramaddress++;
413 }
414
415 /* Update the SRAM controller state */
416 hsram->State = HAL_SRAM_STATE_READY;
417
418 /* Process unlocked */
419 __HAL_UNLOCK(hsram);
420 }
421 else
422 {
423 return HAL_ERROR;
424 }
425
426 return HAL_OK;
427 }
428
429 /**
430 * @brief Reads 16-bit buffer from SRAM memory.
431 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
432 * the configuration information for SRAM module.
433 * @param pAddress Pointer to read start address
434 * @param pDstBuffer Pointer to destination buffer
435 * @param BufferSize Size of the buffer to read from memory
436 * @retval HAL status
437 */
HAL_SRAM_Read_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)438 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
439 {
440 uint32_t size;
441 __IO uint32_t *psramaddress = pAddress;
442 uint16_t *pdestbuff = pDstBuffer;
443 uint8_t limit;
444 HAL_SRAM_StateTypeDef state = hsram->State;
445
446 /* Check the SRAM controller state */
447 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
448 {
449 /* Process Locked */
450 __HAL_LOCK(hsram);
451
452 /* Update the SRAM controller state */
453 hsram->State = HAL_SRAM_STATE_BUSY;
454
455 /* Check if the size is a 32-bits mulitple */
456 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
457
458 /* Read data from memory */
459 for (size = BufferSize; size != limit; size-=2U)
460 {
461 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
462 pdestbuff++;
463 *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
464 pdestbuff++;
465 psramaddress++;
466 }
467
468 /* Read last 16-bits if size is not 32-bits multiple */
469 if (limit != 0U)
470 {
471 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
472 }
473
474 /* Update the SRAM controller state */
475 hsram->State = state;
476
477 /* Process unlocked */
478 __HAL_UNLOCK(hsram);
479 }
480 else
481 {
482 return HAL_ERROR;
483 }
484
485 return HAL_OK;
486 }
487
488 /**
489 * @brief Writes 16-bit buffer to SRAM memory.
490 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
491 * the configuration information for SRAM module.
492 * @param pAddress Pointer to write start address
493 * @param pSrcBuffer Pointer to source buffer to write
494 * @param BufferSize Size of the buffer to write to memory
495 * @retval HAL status
496 */
HAL_SRAM_Write_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)497 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
498 {
499 uint32_t size;
500 __IO uint32_t *psramaddress = pAddress;
501 uint16_t * psrcbuff = pSrcBuffer;
502 uint8_t limit;
503
504 /* Check the SRAM controller state */
505 if (hsram->State == HAL_SRAM_STATE_READY)
506 {
507 /* Process Locked */
508 __HAL_LOCK(hsram);
509
510 /* Update the SRAM controller state */
511 hsram->State = HAL_SRAM_STATE_BUSY;
512
513 /* Check if the size is a 32-bits mulitple */
514 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
515
516 /* Write data to memory */
517 for (size = BufferSize; size != limit; size-=2U)
518 {
519 *psramaddress = (uint32_t)(*psrcbuff);
520 psrcbuff++;
521 *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
522 psrcbuff++;
523 psramaddress++;
524 }
525
526 /* Write last 16-bits if size is not 32-bits multiple */
527 if (limit != 0U)
528 {
529 *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
530 }
531
532 /* Update the SRAM controller state */
533 hsram->State = HAL_SRAM_STATE_READY;
534
535 /* Process unlocked */
536 __HAL_UNLOCK(hsram);
537 }
538 else
539 {
540 return HAL_ERROR;
541 }
542
543 return HAL_OK;
544 }
545
546 /**
547 * @brief Reads 32-bit buffer from SRAM memory.
548 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
549 * the configuration information for SRAM module.
550 * @param pAddress Pointer to read start address
551 * @param pDstBuffer Pointer to destination buffer
552 * @param BufferSize Size of the buffer to read from memory
553 * @retval HAL status
554 */
HAL_SRAM_Read_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)555 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
556 {
557 uint32_t size;
558 __IO uint32_t * psramaddress = pAddress;
559 uint32_t * pdestbuff = pDstBuffer;
560 HAL_SRAM_StateTypeDef state = hsram->State;
561
562 /* Check the SRAM controller state */
563 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
564 {
565 /* Process Locked */
566 __HAL_LOCK(hsram);
567
568 /* Update the SRAM controller state */
569 hsram->State = HAL_SRAM_STATE_BUSY;
570
571 /* Read data from memory */
572 for (size = BufferSize; size != 0U; size--)
573 {
574 *pdestbuff = *psramaddress;
575 pdestbuff++;
576 psramaddress++;
577 }
578
579 /* Update the SRAM controller state */
580 hsram->State = state;
581
582 /* Process unlocked */
583 __HAL_UNLOCK(hsram);
584 }
585 else
586 {
587 return HAL_ERROR;
588 }
589
590 return HAL_OK;
591 }
592
593 /**
594 * @brief Writes 32-bit buffer to SRAM memory.
595 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
596 * the configuration information for SRAM module.
597 * @param pAddress Pointer to write start address
598 * @param pSrcBuffer Pointer to source buffer to write
599 * @param BufferSize Size of the buffer to write to memory
600 * @retval HAL status
601 */
HAL_SRAM_Write_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)602 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
603 {
604 uint32_t size;
605 __IO uint32_t * psramaddress = pAddress;
606 uint32_t * psrcbuff = pSrcBuffer;
607
608 /* Check the SRAM controller state */
609 if (hsram->State == HAL_SRAM_STATE_READY)
610 {
611 /* Process Locked */
612 __HAL_LOCK(hsram);
613
614 /* Update the SRAM controller state */
615 hsram->State = HAL_SRAM_STATE_BUSY;
616
617 /* Write data to memory */
618 for (size = BufferSize; size != 0U; size--)
619 {
620 *psramaddress = *psrcbuff;
621 psrcbuff++;
622 psramaddress++;
623 }
624
625 /* Update the SRAM controller state */
626 hsram->State = HAL_SRAM_STATE_READY;
627
628 /* Process unlocked */
629 __HAL_UNLOCK(hsram);
630 }
631 else
632 {
633 return HAL_ERROR;
634 }
635
636 return HAL_OK;
637 }
638
639 /**
640 * @brief Reads a Words data from the SRAM memory using DMA transfer.
641 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
642 * the configuration information for SRAM module.
643 * @param pAddress Pointer to read start address
644 * @param pDstBuffer Pointer to destination buffer
645 * @param BufferSize Size of the buffer to read from memory
646 * @retval HAL status
647 */
HAL_SRAM_Read_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)648 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
649 {
650 HAL_StatusTypeDef status;
651 HAL_SRAM_StateTypeDef state = hsram->State;
652
653 /* Check the SRAM controller state */
654 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
655 {
656 /* Process Locked */
657 __HAL_LOCK(hsram);
658
659 /* Update the SRAM controller state */
660 hsram->State = HAL_SRAM_STATE_BUSY;
661
662 /* Configure DMA user callbacks */
663 if (state == HAL_SRAM_STATE_READY)
664 {
665 hsram->hdma->XferCpltCallback = SRAM_DMACplt;
666 }
667 else
668 {
669 hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
670 }
671 hsram->hdma->XferErrorCallback = SRAM_DMAError;
672
673 /* Enable the DMA Stream */
674 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
675
676 /* Process unlocked */
677 __HAL_UNLOCK(hsram);
678 }
679 else
680 {
681 return HAL_ERROR;
682 }
683
684 return status;
685 }
686
687 /**
688 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
689 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
690 * the configuration information for SRAM module.
691 * @param pAddress Pointer to write start address
692 * @param pSrcBuffer Pointer to source buffer to write
693 * @param BufferSize Size of the buffer to write to memory
694 * @retval HAL status
695 */
HAL_SRAM_Write_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)696 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
697 {
698 HAL_StatusTypeDef status;
699
700 /* Check the SRAM controller state */
701 if (hsram->State == HAL_SRAM_STATE_READY)
702 {
703 /* Process Locked */
704 __HAL_LOCK(hsram);
705
706 /* Update the SRAM controller state */
707 hsram->State = HAL_SRAM_STATE_BUSY;
708
709 /* Configure DMA user callbacks */
710 hsram->hdma->XferCpltCallback = SRAM_DMACplt;
711 hsram->hdma->XferErrorCallback = SRAM_DMAError;
712
713 /* Enable the DMA Stream */
714 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
715
716 /* Process unlocked */
717 __HAL_UNLOCK(hsram);
718 }
719 else
720 {
721 return HAL_ERROR;
722 }
723
724 return status;
725 }
726
727 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
728 /**
729 * @brief Register a User SRAM Callback
730 * To be used instead of the weak (surcharged) predefined callback
731 * @param hsram : SRAM handle
732 * @param CallbackId : ID of the callback to be registered
733 * This parameter can be one of the following values:
734 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
735 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
736 * @param pCallback : pointer to the Callback function
737 * @retval status
738 */
HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_CallbackTypeDef pCallback)739 HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
740 {
741 HAL_StatusTypeDef status = HAL_OK;
742 HAL_SRAM_StateTypeDef state;
743
744 if(pCallback == NULL)
745 {
746 return HAL_ERROR;
747 }
748
749 /* Process locked */
750 __HAL_LOCK(hsram);
751
752 state = hsram->State;
753 if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
754 {
755 switch (CallbackId)
756 {
757 case HAL_SRAM_MSP_INIT_CB_ID :
758 hsram->MspInitCallback = pCallback;
759 break;
760 case HAL_SRAM_MSP_DEINIT_CB_ID :
761 hsram->MspDeInitCallback = pCallback;
762 break;
763 default :
764 /* update return status */
765 status = HAL_ERROR;
766 break;
767 }
768 }
769 else
770 {
771 /* update return status */
772 status = HAL_ERROR;
773 }
774
775 /* Release Lock */
776 __HAL_UNLOCK(hsram);
777 return status;
778 }
779
780 /**
781 * @brief Unregister a User SRAM Callback
782 * SRAM Callback is redirected to the weak (surcharged) predefined callback
783 * @param hsram : SRAM handle
784 * @param CallbackId : ID of the callback to be unregistered
785 * This parameter can be one of the following values:
786 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
787 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
788 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
789 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
790 * @retval status
791 */
HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId)792 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
793 {
794 HAL_StatusTypeDef status = HAL_OK;
795 HAL_SRAM_StateTypeDef state;
796
797 /* Process locked */
798 __HAL_LOCK(hsram);
799
800 state = hsram->State;
801 if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
802 {
803 switch (CallbackId)
804 {
805 case HAL_SRAM_MSP_INIT_CB_ID :
806 hsram->MspInitCallback = HAL_SRAM_MspInit;
807 break;
808 case HAL_SRAM_MSP_DEINIT_CB_ID :
809 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
810 break;
811 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
812 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
813 break;
814 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
815 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
816 break;
817 default :
818 /* update return status */
819 status = HAL_ERROR;
820 break;
821 }
822 }
823 else if(state == HAL_SRAM_STATE_RESET)
824 {
825 switch (CallbackId)
826 {
827 case HAL_SRAM_MSP_INIT_CB_ID :
828 hsram->MspInitCallback = HAL_SRAM_MspInit;
829 break;
830 case HAL_SRAM_MSP_DEINIT_CB_ID :
831 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
832 break;
833 default :
834 /* update return status */
835 status = HAL_ERROR;
836 break;
837 }
838 }
839 else
840 {
841 /* update return status */
842 status = HAL_ERROR;
843 }
844
845 /* Release Lock */
846 __HAL_UNLOCK(hsram);
847 return status;
848 }
849
850 /**
851 * @brief Register a User SRAM Callback for DMA transfers
852 * To be used instead of the weak (surcharged) predefined callback
853 * @param hsram : SRAM handle
854 * @param CallbackId : ID of the callback to be registered
855 * This parameter can be one of the following values:
856 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
857 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
858 * @param pCallback : pointer to the Callback function
859 * @retval status
860 */
HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_DmaCallbackTypeDef pCallback)861 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
862 {
863 HAL_StatusTypeDef status = HAL_OK;
864 HAL_SRAM_StateTypeDef state;
865
866 if(pCallback == NULL)
867 {
868 return HAL_ERROR;
869 }
870
871 /* Process locked */
872 __HAL_LOCK(hsram);
873
874 state = hsram->State;
875 if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
876 {
877 switch (CallbackId)
878 {
879 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
880 hsram->DmaXferCpltCallback = pCallback;
881 break;
882 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
883 hsram->DmaXferErrorCallback = pCallback;
884 break;
885 default :
886 /* update return status */
887 status = HAL_ERROR;
888 break;
889 }
890 }
891 else
892 {
893 /* update return status */
894 status = HAL_ERROR;
895 }
896
897 /* Release Lock */
898 __HAL_UNLOCK(hsram);
899 return status;
900 }
901 #endif
902
903 /**
904 * @}
905 */
906
907 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
908 * @brief Control functions
909 *
910 @verbatim
911 ==============================================================================
912 ##### SRAM Control functions #####
913 ==============================================================================
914 [..]
915 This subsection provides a set of functions allowing to control dynamically
916 the SRAM interface.
917
918 @endverbatim
919 * @{
920 */
921
922 /**
923 * @brief Enables dynamically SRAM write operation.
924 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
925 * the configuration information for SRAM module.
926 * @retval HAL status
927 */
HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef * hsram)928 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
929 {
930 /* Check the SRAM controller state */
931 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
932 {
933 /* Process Locked */
934 __HAL_LOCK(hsram);
935
936 /* Update the SRAM controller state */
937 hsram->State = HAL_SRAM_STATE_BUSY;
938
939 /* Enable write operation */
940 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
941
942 /* Update the SRAM controller state */
943 hsram->State = HAL_SRAM_STATE_READY;
944
945 /* Process unlocked */
946 __HAL_UNLOCK(hsram);
947 }
948 else
949 {
950 return HAL_ERROR;
951 }
952
953 return HAL_OK;
954 }
955
956 /**
957 * @brief Disables dynamically SRAM write operation.
958 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
959 * the configuration information for SRAM module.
960 * @retval HAL status
961 */
HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef * hsram)962 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
963 {
964 /* Check the SRAM controller state */
965 if(hsram->State == HAL_SRAM_STATE_READY)
966 {
967 /* Process Locked */
968 __HAL_LOCK(hsram);
969
970 /* Update the SRAM controller state */
971 hsram->State = HAL_SRAM_STATE_BUSY;
972
973 /* Disable write operation */
974 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
975
976 /* Update the SRAM controller state */
977 hsram->State = HAL_SRAM_STATE_PROTECTED;
978
979 /* Process unlocked */
980 __HAL_UNLOCK(hsram);
981 }
982 else
983 {
984 return HAL_ERROR;
985 }
986
987 return HAL_OK;
988 }
989
990 /**
991 * @}
992 */
993
994 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
995 * @brief Peripheral State functions
996 *
997 @verbatim
998 ==============================================================================
999 ##### SRAM State functions #####
1000 ==============================================================================
1001 [..]
1002 This subsection permits to get in run-time the status of the SRAM controller
1003 and the data flow.
1004
1005 @endverbatim
1006 * @{
1007 */
1008
1009 /**
1010 * @brief Returns the SRAM controller state
1011 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
1012 * the configuration information for SRAM module.
1013 * @retval HAL state
1014 */
HAL_SRAM_GetState(SRAM_HandleTypeDef * hsram)1015 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
1016 {
1017 return hsram->State;
1018 }
1019
1020 /**
1021 * @}
1022 */
1023
1024 /**
1025 * @}
1026 */
1027
1028 /**
1029 @cond 0
1030 */
1031 /**
1032 * @brief DMA SRAM process complete callback.
1033 * @param hdma : DMA handle
1034 * @retval None
1035 */
SRAM_DMACplt(DMA_HandleTypeDef * hdma)1036 static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
1037 {
1038 SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
1039
1040 /* Disable the DMA channel */
1041 __HAL_DMA_DISABLE(hdma);
1042
1043 /* Update the SRAM controller state */
1044 hsram->State = HAL_SRAM_STATE_READY;
1045
1046 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1047 hsram->DmaXferCpltCallback(hdma);
1048 #else
1049 HAL_SRAM_DMA_XferCpltCallback(hdma);
1050 #endif
1051 }
1052
1053 /**
1054 * @brief DMA SRAM process complete callback.
1055 * @param hdma : DMA handle
1056 * @retval None
1057 */
SRAM_DMACpltProt(DMA_HandleTypeDef * hdma)1058 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
1059 {
1060 SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
1061
1062 /* Disable the DMA channel */
1063 __HAL_DMA_DISABLE(hdma);
1064
1065 /* Update the SRAM controller state */
1066 hsram->State = HAL_SRAM_STATE_PROTECTED;
1067
1068 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1069 hsram->DmaXferCpltCallback(hdma);
1070 #else
1071 HAL_SRAM_DMA_XferCpltCallback(hdma);
1072 #endif
1073 }
1074
1075 /**
1076 * @brief DMA SRAM error callback.
1077 * @param hdma : DMA handle
1078 * @retval None
1079 */
SRAM_DMAError(DMA_HandleTypeDef * hdma)1080 static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
1081 {
1082 SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
1083
1084 /* Disable the DMA channel */
1085 __HAL_DMA_DISABLE(hdma);
1086
1087 /* Update the SRAM controller state */
1088 hsram->State = HAL_SRAM_STATE_ERROR;
1089
1090 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1091 hsram->DmaXferErrorCallback(hdma);
1092 #else
1093 HAL_SRAM_DMA_XferErrorCallback(hdma);
1094 #endif
1095 }
1096 /**
1097 @endcond
1098 */
1099
1100 /**
1101 * @}
1102 */
1103
1104 #endif /* HAL_SRAM_MODULE_ENABLED */
1105
1106 /**
1107 * @}
1108 */
1109
1110 #endif /* FMC_BANK1 */
1111
1112 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1113