1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef STM32L4xx_HAL_H 23 #define STM32L4xx_HAL_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32l4xx_hal_conf.h" 31 32 /** @addtogroup STM32L4xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup HAL 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup HAL_Exported_Types HAL Exported Types 42 * @{ 43 */ 44 45 /** @defgroup HAL_TICK_FREQ Tick Frequency 46 * @{ 47 */ 48 typedef enum 49 { 50 HAL_TICK_FREQ_10HZ = 100U, 51 HAL_TICK_FREQ_100HZ = 10U, 52 HAL_TICK_FREQ_1KHZ = 1U, 53 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 54 } HAL_TickFreqTypeDef; 55 /** 56 * @} 57 */ 58 59 /** 60 * @} 61 */ 62 63 /* Exported constants --------------------------------------------------------*/ 64 65 /** @defgroup HAL_Exported_Constants HAL Exported Constants 66 * @{ 67 */ 68 69 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 70 * @{ 71 */ 72 73 /** @defgroup SYSCFG_BootMode Boot Mode 74 * @{ 75 */ 76 #define SYSCFG_BOOT_MAINFLASH 0U 77 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 78 79 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 80 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 81 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ 82 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 83 #define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1 84 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 85 /* STM32L496xx || STM32L4A6xx || */ 86 /* STM32L4P5xx || STM32L4Q5xx || */ 87 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 88 89 #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) 90 91 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 92 #define SYSCFG_BOOT_OCTOPSPI1 (SYSCFG_MEMRMP_MEM_MODE_2) 93 #define SYSCFG_BOOT_OCTOPSPI2 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0) 94 #else 95 #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) 96 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 97 98 /** 99 * @} 100 */ 101 102 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 103 * @{ 104 */ 105 #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 106 #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 107 #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 108 #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 109 #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 110 #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 111 112 /** 113 * @} 114 */ 115 116 /** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31) 117 * @{ 118 */ 119 #define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ 120 #define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ 121 #define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ 122 #define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ 123 #define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ 124 #define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ 125 #define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ 126 #define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ 127 #define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ 128 #define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ 129 #define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ 130 #define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ 131 #define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ 132 #define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ 133 #define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ 134 #define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ 135 #if defined(SYSCFG_SWPR_PAGE31) 136 #define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ 137 #define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ 138 #define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ 139 #define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ 140 #define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ 141 #define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ 142 #define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ 143 #define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ 144 #define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ 145 #define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ 146 #define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ 147 #define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ 148 #define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ 149 #define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ 150 #define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ 151 #define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ 152 #endif /* SYSCFG_SWPR_PAGE31 */ 153 154 /** 155 * @} 156 */ 157 158 #if defined(SYSCFG_SWPR2_PAGE63) 159 /** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63) 160 * @{ 161 */ 162 #define SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */ 163 #define SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */ 164 #define SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */ 165 #define SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */ 166 #define SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */ 167 #define SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */ 168 #define SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */ 169 #define SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */ 170 #define SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */ 171 #define SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */ 172 #define SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */ 173 #define SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */ 174 #define SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */ 175 #define SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */ 176 #define SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */ 177 #define SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */ 178 #define SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */ 179 #define SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */ 180 #define SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */ 181 #define SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */ 182 #define SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */ 183 #define SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */ 184 #define SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */ 185 #define SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */ 186 #define SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */ 187 #define SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */ 188 #define SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */ 189 #define SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */ 190 #define SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */ 191 #define SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */ 192 #define SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */ 193 #define SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */ 194 195 /** 196 * @} 197 */ 198 #endif /* SYSCFG_SWPR2_PAGE63 */ 199 200 #if defined(VREFBUF) 201 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 202 * @{ 203 */ 204 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0U /*!< Voltage reference scale 0 (VREF_OUT1) */ 205 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ 206 207 /** 208 * @} 209 */ 210 211 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 212 * @{ 213 */ 214 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 215 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 216 217 /** 218 * @} 219 */ 220 #endif /* VREFBUF */ 221 222 /** @defgroup SYSCFG_flags_definition Flags 223 * @{ 224 */ 225 226 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ 227 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ 228 229 /** 230 * @} 231 */ 232 233 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 234 * @{ 235 */ 236 237 /** @brief Fast-mode Plus driving capability on a specific GPIO 238 */ 239 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 240 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 241 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) 242 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 243 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ 244 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) 245 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 246 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ 247 248 /** 249 * @} 250 */ 251 252 /** 253 * @} 254 */ 255 256 /** 257 * @} 258 */ 259 260 /* Exported macros -----------------------------------------------------------*/ 261 /** @defgroup HAL_Exported_Macros HAL Exported Macros 262 * @{ 263 */ 264 265 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 266 * @{ 267 */ 268 269 /** @brief Freeze/Unfreeze Peripherals in Debug mode 270 */ 271 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 272 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 273 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 274 #endif 275 276 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 277 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 278 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 279 #endif 280 281 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 282 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 283 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 284 #endif 285 286 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) 287 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 288 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 289 #endif 290 291 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 292 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 293 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 294 #endif 295 296 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 297 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 298 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 299 #endif 300 301 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) 302 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 303 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 304 #endif 305 306 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 307 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 308 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 309 #endif 310 311 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 312 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 313 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 314 #endif 315 316 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 317 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 318 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 319 #endif 320 321 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 322 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 323 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 324 #endif 325 326 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) 327 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 328 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 329 #endif 330 331 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) 332 #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 333 #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 334 #endif 335 336 #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP) 337 #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) 338 #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) 339 #endif 340 341 #if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP) 342 #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) 343 #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) 344 #endif 345 346 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 347 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 348 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 349 #endif 350 351 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 352 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 353 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 354 #endif 355 356 #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) 357 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 358 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 359 #endif 360 361 #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) 362 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 363 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 364 #endif 365 366 #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) 367 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 368 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 369 #endif 370 371 #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) 372 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 373 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 374 #endif 375 376 #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) 377 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 378 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 379 #endif 380 381 /** 382 * @} 383 */ 384 385 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 386 * @{ 387 */ 388 389 /** @brief Main Flash memory mapped at 0x00000000. 390 */ 391 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 392 393 /** @brief System Flash memory mapped at 0x00000000. 394 */ 395 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) 396 397 /** @brief Embedded SRAM mapped at 0x00000000. 398 */ 399 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) 400 401 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 402 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 403 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ 404 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 405 406 /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. 407 */ 408 #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) 409 410 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 411 /* STM32L496xx || STM32L4A6xx || */ 412 /* STM32L4P5xx || STM32L4Q5xx || */ 413 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 414 415 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 416 417 /** @brief OCTOSPI mapped at 0x00000000. 418 */ 419 #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2)) 420 #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0)) 421 422 #else 423 424 /** @brief QUADSPI mapped at 0x00000000. 425 */ 426 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) 427 428 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 429 430 /** 431 * @brief Return the boot mode as configured by user. 432 * @retval The boot mode as configured by user. The returned value can be one 433 * of the following values: 434 * @arg @ref SYSCFG_BOOT_MAINFLASH 435 * @arg @ref SYSCFG_BOOT_SYSTEMFLASH 436 @if STM32L486xx 437 * @arg @ref SYSCFG_BOOT_FMC 438 @endif 439 * @arg @ref SYSCFG_BOOT_SRAM 440 @if STM32L422xx 441 * @arg @ref SYSCFG_BOOT_QUADSPI 442 @endif 443 @if STM32L443xx 444 * @arg @ref SYSCFG_BOOT_QUADSPI 445 @endif 446 @if STM32L462xx 447 * @arg @ref SYSCFG_BOOT_QUADSPI 448 @endif 449 @if STM32L486xx 450 * @arg @ref SYSCFG_BOOT_QUADSPI 451 @endif 452 */ 453 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 454 455 /** @brief SRAM2 page 0 to 31 write protection enable macro 456 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP 457 * @note Write protection can only be disabled by a system reset 458 */ 459 #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 460 SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ 461 }while(0) 462 463 #if defined(SYSCFG_SWPR2_PAGE63) 464 /** @brief SRAM2 page 32 to 63 write protection enable macro 465 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63 466 * @note Write protection can only be disabled by a system reset 467 */ 468 #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 469 SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\ 470 }while(0) 471 #endif /* SYSCFG_SWPR2_PAGE63 */ 472 473 /** @brief SRAM2 page write protection unlock prior to erase 474 * @note Writing a wrong key reactivates the write protection 475 */ 476 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ 477 SYSCFG->SKR = 0x53;\ 478 }while(0) 479 480 /** @brief SRAM2 erase 481 * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase 482 */ 483 #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER) 484 485 /** @brief Floating Point Unit interrupt enable/disable macros 486 * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts 487 */ 488 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 489 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 490 }while(0) 491 492 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 493 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 494 }while(0) 495 496 /** @brief SYSCFG Break ECC lock. 497 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 498 * @note The selected configuration is locked and can be unlocked only by system reset. 499 */ 500 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 501 502 /** @brief SYSCFG Break Cortex-M4 Lockup lock. 503 * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 504 * @note The selected configuration is locked and can be unlocked only by system reset. 505 */ 506 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 507 508 /** @brief SYSCFG Break PVD lock. 509 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. 510 * @note The selected configuration is locked and can be unlocked only by system reset. 511 */ 512 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 513 514 /** @brief SYSCFG Break SRAM2 parity lock. 515 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. 516 * @note The selected configuration is locked and can be unlocked by system reset. 517 */ 518 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) 519 520 /** @brief Check SYSCFG flag is set or not. 521 * @param __FLAG__ specifies the flag to check. 522 * This parameter can be one of the following values: 523 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 524 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing 525 * @retval The new state of __FLAG__ (TRUE or FALSE). 526 */ 527 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U) 528 529 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 530 */ 531 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) 532 533 /** @brief Fast-mode Plus driving capability enable/disable macros 534 * @param __FASTMODEPLUS__ This parameter can be a value of : 535 * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 536 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 537 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 538 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 539 */ 540 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 541 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 542 }while(0) 543 544 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 545 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 546 }while(0) 547 548 /** 549 * @} 550 */ 551 552 /** 553 * @} 554 */ 555 556 /* Private macros ------------------------------------------------------------*/ 557 /** @defgroup HAL_Private_Macros HAL Private Macros 558 * @{ 559 */ 560 561 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 562 * @{ 563 */ 564 565 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 566 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 567 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 568 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 569 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 570 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) 571 572 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 573 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 574 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ 575 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 576 577 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL)) 578 579 #if defined(VREFBUF) 580 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 581 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) 582 583 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 584 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 585 586 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 587 #endif /* VREFBUF */ 588 589 #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) 590 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 591 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 592 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 593 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 594 #elif defined(SYSCFG_FASTMODEPLUS_PB8) 595 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 596 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 597 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8)) 598 #elif defined(SYSCFG_FASTMODEPLUS_PB9) 599 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 600 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 601 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 602 #else 603 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 604 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7)) 605 #endif 606 /** 607 * @} 608 */ 609 610 /** 611 * @} 612 */ 613 614 /* Exported variables --------------------------------------------------------*/ 615 616 /** @addtogroup HAL_Exported_Variables 617 * @{ 618 */ 619 extern __IO uint32_t uwTick; 620 extern uint32_t uwTickPrio; 621 extern HAL_TickFreqTypeDef uwTickFreq; 622 /** 623 * @} 624 */ 625 626 /* Exported functions --------------------------------------------------------*/ 627 628 /** @addtogroup HAL_Exported_Functions 629 * @{ 630 */ 631 632 /** @addtogroup HAL_Exported_Functions_Group1 633 * @{ 634 */ 635 636 /* Initialization and de-initialization functions ******************************/ 637 HAL_StatusTypeDef HAL_Init(void); 638 HAL_StatusTypeDef HAL_DeInit(void); 639 void HAL_MspInit(void); 640 void HAL_MspDeInit(void); 641 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); 642 643 /** 644 * @} 645 */ 646 647 /** @addtogroup HAL_Exported_Functions_Group2 648 * @{ 649 */ 650 651 /* Peripheral Control functions ************************************************/ 652 void HAL_IncTick(void); 653 void HAL_Delay(uint32_t Delay); 654 uint32_t HAL_GetTick(void); 655 uint32_t HAL_GetTickPrio(void); 656 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 657 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 658 void HAL_SuspendTick(void); 659 void HAL_ResumeTick(void); 660 uint32_t HAL_GetHalVersion(void); 661 uint32_t HAL_GetREVID(void); 662 uint32_t HAL_GetDEVID(void); 663 uint32_t HAL_GetUIDw0(void); 664 uint32_t HAL_GetUIDw1(void); 665 uint32_t HAL_GetUIDw2(void); 666 667 /** 668 * @} 669 */ 670 671 /** @addtogroup HAL_Exported_Functions_Group3 672 * @{ 673 */ 674 675 /* DBGMCU Peripheral Control functions *****************************************/ 676 void HAL_DBGMCU_EnableDBGSleepMode(void); 677 void HAL_DBGMCU_DisableDBGSleepMode(void); 678 void HAL_DBGMCU_EnableDBGStopMode(void); 679 void HAL_DBGMCU_DisableDBGStopMode(void); 680 void HAL_DBGMCU_EnableDBGStandbyMode(void); 681 void HAL_DBGMCU_DisableDBGStandbyMode(void); 682 683 /** 684 * @} 685 */ 686 687 /** @addtogroup HAL_Exported_Functions_Group4 688 * @{ 689 */ 690 691 /* SYSCFG Control functions ****************************************************/ 692 void HAL_SYSCFG_SRAM2Erase(void); 693 void HAL_SYSCFG_EnableMemorySwappingBank(void); 694 void HAL_SYSCFG_DisableMemorySwappingBank(void); 695 696 #if defined(VREFBUF) 697 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 698 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 699 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 700 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 701 void HAL_SYSCFG_DisableVREFBUF(void); 702 #endif /* VREFBUF */ 703 704 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); 705 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); 706 707 /** 708 * @} 709 */ 710 711 /** 712 * @} 713 */ 714 715 /** 716 * @} 717 */ 718 719 /** 720 * @} 721 */ 722 723 #ifdef __cplusplus 724 } 725 #endif 726 727 #endif /* STM32L4xx_HAL_H */ 728 729 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 730