1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_ipcc.h
4 * @author MCD Application Team
5 * @brief Header file of IPCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32WBxx_LL_IPCC_H
22 #define STM32WBxx_LL_IPCC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32wbxx.h"
30
31 /** @addtogroup STM32WBxx_LL_Driver
32 * @{
33 */
34
35 #if defined(IPCC)
36
37 /** @defgroup IPCC_LL IPCC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 /* Exported types ------------------------------------------------------------*/
46 /* Exported constants --------------------------------------------------------*/
47 /** @defgroup IPCC_LL_Exported_Constants IPCC Exported Constants
48 * @{
49 */
50
51 /** @defgroup IPCC_LL_EC_GET_FLAG Get Flags Defines
52 * @brief Flags defines which can be used with LL_IPCC_ReadReg function
53 * @{
54 */
55 #define LL_IPCC_C1TOC2SR_CH1F IPCC_C1TOC2SR_CH1F_Msk /*!< C1 transmit to C2 receive Channel1 status flag before masking */
56 #define LL_IPCC_C1TOC2SR_CH2F IPCC_C1TOC2SR_CH2F_Msk /*!< C1 transmit to C2 receive Channel2 status flag before masking */
57 #define LL_IPCC_C1TOC2SR_CH3F IPCC_C1TOC2SR_CH3F_Msk /*!< C1 transmit to C2 receive Channel3 status flag before masking */
58 #define LL_IPCC_C1TOC2SR_CH4F IPCC_C1TOC2SR_CH4F_Msk /*!< C1 transmit to C2 receive Channel4 status flag before masking */
59 #define LL_IPCC_C1TOC2SR_CH5F IPCC_C1TOC2SR_CH5F_Msk /*!< C1 transmit to C2 receive Channel5 status flag before masking */
60 #define LL_IPCC_C1TOC2SR_CH6F IPCC_C1TOC2SR_CH6F_Msk /*!< C1 transmit to C2 receive Channel6 status flag before masking */
61 #define LL_IPCC_C2TOC1SR_CH1F IPCC_C2TOC1SR_CH1F_Msk /*!< C2 transmit to C1 receive Channel1 status flag before masking */
62 #define LL_IPCC_C2TOC1SR_CH2F IPCC_C2TOC1SR_CH2F_Msk /*!< C2 transmit to C1 receive Channel2 status flag before masking */
63 #define LL_IPCC_C2TOC1SR_CH3F IPCC_C2TOC1SR_CH3F_Msk /*!< C2 transmit to C1 receive Channel3 status flag before masking */
64 #define LL_IPCC_C2TOC1SR_CH4F IPCC_C2TOC1SR_CH4F_Msk /*!< C2 transmit to C1 receive Channel4 status flag before masking */
65 #define LL_IPCC_C2TOC1SR_CH5F IPCC_C2TOC1SR_CH5F_Msk /*!< C2 transmit to C1 receive Channel5 status flag before masking */
66 #define LL_IPCC_C2TOC1SR_CH6F IPCC_C2TOC1SR_CH6F_Msk /*!< C2 transmit to C1 receive Channel6 status flag before masking */
67
68 /**
69 * @}
70 */
71
72 /** @defgroup IPCC_LL_EC_Channel Channel
73 * @{
74 */
75 #define LL_IPCC_CHANNEL_1 (0x00000001U) /*!< IPCC Channel 1 */
76 #define LL_IPCC_CHANNEL_2 (0x00000002U) /*!< IPCC Channel 2 */
77 #define LL_IPCC_CHANNEL_3 (0x00000004U) /*!< IPCC Channel 3 */
78 #define LL_IPCC_CHANNEL_4 (0x00000008U) /*!< IPCC Channel 4 */
79 #define LL_IPCC_CHANNEL_5 (0x00000010U) /*!< IPCC Channel 5 */
80 #define LL_IPCC_CHANNEL_6 (0x00000020U) /*!< IPCC Channel 6 */
81 /**
82 * @}
83 */
84
85 /**
86 * @}
87 */
88
89 /* Exported macro ------------------------------------------------------------*/
90 /** @defgroup IPCC_LL_Exported_Macros IPCC Exported Macros
91 * @{
92 */
93
94 /** @defgroup IPCC_LL_EM_WRITE_READ Common Write and read registers Macros
95 * @{
96 */
97
98 /**
99 * @brief Write a value in IPCC register
100 * @param __INSTANCE__ IPCC Instance
101 * @param __REG__ Register to be written
102 * @param __VALUE__ Value to be written in the register
103 * @retval None
104 */
105 #define LL_IPCC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
106
107 /**
108 * @brief Read a value in IPCC register
109 * @param __INSTANCE__ IPCC Instance
110 * @param __REG__ Register to be read
111 * @retval Register value
112 */
113 #define LL_IPCC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
114 /**
115 * @}
116 */
117
118 /**
119 * @}
120 */
121
122
123 /* Exported functions --------------------------------------------------------*/
124 /** @defgroup IPCC_LL_Exported_Functions IPCC Exported Functions
125 * @{
126 */
127
128 /** @defgroup IPCC_LL_EF_IT_Management IT_Management
129 * @{
130 */
131
132 /**
133 * @brief Enable Transmit channel free interrupt for processor 1.
134 * @rmtoll C1CR TXFIE LL_C1_IPCC_EnableIT_TXF
135 * @param IPCCx IPCC Instance.
136 * @retval None
137 */
LL_C1_IPCC_EnableIT_TXF(IPCC_TypeDef * IPCCx)138 __STATIC_INLINE void LL_C1_IPCC_EnableIT_TXF(IPCC_TypeDef *IPCCx)
139 {
140 SET_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE);
141 }
142
143 /**
144 * @brief Disable Transmit channel free interrupt for processor 1.
145 * @rmtoll C1CR TXFIE LL_C1_IPCC_DisableIT_TXF
146 * @param IPCCx IPCC Instance.
147 * @retval None
148 */
LL_C1_IPCC_DisableIT_TXF(IPCC_TypeDef * IPCCx)149 __STATIC_INLINE void LL_C1_IPCC_DisableIT_TXF(IPCC_TypeDef *IPCCx)
150 {
151 CLEAR_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE);
152 }
153
154 /**
155 * @brief Check if Transmit channel free interrupt for processor 1 is enabled.
156 * @rmtoll C1CR TXFIE LL_C1_IPCC_IsEnabledIT_TXF
157 * @param IPCCx IPCC Instance.
158 * @retval State of bit (1 or 0).
159 */
LL_C1_IPCC_IsEnabledIT_TXF(IPCC_TypeDef const * const IPCCx)160 __STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledIT_TXF(IPCC_TypeDef const *const IPCCx)
161 {
162 return ((READ_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE) == (IPCC_C1CR_TXFIE)) ? 1UL : 0UL);
163 }
164
165 /**
166 * @brief Enable Receive channel occupied interrupt for processor 1.
167 * @rmtoll C1CR RXOIE LL_C1_IPCC_EnableIT_RXO
168 * @param IPCCx IPCC Instance.
169 * @retval None
170 */
LL_C1_IPCC_EnableIT_RXO(IPCC_TypeDef * IPCCx)171 __STATIC_INLINE void LL_C1_IPCC_EnableIT_RXO(IPCC_TypeDef *IPCCx)
172 {
173 SET_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE);
174 }
175
176 /**
177 * @brief Disable Receive channel occupied interrupt for processor 1.
178 * @rmtoll C1CR RXOIE LL_C1_IPCC_DisableIT_RXO
179 * @param IPCCx IPCC Instance.
180 * @retval None
181 */
LL_C1_IPCC_DisableIT_RXO(IPCC_TypeDef * IPCCx)182 __STATIC_INLINE void LL_C1_IPCC_DisableIT_RXO(IPCC_TypeDef *IPCCx)
183 {
184 CLEAR_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE);
185 }
186
187 /**
188 * @brief Check if Receive channel occupied interrupt for processor 1 is enabled.
189 * @rmtoll C1CR RXOIE LL_C1_IPCC_IsEnabledIT_RXO
190 * @param IPCCx IPCC Instance.
191 * @retval State of bit (1 or 0).
192 */
LL_C1_IPCC_IsEnabledIT_RXO(IPCC_TypeDef const * const IPCCx)193 __STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledIT_RXO(IPCC_TypeDef const *const IPCCx)
194 {
195 return ((READ_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE) == (IPCC_C1CR_RXOIE)) ? 1UL : 0UL);
196 }
197
198 /**
199 * @brief Enable Transmit channel free interrupt for processor 2.
200 * @rmtoll C2CR TXFIE LL_C2_IPCC_EnableIT_TXF
201 * @param IPCCx IPCC Instance.
202 * @retval None
203 */
LL_C2_IPCC_EnableIT_TXF(IPCC_TypeDef * IPCCx)204 __STATIC_INLINE void LL_C2_IPCC_EnableIT_TXF(IPCC_TypeDef *IPCCx)
205 {
206 SET_BIT(IPCCx->C2CR, IPCC_C2CR_TXFIE);
207 }
208
209 /**
210 * @brief Disable Transmit channel free interrupt for processor 2.
211 * @rmtoll C2CR TXFIE LL_C2_IPCC_DisableIT_TXF
212 * @param IPCCx IPCC Instance.
213 * @retval None
214 */
LL_C2_IPCC_DisableIT_TXF(IPCC_TypeDef * IPCCx)215 __STATIC_INLINE void LL_C2_IPCC_DisableIT_TXF(IPCC_TypeDef *IPCCx)
216 {
217 CLEAR_BIT(IPCCx->C2CR, IPCC_C2CR_TXFIE);
218 }
219
220 /**
221 * @brief Check if Transmit channel free interrupt for processor 2 is enabled.
222 * @rmtoll C2CR TXFIE LL_C2_IPCC_IsEnabledIT_TXF
223 * @param IPCCx IPCC Instance.
224 * @retval State of bit (1 or 0).
225 */
LL_C2_IPCC_IsEnabledIT_TXF(IPCC_TypeDef const * const IPCCx)226 __STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledIT_TXF(IPCC_TypeDef const *const IPCCx)
227 {
228 return ((READ_BIT(IPCCx->C2CR, IPCC_C2CR_TXFIE) == (IPCC_C2CR_TXFIE)) ? 1UL : 0UL);
229 }
230
231 /**
232 * @brief Enable Receive channel occupied interrupt for processor 2.
233 * @rmtoll C2CR RXOIE LL_C2_IPCC_EnableIT_RXO
234 * @param IPCCx IPCC Instance.
235 * @retval None
236 */
LL_C2_IPCC_EnableIT_RXO(IPCC_TypeDef * IPCCx)237 __STATIC_INLINE void LL_C2_IPCC_EnableIT_RXO(IPCC_TypeDef *IPCCx)
238 {
239 SET_BIT(IPCCx->C2CR, IPCC_C2CR_RXOIE);
240 }
241
242 /**
243 * @brief Disable Receive channel occupied interrupt for processor 2.
244 * @rmtoll C2CR RXOIE LL_C2_IPCC_DisableIT_RXO
245 * @param IPCCx IPCC Instance.
246 * @retval None
247 */
LL_C2_IPCC_DisableIT_RXO(IPCC_TypeDef * IPCCx)248 __STATIC_INLINE void LL_C2_IPCC_DisableIT_RXO(IPCC_TypeDef *IPCCx)
249 {
250 CLEAR_BIT(IPCCx->C2CR, IPCC_C2CR_RXOIE);
251 }
252
253 /**
254 * @brief Check if Receive channel occupied interrupt for processor 2 is enabled.
255 * @rmtoll C2CR RXOIE LL_C2_IPCC_IsEnabledIT_RXO
256 * @param IPCCx IPCC Instance.
257 * @retval State of bit (1 or 0).
258 */
LL_C2_IPCC_IsEnabledIT_RXO(IPCC_TypeDef const * const IPCCx)259 __STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledIT_RXO(IPCC_TypeDef const *const IPCCx)
260 {
261 return ((READ_BIT(IPCCx->C2CR, IPCC_C2CR_RXOIE) == (IPCC_C2CR_RXOIE)) ? 1UL : 0UL);
262 }
263
264 /**
265 * @}
266 */
267
268 /** @defgroup IPCC_LL_EF_Configuration Configuration
269 * @{
270 */
271
272 /**
273 * @brief Unmask transmit channel free interrupt for processor 1.
274 * @rmtoll C1MR CH1FM LL_C1_IPCC_EnableTransmitChannel\n
275 * C1MR CH2FM LL_C1_IPCC_EnableTransmitChannel\n
276 * C1MR CH3FM LL_C1_IPCC_EnableTransmitChannel\n
277 * C1MR CH4FM LL_C1_IPCC_EnableTransmitChannel\n
278 * C1MR CH5FM LL_C1_IPCC_EnableTransmitChannel\n
279 * C1MR CH6FM LL_C1_IPCC_EnableTransmitChannel
280 * @param IPCCx IPCC Instance.
281 * @param Channel This parameter can be a combination of the following values:
282 * @arg @ref LL_IPCC_CHANNEL_1
283 * @arg @ref LL_IPCC_CHANNEL_2
284 * @arg @ref LL_IPCC_CHANNEL_3
285 * @arg @ref LL_IPCC_CHANNEL_4
286 * @arg @ref LL_IPCC_CHANNEL_5
287 * @arg @ref LL_IPCC_CHANNEL_6
288 * @retval None
289 */
LL_C1_IPCC_EnableTransmitChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)290 __STATIC_INLINE void LL_C1_IPCC_EnableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
291 {
292 CLEAR_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos);
293 }
294
295 /**
296 * @brief Mask transmit channel free interrupt for processor 1.
297 * @rmtoll C1MR CH1FM LL_C1_IPCC_DisableTransmitChannel\n
298 * C1MR CH2FM LL_C1_IPCC_DisableTransmitChannel\n
299 * C1MR CH3FM LL_C1_IPCC_DisableTransmitChannel\n
300 * C1MR CH4FM LL_C1_IPCC_DisableTransmitChannel\n
301 * C1MR CH5FM LL_C1_IPCC_DisableTransmitChannel\n
302 * C1MR CH6FM LL_C1_IPCC_DisableTransmitChannel
303 * @param IPCCx IPCC Instance.
304 * @param Channel This parameter can be a combination of the following values:
305 * @arg @ref LL_IPCC_CHANNEL_1
306 * @arg @ref LL_IPCC_CHANNEL_2
307 * @arg @ref LL_IPCC_CHANNEL_3
308 * @arg @ref LL_IPCC_CHANNEL_4
309 * @arg @ref LL_IPCC_CHANNEL_5
310 * @arg @ref LL_IPCC_CHANNEL_6
311 * @retval None
312 */
LL_C1_IPCC_DisableTransmitChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)313 __STATIC_INLINE void LL_C1_IPCC_DisableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
314 {
315 SET_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos);
316 }
317
318 /**
319 * @brief Check if Transmit channel free interrupt for processor 1 is masked.
320 * @rmtoll C1MR CH1FM LL_C1_IPCC_IsEnabledTransmitChannel\n
321 * C1MR CH2FM LL_C1_IPCC_IsEnabledTransmitChannel\n
322 * C1MR CH3FM LL_C1_IPCC_IsEnabledTransmitChannel\n
323 * C1MR CH4FM LL_C1_IPCC_IsEnabledTransmitChannel\n
324 * C1MR CH5FM LL_C1_IPCC_IsEnabledTransmitChannel\n
325 * C1MR CH6FM LL_C1_IPCC_IsEnabledTransmitChannel
326 * @param IPCCx IPCC Instance.
327 * @param Channel This parameter can be one of the following values:
328 * @arg @ref LL_IPCC_CHANNEL_1
329 * @arg @ref LL_IPCC_CHANNEL_2
330 * @arg @ref LL_IPCC_CHANNEL_3
331 * @arg @ref LL_IPCC_CHANNEL_4
332 * @arg @ref LL_IPCC_CHANNEL_5
333 * @arg @ref LL_IPCC_CHANNEL_6
334 * @retval State of bit (1 or 0).
335 */
LL_C1_IPCC_IsEnabledTransmitChannel(IPCC_TypeDef const * const IPCCx,uint32_t Channel)336 __STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledTransmitChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
337 {
338 return ((READ_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos) != (Channel << IPCC_C1MR_CH1FM_Pos)) ? 1UL : 0UL);
339 }
340
341 /**
342 * @brief Unmask receive channel occupied interrupt for processor 1.
343 * @rmtoll C1MR CH1OM LL_C1_IPCC_EnableReceiveChannel\n
344 * C1MR CH2OM LL_C1_IPCC_EnableReceiveChannel\n
345 * C1MR CH3OM LL_C1_IPCC_EnableReceiveChannel\n
346 * C1MR CH4OM LL_C1_IPCC_EnableReceiveChannel\n
347 * C1MR CH5OM LL_C1_IPCC_EnableReceiveChannel\n
348 * C1MR CH6OM LL_C1_IPCC_EnableReceiveChannel
349 * @param IPCCx IPCC Instance.
350 * @param Channel This parameter can be a combination of the following values:
351 * @arg @ref LL_IPCC_CHANNEL_1
352 * @arg @ref LL_IPCC_CHANNEL_2
353 * @arg @ref LL_IPCC_CHANNEL_3
354 * @arg @ref LL_IPCC_CHANNEL_4
355 * @arg @ref LL_IPCC_CHANNEL_5
356 * @arg @ref LL_IPCC_CHANNEL_6
357 * @retval None
358 */
LL_C1_IPCC_EnableReceiveChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)359 __STATIC_INLINE void LL_C1_IPCC_EnableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
360 {
361 CLEAR_BIT(IPCCx->C1MR, Channel);
362 }
363
364 /**
365 * @brief Mask receive channel occupied interrupt for processor 1.
366 * @rmtoll C1MR CH1OM LL_C1_IPCC_DisableReceiveChannel\n
367 * C1MR CH2OM LL_C1_IPCC_DisableReceiveChannel\n
368 * C1MR CH3OM LL_C1_IPCC_DisableReceiveChannel\n
369 * C1MR CH4OM LL_C1_IPCC_DisableReceiveChannel\n
370 * C1MR CH5OM LL_C1_IPCC_DisableReceiveChannel\n
371 * C1MR CH6OM LL_C1_IPCC_DisableReceiveChannel
372 * @param IPCCx IPCC Instance.
373 * @param Channel This parameter can be a combination of the following values:
374 * @arg @ref LL_IPCC_CHANNEL_1
375 * @arg @ref LL_IPCC_CHANNEL_2
376 * @arg @ref LL_IPCC_CHANNEL_3
377 * @arg @ref LL_IPCC_CHANNEL_4
378 * @arg @ref LL_IPCC_CHANNEL_5
379 * @arg @ref LL_IPCC_CHANNEL_6
380 * @retval None
381 */
LL_C1_IPCC_DisableReceiveChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)382 __STATIC_INLINE void LL_C1_IPCC_DisableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
383 {
384 SET_BIT(IPCCx->C1MR, Channel);
385 }
386
387 /**
388 * @brief Check if Receive channel occupied interrupt for processor 1 is masked.
389 * @rmtoll C1MR CH1OM LL_C1_IPCC_IsEnabledReceiveChannel\n
390 * C1MR CH2OM LL_C1_IPCC_IsEnabledReceiveChannel\n
391 * C1MR CH3OM LL_C1_IPCC_IsEnabledReceiveChannel\n
392 * C1MR CH4OM LL_C1_IPCC_IsEnabledReceiveChannel\n
393 * C1MR CH5OM LL_C1_IPCC_IsEnabledReceiveChannel\n
394 * C1MR CH6OM LL_C1_IPCC_IsEnabledReceiveChannel
395 * @param IPCCx IPCC Instance.
396 * @param Channel This parameter can be one of the following values:
397 * @arg @ref LL_IPCC_CHANNEL_1
398 * @arg @ref LL_IPCC_CHANNEL_2
399 * @arg @ref LL_IPCC_CHANNEL_3
400 * @arg @ref LL_IPCC_CHANNEL_4
401 * @arg @ref LL_IPCC_CHANNEL_5
402 * @arg @ref LL_IPCC_CHANNEL_6
403 * @retval State of bit (1 or 0).
404 */
LL_C1_IPCC_IsEnabledReceiveChannel(IPCC_TypeDef const * const IPCCx,uint32_t Channel)405 __STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledReceiveChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
406 {
407 return ((READ_BIT(IPCCx->C1MR, Channel) != (Channel)) ? 1UL : 0UL);
408 }
409
410 /**
411 * @brief Unmask transmit channel free interrupt for processor 2.
412 * @rmtoll C2MR CH1FM LL_C2_IPCC_EnableTransmitChannel\n
413 * C2MR CH2FM LL_C2_IPCC_EnableTransmitChannel\n
414 * C2MR CH3FM LL_C2_IPCC_EnableTransmitChannel\n
415 * C2MR CH4FM LL_C2_IPCC_EnableTransmitChannel\n
416 * C2MR CH5FM LL_C2_IPCC_EnableTransmitChannel\n
417 * C2MR CH6FM LL_C2_IPCC_EnableTransmitChannel
418 * @param IPCCx IPCC Instance.
419 * @param Channel This parameter can be a combination of the following values:
420 * @arg @ref LL_IPCC_CHANNEL_1
421 * @arg @ref LL_IPCC_CHANNEL_2
422 * @arg @ref LL_IPCC_CHANNEL_3
423 * @arg @ref LL_IPCC_CHANNEL_4
424 * @arg @ref LL_IPCC_CHANNEL_5
425 * @arg @ref LL_IPCC_CHANNEL_6
426 * @retval None
427 */
LL_C2_IPCC_EnableTransmitChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)428 __STATIC_INLINE void LL_C2_IPCC_EnableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
429 {
430 CLEAR_BIT(IPCCx->C2MR, Channel << IPCC_C2MR_CH1FM_Pos);
431 }
432
433 /**
434 * @brief Mask transmit channel free interrupt for processor 2.
435 * @rmtoll C2MR CH1FM LL_C2_IPCC_DisableTransmitChannel\n
436 * C2MR CH2FM LL_C2_IPCC_DisableTransmitChannel\n
437 * C2MR CH3FM LL_C2_IPCC_DisableTransmitChannel\n
438 * C2MR CH4FM LL_C2_IPCC_DisableTransmitChannel\n
439 * C2MR CH5FM LL_C2_IPCC_DisableTransmitChannel\n
440 * C2MR CH6FM LL_C2_IPCC_DisableTransmitChannel
441 * @param IPCCx IPCC Instance.
442 * @param Channel This parameter can be a combination of the following values:
443 * @arg @ref LL_IPCC_CHANNEL_1
444 * @arg @ref LL_IPCC_CHANNEL_2
445 * @arg @ref LL_IPCC_CHANNEL_3
446 * @arg @ref LL_IPCC_CHANNEL_4
447 * @arg @ref LL_IPCC_CHANNEL_5
448 * @arg @ref LL_IPCC_CHANNEL_6
449 * @retval None
450 */
LL_C2_IPCC_DisableTransmitChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)451 __STATIC_INLINE void LL_C2_IPCC_DisableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
452 {
453 SET_BIT(IPCCx->C2MR, Channel << (IPCC_C2MR_CH1FM_Pos));
454 }
455
456 /**
457 * @brief Check if Transmit channel free interrupt for processor 2 is masked.
458 * @rmtoll C2MR CH1FM LL_C2_IPCC_IsEnabledTransmitChannel\n
459 * C2MR CH2FM LL_C2_IPCC_IsEnabledTransmitChannel\n
460 * C2MR CH3FM LL_C2_IPCC_IsEnabledTransmitChannel\n
461 * C2MR CH4FM LL_C2_IPCC_IsEnabledTransmitChannel\n
462 * C2MR CH5FM LL_C2_IPCC_IsEnabledTransmitChannel\n
463 * C2MR CH6FM LL_C2_IPCC_IsEnabledTransmitChannel
464 * @param IPCCx IPCC Instance.
465 * @param Channel This parameter can be one of the following values:
466 * @arg @ref LL_IPCC_CHANNEL_1
467 * @arg @ref LL_IPCC_CHANNEL_2
468 * @arg @ref LL_IPCC_CHANNEL_3
469 * @arg @ref LL_IPCC_CHANNEL_4
470 * @arg @ref LL_IPCC_CHANNEL_5
471 * @arg @ref LL_IPCC_CHANNEL_6
472 * @retval State of bit (1 or 0).
473 */
LL_C2_IPCC_IsEnabledTransmitChannel(IPCC_TypeDef const * const IPCCx,uint32_t Channel)474 __STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledTransmitChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
475 {
476 return ((READ_BIT(IPCCx->C2MR, Channel << IPCC_C2MR_CH1FM_Pos) != (Channel << IPCC_C2MR_CH1FM_Pos)) ? 1UL : 0UL);
477 }
478
479 /**
480 * @brief Unmask receive channel occupied interrupt for processor 2.
481 * @rmtoll C2MR CH1OM LL_C2_IPCC_EnableReceiveChannel\n
482 * C2MR CH2OM LL_C2_IPCC_EnableReceiveChannel\n
483 * C2MR CH3OM LL_C2_IPCC_EnableReceiveChannel\n
484 * C2MR CH4OM LL_C2_IPCC_EnableReceiveChannel\n
485 * C2MR CH5OM LL_C2_IPCC_EnableReceiveChannel\n
486 * C2MR CH6OM LL_C2_IPCC_EnableReceiveChannel
487 * @param IPCCx IPCC Instance.
488 * @param Channel This parameter can be a combination of the following values:
489 * @arg @ref LL_IPCC_CHANNEL_1
490 * @arg @ref LL_IPCC_CHANNEL_2
491 * @arg @ref LL_IPCC_CHANNEL_3
492 * @arg @ref LL_IPCC_CHANNEL_4
493 * @arg @ref LL_IPCC_CHANNEL_5
494 * @arg @ref LL_IPCC_CHANNEL_6
495 * @retval None
496 */
LL_C2_IPCC_EnableReceiveChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)497 __STATIC_INLINE void LL_C2_IPCC_EnableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
498 {
499 CLEAR_BIT(IPCCx->C2MR, Channel);
500 }
501
502 /**
503 * @brief Mask receive channel occupied interrupt for processor 1.
504 * @rmtoll C2MR CH1OM LL_C2_IPCC_DisableReceiveChannel\n
505 * C2MR CH2OM LL_C2_IPCC_DisableReceiveChannel\n
506 * C2MR CH3OM LL_C2_IPCC_DisableReceiveChannel\n
507 * C2MR CH4OM LL_C2_IPCC_DisableReceiveChannel\n
508 * C2MR CH5OM LL_C2_IPCC_DisableReceiveChannel\n
509 * C2MR CH6OM LL_C2_IPCC_DisableReceiveChannel
510 * @param IPCCx IPCC Instance.
511 * @param Channel This parameter can be a combination of the following values:
512 * @arg @ref LL_IPCC_CHANNEL_1
513 * @arg @ref LL_IPCC_CHANNEL_2
514 * @arg @ref LL_IPCC_CHANNEL_3
515 * @arg @ref LL_IPCC_CHANNEL_4
516 * @arg @ref LL_IPCC_CHANNEL_5
517 * @arg @ref LL_IPCC_CHANNEL_6
518 * @retval None
519 */
LL_C2_IPCC_DisableReceiveChannel(IPCC_TypeDef * IPCCx,uint32_t Channel)520 __STATIC_INLINE void LL_C2_IPCC_DisableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
521 {
522 SET_BIT(IPCCx->C2MR, Channel);
523 }
524
525 /**
526 * @brief Check if Receive channel occupied interrupt for processor 2 is masked.
527 * @rmtoll C2MR CH1OM LL_C2_IPCC_IsEnabledReceiveChannel\n
528 * C2MR CH2OM LL_C2_IPCC_IsEnabledReceiveChannel\n
529 * C2MR CH3OM LL_C2_IPCC_IsEnabledReceiveChannel\n
530 * C2MR CH4OM LL_C2_IPCC_IsEnabledReceiveChannel\n
531 * C2MR CH5OM LL_C2_IPCC_IsEnabledReceiveChannel\n
532 * C2MR CH6OM LL_C2_IPCC_IsEnabledReceiveChannel
533 * @param IPCCx IPCC Instance.
534 * @param Channel This parameter can be one of the following values:
535 * @arg @ref LL_IPCC_CHANNEL_1
536 * @arg @ref LL_IPCC_CHANNEL_2
537 * @arg @ref LL_IPCC_CHANNEL_3
538 * @arg @ref LL_IPCC_CHANNEL_4
539 * @arg @ref LL_IPCC_CHANNEL_5
540 * @arg @ref LL_IPCC_CHANNEL_6
541 * @retval State of bit (1 or 0).
542 */
LL_C2_IPCC_IsEnabledReceiveChannel(IPCC_TypeDef const * const IPCCx,uint32_t Channel)543 __STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledReceiveChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
544 {
545 return ((READ_BIT(IPCCx->C2MR, Channel) != (Channel)) ? 1UL : 0UL);
546 }
547
548 /**
549 * @}
550 */
551
552 /** @defgroup IPCC_LL_EF_FLAG_Management FLAG_Management
553 * @{
554 */
555
556 /**
557 * @brief Clear IPCC receive channel status for processor 1.
558 * @note Associated with IPCC_C2TOC1SR.CHxF
559 * @rmtoll C1SCR CH1C LL_C1_IPCC_ClearFlag_CHx\n
560 * C1SCR CH2C LL_C1_IPCC_ClearFlag_CHx\n
561 * C1SCR CH3C LL_C1_IPCC_ClearFlag_CHx\n
562 * C1SCR CH4C LL_C1_IPCC_ClearFlag_CHx\n
563 * C1SCR CH5C LL_C1_IPCC_ClearFlag_CHx\n
564 * C1SCR CH6C LL_C1_IPCC_ClearFlag_CHx
565 * @param IPCCx IPCC Instance.
566 * @param Channel This parameter can be a combination of the following values:
567 * @arg @ref LL_IPCC_CHANNEL_1
568 * @arg @ref LL_IPCC_CHANNEL_2
569 * @arg @ref LL_IPCC_CHANNEL_3
570 * @arg @ref LL_IPCC_CHANNEL_4
571 * @arg @ref LL_IPCC_CHANNEL_5
572 * @arg @ref LL_IPCC_CHANNEL_6
573 * @retval None
574 */
LL_C1_IPCC_ClearFlag_CHx(IPCC_TypeDef * IPCCx,uint32_t Channel)575 __STATIC_INLINE void LL_C1_IPCC_ClearFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
576 {
577 WRITE_REG(IPCCx->C1SCR, Channel);
578 }
579
580 /**
581 * @brief Set IPCC transmit channel status for processor 1.
582 * @note Associated with IPCC_C1TOC2SR.CHxF
583 * @rmtoll C1SCR CH1S LL_C1_IPCC_SetFlag_CHx\n
584 * C1SCR CH2S LL_C1_IPCC_SetFlag_CHx\n
585 * C1SCR CH3S LL_C1_IPCC_SetFlag_CHx\n
586 * C1SCR CH4S LL_C1_IPCC_SetFlag_CHx\n
587 * C1SCR CH5S LL_C1_IPCC_SetFlag_CHx\n
588 * C1SCR CH6S LL_C1_IPCC_SetFlag_CHx
589 * @param IPCCx IPCC Instance.
590 * @param Channel This parameter can be a combination of the following values:
591 * @arg @ref LL_IPCC_CHANNEL_1
592 * @arg @ref LL_IPCC_CHANNEL_2
593 * @arg @ref LL_IPCC_CHANNEL_3
594 * @arg @ref LL_IPCC_CHANNEL_4
595 * @arg @ref LL_IPCC_CHANNEL_5
596 * @arg @ref LL_IPCC_CHANNEL_6
597 * @retval None
598 */
LL_C1_IPCC_SetFlag_CHx(IPCC_TypeDef * IPCCx,uint32_t Channel)599 __STATIC_INLINE void LL_C1_IPCC_SetFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
600 {
601 WRITE_REG(IPCCx->C1SCR, Channel << IPCC_C1SCR_CH1S_Pos);
602 }
603
604 /**
605 * @brief Get channel status for processor 1.
606 * @rmtoll C1TOC2SR CH1F LL_C1_IPCC_IsActiveFlag_CHx\n
607 * C1TOC2SR CH2F LL_C1_IPCC_IsActiveFlag_CHx\n
608 * C1TOC2SR CH3F LL_C1_IPCC_IsActiveFlag_CHx\n
609 * C1TOC2SR CH4F LL_C1_IPCC_IsActiveFlag_CHx\n
610 * C1TOC2SR CH5F LL_C1_IPCC_IsActiveFlag_CHx\n
611 * C1TOC2SR CH6F LL_C1_IPCC_IsActiveFlag_CHx
612 * @param IPCCx IPCC Instance.
613 * @param Channel This parameter can be one of the following values:
614 * @arg @ref LL_IPCC_CHANNEL_1
615 * @arg @ref LL_IPCC_CHANNEL_2
616 * @arg @ref LL_IPCC_CHANNEL_3
617 * @arg @ref LL_IPCC_CHANNEL_4
618 * @arg @ref LL_IPCC_CHANNEL_5
619 * @arg @ref LL_IPCC_CHANNEL_6
620 * @retval State of bit (1 or 0).
621 */
LL_C1_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const * const IPCCx,uint32_t Channel)622 __STATIC_INLINE uint32_t LL_C1_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
623 {
624 return ((READ_BIT(IPCCx->C1TOC2SR, Channel) == (Channel)) ? 1UL : 0UL);
625 }
626
627 /**
628 * @brief Clear IPCC receive channel status for processor 2.
629 * @note Associated with IPCC_C1TOC2SR.CHxF
630 * @rmtoll C2SCR CH1C LL_C2_IPCC_ClearFlag_CHx\n
631 * C2SCR CH2C LL_C2_IPCC_ClearFlag_CHx\n
632 * C2SCR CH3C LL_C2_IPCC_ClearFlag_CHx\n
633 * C2SCR CH4C LL_C2_IPCC_ClearFlag_CHx\n
634 * C2SCR CH5C LL_C2_IPCC_ClearFlag_CHx\n
635 * C2SCR CH6C LL_C2_IPCC_ClearFlag_CHx
636 * @param IPCCx IPCC Instance.
637 * @param Channel This parameter can be a combination of the following values:
638 * @arg @ref LL_IPCC_CHANNEL_1
639 * @arg @ref LL_IPCC_CHANNEL_2
640 * @arg @ref LL_IPCC_CHANNEL_3
641 * @arg @ref LL_IPCC_CHANNEL_4
642 * @arg @ref LL_IPCC_CHANNEL_5
643 * @arg @ref LL_IPCC_CHANNEL_6
644 * @retval None
645 */
LL_C2_IPCC_ClearFlag_CHx(IPCC_TypeDef * IPCCx,uint32_t Channel)646 __STATIC_INLINE void LL_C2_IPCC_ClearFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
647 {
648 WRITE_REG(IPCCx->C2SCR, Channel);
649 }
650
651 /**
652 * @brief Set IPCC transmit channel status for processor 2.
653 * @note Associated with IPCC_C2TOC1SR.CHxF
654 * @rmtoll C2SCR CH1S LL_C2_IPCC_SetFlag_CHx\n
655 * C2SCR CH2S LL_C2_IPCC_SetFlag_CHx\n
656 * C2SCR CH3S LL_C2_IPCC_SetFlag_CHx\n
657 * C2SCR CH4S LL_C2_IPCC_SetFlag_CHx\n
658 * C2SCR CH5S LL_C2_IPCC_SetFlag_CHx\n
659 * C2SCR CH6S LL_C2_IPCC_SetFlag_CHx
660 * @param IPCCx IPCC Instance.
661 * @param Channel This parameter can be a combination of the following values:
662 * @arg @ref LL_IPCC_CHANNEL_1
663 * @arg @ref LL_IPCC_CHANNEL_2
664 * @arg @ref LL_IPCC_CHANNEL_3
665 * @arg @ref LL_IPCC_CHANNEL_4
666 * @arg @ref LL_IPCC_CHANNEL_5
667 * @arg @ref LL_IPCC_CHANNEL_6
668 * @retval None
669 */
LL_C2_IPCC_SetFlag_CHx(IPCC_TypeDef * IPCCx,uint32_t Channel)670 __STATIC_INLINE void LL_C2_IPCC_SetFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
671 {
672 WRITE_REG(IPCCx->C2SCR, Channel << IPCC_C2SCR_CH1S_Pos);
673 }
674
675 /**
676 * @brief Get channel status for processor 2.
677 * @rmtoll C2TOC1SR CH1F LL_C2_IPCC_IsActiveFlag_CHx\n
678 * C2TOC1SR CH2F LL_C2_IPCC_IsActiveFlag_CHx\n
679 * C2TOC1SR CH3F LL_C2_IPCC_IsActiveFlag_CHx\n
680 * C2TOC1SR CH4F LL_C2_IPCC_IsActiveFlag_CHx\n
681 * C2TOC1SR CH5F LL_C2_IPCC_IsActiveFlag_CHx\n
682 * C2TOC1SR CH6F LL_C2_IPCC_IsActiveFlag_CHx
683 * @param IPCCx IPCC Instance.
684 * @param Channel This parameter can be one of the following values:
685 * @arg @ref LL_IPCC_CHANNEL_1
686 * @arg @ref LL_IPCC_CHANNEL_2
687 * @arg @ref LL_IPCC_CHANNEL_3
688 * @arg @ref LL_IPCC_CHANNEL_4
689 * @arg @ref LL_IPCC_CHANNEL_5
690 * @arg @ref LL_IPCC_CHANNEL_6
691 * @retval State of bit (1 or 0).
692 */
LL_C2_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const * const IPCCx,uint32_t Channel)693 __STATIC_INLINE uint32_t LL_C2_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
694 {
695 return ((READ_BIT(IPCCx->C2TOC1SR, Channel) == (Channel)) ? 1UL : 0UL);
696 }
697
698 /**
699 * @}
700 */
701
702
703 /**
704 * @}
705 */
706
707 /**
708 * @}
709 */
710
711 #endif /* defined(IPCC) */
712
713 /**
714 * @}
715 */
716
717 #ifdef __cplusplus
718 }
719 #endif
720
721 #endif /* STM32WBxx_LL_IPCC_H */
722
723 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
724