1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <[email protected]> for STMicroelectronics. 5 */ 6#include <dt-bindings/clock/st,stm32mp25-rcc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/reset/st,stm32mp25-rcc.h> 9#include <dt-bindings/regulator/st,stm32mp25-regulator.h> 10#include <dt-bindings/phy/phy.h> 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "arm,cortex-a35"; 22 device_type = "cpu"; 23 reg = <0>; 24 enable-method = "psci"; 25 power-domains = <&CPU_PD0>; 26 power-domain-names = "psci"; 27 }; 28 }; 29 30 arm-pmu { 31 compatible = "arm,cortex-a35-pmu"; 32 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 33 interrupt-affinity = <&cpu0>; 34 interrupt-parent = <&intc>; 35 }; 36 37 arm_wdt: watchdog { 38 compatible = "arm,smc-wdt"; 39 arm,smc-id = <0xb200005a>; 40 status = "disabled"; 41 }; 42 43 clocks { 44 clk_dsi_txbyte: txbyteclk { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <0>; 48 }; 49 50 clk_rcbsec: clk-rcbsec { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <64000000>; 54 }; 55 }; 56 57 firmware { 58 optee: optee { 59 compatible = "linaro,optee-tz"; 60 method = "smc"; 61 interrupt-parent = <&intc>; 62 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 63 }; 64 65 scmi { 66 compatible = "linaro,scmi-optee"; 67 #address-cells = <1>; 68 #size-cells = <0>; 69 linaro,optee-channel-id = <0>; 70 71 scmi_clk: protocol@14 { 72 reg = <0x14>; 73 #clock-cells = <1>; 74 }; 75 76 scmi_reset: protocol@16 { 77 reg = <0x16>; 78 #reset-cells = <1>; 79 }; 80 81 scmi_voltd: protocol@17 { 82 reg = <0x17>; 83 84 scmi_regu: regulators { 85 #address-cells = <1>; 86 #size-cells = <0>; 87 88 scmi_vddio1: regulator@0 { 89 reg = <VOLTD_SCMI_VDDIO1>; 90 regulator-name = "vddio1"; 91 }; 92 scmi_vddio2: regulator@1 { 93 reg = <VOLTD_SCMI_VDDIO2>; 94 regulator-name = "vddio2"; 95 }; 96 scmi_vddio3: regulator@2 { 97 reg = <VOLTD_SCMI_VDDIO3>; 98 regulator-name = "vddio3"; 99 }; 100 scmi_vddio4: regulator@3 { 101 reg = <VOLTD_SCMI_VDDIO4>; 102 regulator-name = "vddio4"; 103 }; 104 scmi_vdd33ucpd: regulator@5 { 105 reg = <VOLTD_SCMI_UCPD>; 106 regulator-name = "vdd33ucpd"; 107 }; 108 scmi_vdda18adc: regulator@7 { 109 reg = <VOLTD_SCMI_ADC>; 110 regulator-name = "vdda18adc"; 111 }; 112 }; 113 }; 114 }; 115 }; 116 117 intc: interrupt-controller@4ac00000 { 118 compatible = "arm,cortex-a7-gic"; 119 #interrupt-cells = <3>; 120 #address-cells = <1>; 121 interrupt-controller; 122 reg = <0x0 0x4ac10000 0x0 0x1000>, 123 <0x0 0x4ac20000 0x0 0x2000>, 124 <0x0 0x4ac40000 0x0 0x2000>, 125 <0x0 0x4ac60000 0x0 0x2000>; 126 }; 127 128 psci { 129 compatible = "arm,psci-1.0"; 130 method = "smc"; 131 132 CPU_PD0: power-domain-cpu0 { 133 #power-domain-cells = <0>; 134 power-domains = <&CLUSTER_PD>; 135 }; 136 137 CLUSTER_PD: power-domain-cluster { 138 #power-domain-cells = <0>; 139 power-domains = <&RET_PD>; 140 }; 141 142 RET_PD: power-domain-retention { 143 #power-domain-cells = <0>; 144 }; 145 }; 146 147 timer { 148 compatible = "arm,armv8-timer"; 149 interrupt-parent = <&intc>; 150 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 152 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 153 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 154 always-on; 155 }; 156 157 soc@0 { 158 compatible = "simple-bus"; 159 #address-cells = <1>; 160 #size-cells = <1>; 161 interrupt-parent = <&intc>; 162 ranges = <0x0 0x0 0x0 0x80000000>; 163 164 hpdma: dma-controller@40400000 { 165 compatible = "st,stm32mp25-dma3"; 166 reg = <0x40400000 0x1000>; 167 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&scmi_clk CK_SCMI_HPDMA1>; 184 #dma-cells = <3>; 185 }; 186 187 hpdma2: dma-controller@40410000 { 188 compatible = "st,stm32mp25-dma3"; 189 reg = <0x40410000 0x1000>; 190 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&scmi_clk CK_SCMI_HPDMA2>; 207 #dma-cells = <3>; 208 }; 209 210 hpdma3: dma-controller@40420000 { 211 compatible = "st,stm32mp25-dma3"; 212 reg = <0x40420000 0x1000>; 213 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&scmi_clk CK_SCMI_HPDMA3>; 230 #dma-cells = <3>; 231 }; 232 233 rifsc: bus@42080000 { 234 compatible = "st,stm32mp25-rifsc", "simple-bus"; 235 reg = <0x42080000 0x1000>; 236 #address-cells = <1>; 237 #size-cells = <1>; 238 #access-controller-cells = <1>; 239 ranges; 240 241 i2s2: audio-controller@400b0000 { 242 compatible = "st,stm32mp25-i2s"; 243 reg = <0x400b0000 0x400>; 244 #sound-dai-cells = <0>; 245 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>; 247 clock-names = "pclk", "i2sclk"; 248 resets = <&rcc SPI2_R>; 249 dmas = <&hpdma 51 0x43 0x12>, 250 <&hpdma 52 0x43 0x21>; 251 dma-names = "rx", "tx"; 252 access-controllers = <&rifsc 23>; 253 status = "disabled"; 254 }; 255 256 spi2: spi@400b0000 { 257 #address-cells = <1>; 258 #size-cells = <0>; 259 compatible = "st,stm32mp25-spi"; 260 reg = <0x400b0000 0x400>; 261 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&rcc CK_KER_SPI2>; 263 resets = <&rcc SPI2_R>; 264 dmas = <&hpdma 51 0x20 0x3012>, 265 <&hpdma 52 0x20 0x3021>; 266 dma-names = "rx", "tx"; 267 access-controllers = <&rifsc 23>; 268 status = "disabled"; 269 }; 270 271 i2s3: audio-controller@400c0000 { 272 compatible = "st,stm32mp25-i2s"; 273 reg = <0x400c0000 0x400>; 274 #sound-dai-cells = <0>; 275 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>; 277 clock-names = "pclk", "i2sclk"; 278 resets = <&rcc SPI3_R>; 279 dmas = <&hpdma 53 0x43 0x12>, 280 <&hpdma 54 0x43 0x21>; 281 dma-names = "rx", "tx"; 282 access-controllers = <&rifsc 24>; 283 status = "disabled"; 284 }; 285 286 spi3: spi@400c0000 { 287 #address-cells = <1>; 288 #size-cells = <0>; 289 compatible = "st,stm32mp25-spi"; 290 reg = <0x400c0000 0x400>; 291 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&rcc CK_KER_SPI3>; 293 resets = <&rcc SPI3_R>; 294 dmas = <&hpdma 53 0x20 0x3012>, 295 <&hpdma 54 0x20 0x3021>; 296 dma-names = "rx", "tx"; 297 access-controllers = <&rifsc 24>; 298 status = "disabled"; 299 }; 300 301 spdifrx: audio-controller@400d0000 { 302 compatible = "st,stm32h7-spdifrx"; 303 #sound-dai-cells = <0>; 304 reg = <0x400d0000 0x400>; 305 clocks = <&rcc CK_KER_SPDIFRX>; 306 clock-names = "kclk"; 307 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 308 dmas = <&hpdma 71 0x43 0x212>, 309 <&hpdma 72 0x43 0x212>; 310 dma-names = "rx", "rx-ctrl"; 311 access-controllers = <&rifsc 30>; 312 status = "disabled"; 313 }; 314 315 usart2: serial@400e0000 { 316 compatible = "st,stm32h7-uart"; 317 reg = <0x400e0000 0x400>; 318 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&rcc CK_KER_USART2>; 320 dmas = <&hpdma 11 0x20 0x10012>, 321 <&hpdma 12 0x20 0x3021>; 322 dma-names = "rx", "tx"; 323 access-controllers = <&rifsc 32>; 324 status = "disabled"; 325 }; 326 327 usart3: serial@400f0000 { 328 compatible = "st,stm32h7-uart"; 329 reg = <0x400f0000 0x400>; 330 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&rcc CK_KER_USART3>; 332 dmas = <&hpdma 13 0x20 0x10012>, 333 <&hpdma 14 0x20 0x3021>; 334 dma-names = "rx", "tx"; 335 access-controllers = <&rifsc 33>; 336 status = "disabled"; 337 }; 338 339 uart4: serial@40100000 { 340 compatible = "st,stm32h7-uart"; 341 reg = <0x40100000 0x400>; 342 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&rcc CK_KER_UART4>; 344 dmas = <&hpdma 15 0x20 0x10012>, 345 <&hpdma 16 0x20 0x3021>; 346 dma-names = "rx", "tx"; 347 access-controllers = <&rifsc 34>; 348 status = "disabled"; 349 }; 350 351 uart5: serial@40110000 { 352 compatible = "st,stm32h7-uart"; 353 reg = <0x40110000 0x400>; 354 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&rcc CK_KER_UART5>; 356 dmas = <&hpdma 17 0x20 0x10012>, 357 <&hpdma 18 0x20 0x3021>; 358 dma-names = "rx", "tx"; 359 access-controllers = <&rifsc 35>; 360 status = "disabled"; 361 }; 362 363 i2c1: i2c@40120000 { 364 compatible = "st,stm32mp25-i2c"; 365 reg = <0x40120000 0x400>; 366 interrupt-names = "event"; 367 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&rcc CK_KER_I2C1>; 369 resets = <&rcc I2C1_R>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 dmas = <&hpdma 27 0x20 0x3012>, 373 <&hpdma 28 0x20 0x3021>; 374 dma-names = "rx", "tx"; 375 access-controllers = <&rifsc 41>; 376 status = "disabled"; 377 }; 378 379 i2c2: i2c@40130000 { 380 compatible = "st,stm32mp25-i2c"; 381 reg = <0x40130000 0x400>; 382 interrupt-names = "event"; 383 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&rcc CK_KER_I2C2>; 385 resets = <&rcc I2C2_R>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 dmas = <&hpdma 30 0x20 0x3012>, 389 <&hpdma 31 0x20 0x3021>; 390 dma-names = "rx", "tx"; 391 access-controllers = <&rifsc 42>; 392 status = "disabled"; 393 }; 394 395 i2c3: i2c@40140000 { 396 compatible = "st,stm32mp25-i2c"; 397 reg = <0x40140000 0x400>; 398 interrupt-names = "event"; 399 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&rcc CK_KER_I2C3>; 401 resets = <&rcc I2C3_R>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 dmas = <&hpdma 33 0x20 0x3012>, 405 <&hpdma 34 0x20 0x3021>; 406 dma-names = "rx", "tx"; 407 access-controllers = <&rifsc 43>; 408 status = "disabled"; 409 }; 410 411 i2c4: i2c@40150000 { 412 compatible = "st,stm32mp25-i2c"; 413 reg = <0x40150000 0x400>; 414 interrupt-names = "event"; 415 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&rcc CK_KER_I2C4>; 417 resets = <&rcc I2C4_R>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 dmas = <&hpdma 36 0x20 0x3012>, 421 <&hpdma 37 0x20 0x3021>; 422 dma-names = "rx", "tx"; 423 access-controllers = <&rifsc 44>; 424 status = "disabled"; 425 }; 426 427 i2c5: i2c@40160000 { 428 compatible = "st,stm32mp25-i2c"; 429 reg = <0x40160000 0x400>; 430 interrupt-names = "event"; 431 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&rcc CK_KER_I2C5>; 433 resets = <&rcc I2C5_R>; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 dmas = <&hpdma 39 0x20 0x3012>, 437 <&hpdma 40 0x20 0x3021>; 438 dma-names = "rx", "tx"; 439 access-controllers = <&rifsc 45>; 440 status = "disabled"; 441 }; 442 443 i2c6: i2c@40170000 { 444 compatible = "st,stm32mp25-i2c"; 445 reg = <0x40170000 0x400>; 446 interrupt-names = "event"; 447 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&rcc CK_KER_I2C6>; 449 resets = <&rcc I2C6_R>; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 dmas = <&hpdma 42 0x20 0x3012>, 453 <&hpdma 43 0x20 0x3021>; 454 dma-names = "rx", "tx"; 455 access-controllers = <&rifsc 46>; 456 status = "disabled"; 457 }; 458 459 i2c7: i2c@40180000 { 460 compatible = "st,stm32mp25-i2c"; 461 reg = <0x40180000 0x400>; 462 interrupt-names = "event"; 463 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&rcc CK_KER_I2C7>; 465 resets = <&rcc I2C7_R>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 dmas = <&hpdma 45 0x20 0x3012>, 469 <&hpdma 46 0x20 0x3021>; 470 dma-names = "rx", "tx"; 471 access-controllers = <&rifsc 47>; 472 status = "disabled"; 473 }; 474 475 usart6: serial@40220000 { 476 compatible = "st,stm32h7-uart"; 477 reg = <0x40220000 0x400>; 478 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&rcc CK_KER_USART6>; 480 dmas = <&hpdma 19 0x20 0x10012>, 481 <&hpdma 20 0x20 0x3021>; 482 dma-names = "rx", "tx"; 483 access-controllers = <&rifsc 36>; 484 status = "disabled"; 485 }; 486 487 i2s1: audio-controller@40230000 { 488 compatible = "st,stm32mp25-i2s"; 489 reg = <0x40230000 0x400>; 490 #sound-dai-cells = <0>; 491 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>; 493 clock-names = "pclk", "i2sclk"; 494 resets = <&rcc SPI1_R>; 495 dmas = <&hpdma 49 0x43 0x12>, 496 <&hpdma 50 0x43 0x21>; 497 dma-names = "rx", "tx"; 498 access-controllers = <&rifsc 22>; 499 status = "disabled"; 500 }; 501 502 spi1: spi@40230000 { 503 #address-cells = <1>; 504 #size-cells = <0>; 505 compatible = "st,stm32mp25-spi"; 506 reg = <0x40230000 0x400>; 507 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&rcc CK_KER_SPI1>; 509 resets = <&rcc SPI1_R>; 510 dmas = <&hpdma 49 0x20 0x3012>, 511 <&hpdma 50 0x20 0x3021>; 512 dma-names = "rx", "tx"; 513 access-controllers = <&rifsc 22>; 514 status = "disabled"; 515 }; 516 517 spi4: spi@40240000 { 518 #address-cells = <1>; 519 #size-cells = <0>; 520 compatible = "st,stm32mp25-spi"; 521 reg = <0x40240000 0x400>; 522 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&rcc CK_KER_SPI4>; 524 resets = <&rcc SPI4_R>; 525 dmas = <&hpdma 55 0x20 0x3012>, 526 <&hpdma 56 0x20 0x3021>; 527 dma-names = "rx", "tx"; 528 access-controllers = <&rifsc 25>; 529 status = "disabled"; 530 }; 531 532 spi5: spi@40280000 { 533 #address-cells = <1>; 534 #size-cells = <0>; 535 compatible = "st,stm32mp25-spi"; 536 reg = <0x40280000 0x400>; 537 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&rcc CK_KER_SPI5>; 539 resets = <&rcc SPI5_R>; 540 dmas = <&hpdma 57 0x20 0x3012>, 541 <&hpdma 58 0x20 0x3021>; 542 dma-names = "rx", "tx"; 543 access-controllers = <&rifsc 26>; 544 status = "disabled"; 545 }; 546 547 sai1: sai@40290000 { 548 compatible = "st,stm32mp25-sai"; 549 reg = <0x40290000 0x4>, <0x4029a3f0 0x10>; 550 ranges = <0 0x40290000 0x400>; 551 #address-cells = <1>; 552 #size-cells = <1>; 553 clocks = <&rcc CK_BUS_SAI1>; 554 clock-names = "pclk"; 555 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 556 resets = <&rcc SAI1_R>; 557 access-controllers = <&rifsc 49>; 558 status = "disabled"; 559 560 sai1a: audio-controller@40290004 { 561 compatible = "st,stm32-sai-sub-a"; 562 reg = <0x4 0x20>; 563 #sound-dai-cells = <0>; 564 clocks = <&rcc CK_KER_SAI1>; 565 clock-names = "sai_ck"; 566 dmas = <&hpdma 73 0x43 0x21>; 567 status = "disabled"; 568 }; 569 570 sai1b: audio-controller@40290024 { 571 compatible = "st,stm32-sai-sub-b"; 572 reg = <0x24 0x20>; 573 #sound-dai-cells = <0>; 574 clocks = <&rcc CK_KER_SAI1>; 575 clock-names = "sai_ck"; 576 dmas = <&hpdma 74 0x43 0x12>; 577 status = "disabled"; 578 }; 579 }; 580 581 sai2: sai@402a0000 { 582 compatible = "st,stm32mp25-sai"; 583 reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>; 584 ranges = <0 0x402a0000 0x400>; 585 #address-cells = <1>; 586 #size-cells = <1>; 587 clocks = <&rcc CK_BUS_SAI2>; 588 clock-names = "pclk"; 589 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 590 resets = <&rcc SAI2_R>; 591 access-controllers = <&rifsc 50>; 592 status = "disabled"; 593 594 sai2a: audio-controller@402a0004 { 595 compatible = "st,stm32-sai-sub-a"; 596 reg = <0x4 0x20>; 597 #sound-dai-cells = <0>; 598 clocks = <&rcc CK_KER_SAI2>; 599 clock-names = "sai_ck"; 600 dmas = <&hpdma 75 0x43 0x21>; 601 status = "disabled"; 602 }; 603 604 sai2b: audio-controller@402a0024 { 605 compatible = "st,stm32-sai-sub-b"; 606 reg = <0x24 0x20>; 607 #sound-dai-cells = <0>; 608 clocks = <&rcc CK_KER_SAI2>; 609 clock-names = "sai_ck"; 610 dmas = <&hpdma 76 0x43 0x12>; 611 status = "disabled"; 612 }; 613 }; 614 615 sai3: sai@402b0000 { 616 compatible = "st,stm32mp25-sai"; 617 reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>; 618 ranges = <0 0x402b0000 0x400>; 619 #address-cells = <1>; 620 #size-cells = <1>; 621 clocks = <&rcc CK_BUS_SAI3>; 622 clock-names = "pclk"; 623 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 624 resets = <&rcc SAI3_R>; 625 access-controllers = <&rifsc 51>; 626 status = "disabled"; 627 628 sai3a: audio-controller@402b0004 { 629 compatible = "st,stm32-sai-sub-a"; 630 reg = <0x4 0x20>; 631 #sound-dai-cells = <0>; 632 clocks = <&rcc CK_KER_SAI3>; 633 clock-names = "sai_ck"; 634 dmas = <&hpdma 77 0x43 0x21>; 635 status = "disabled"; 636 }; 637 638 sai3b: audio-controller@502b0024 { 639 compatible = "st,stm32-sai-sub-b"; 640 reg = <0x24 0x20>; 641 #sound-dai-cells = <0>; 642 clocks = <&rcc CK_KER_SAI3>; 643 clock-names = "sai_ck"; 644 dmas = <&hpdma 78 0x43 0x12>; 645 status = "disabled"; 646 }; 647 }; 648 649 uart9: serial@402c0000 { 650 compatible = "st,stm32h7-uart"; 651 reg = <0x402c0000 0x400>; 652 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&rcc CK_KER_UART9>; 654 dmas = <&hpdma 25 0x20 0x10012>, 655 <&hpdma 26 0x20 0x3021>; 656 dma-names = "rx", "tx"; 657 access-controllers = <&rifsc 39>; 658 status = "disabled"; 659 }; 660 661 usart1: serial@40330000 { 662 compatible = "st,stm32h7-uart"; 663 reg = <0x40330000 0x400>; 664 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&rcc CK_KER_USART1>; 666 dmas = <&hpdma 9 0x20 0x10012>, 667 <&hpdma 10 0x20 0x3021>; 668 dma-names = "rx", "tx"; 669 access-controllers = <&rifsc 31>; 670 status = "disabled"; 671 }; 672 673 sai4: sai@40340000 { 674 compatible = "st,stm32mp25-sai"; 675 reg = <0x40340000 0x4>, <0x4034a3f0 0x10>; 676 ranges = <0 0x40340000 0x400>; 677 #address-cells = <1>; 678 #size-cells = <1>; 679 clocks = <&rcc CK_BUS_SAI4>; 680 clock-names = "pclk"; 681 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 682 resets = <&rcc SAI4_R>; 683 access-controllers = <&rifsc 52>; 684 status = "disabled"; 685 686 sai4a: audio-controller@40340004 { 687 compatible = "st,stm32-sai-sub-a"; 688 reg = <0x4 0x20>; 689 #sound-dai-cells = <0>; 690 clocks = <&rcc CK_KER_SAI4>; 691 clock-names = "sai_ck"; 692 dmas = <&hpdma 79 0x63 0x21>; 693 status = "disabled"; 694 }; 695 696 sai4b: audio-controller@40340024 { 697 compatible = "st,stm32-sai-sub-b"; 698 reg = <0x24 0x20>; 699 #sound-dai-cells = <0>; 700 clocks = <&rcc CK_KER_SAI4>; 701 clock-names = "sai_ck"; 702 dmas = <&hpdma 80 0x43 0x12>; 703 status = "disabled"; 704 }; 705 }; 706 707 spi6: spi@40350000 { 708 #address-cells = <1>; 709 #size-cells = <0>; 710 compatible = "st,stm32mp25-spi"; 711 reg = <0x40350000 0x400>; 712 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&rcc CK_KER_SPI6>; 714 resets = <&rcc SPI6_R>; 715 dmas = <&hpdma 59 0x20 0x3012>, 716 <&hpdma 60 0x20 0x3021>; 717 dma-names = "rx", "tx"; 718 access-controllers = <&rifsc 27>; 719 status = "disabled"; 720 }; 721 722 spi7: spi@40360000 { 723 #address-cells = <1>; 724 #size-cells = <0>; 725 compatible = "st,stm32mp25-spi"; 726 reg = <0x40360000 0x400>; 727 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&rcc CK_KER_SPI7>; 729 resets = <&rcc SPI7_R>; 730 dmas = <&hpdma 61 0x20 0x3012>, 731 <&hpdma 62 0x20 0x3021>; 732 dma-names = "rx", "tx"; 733 access-controllers = <&rifsc 28>; 734 status = "disabled"; 735 }; 736 737 uart7: serial@40370000 { 738 compatible = "st,stm32h7-uart"; 739 reg = <0x40370000 0x400>; 740 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&rcc CK_KER_UART7>; 742 dmas = <&hpdma 21 0x20 0x10012>, 743 <&hpdma 22 0x20 0x3021>; 744 dma-names = "rx", "tx"; 745 access-controllers = <&rifsc 37>; 746 status = "disabled"; 747 }; 748 749 uart8: serial@40380000 { 750 compatible = "st,stm32h7-uart"; 751 reg = <0x40380000 0x400>; 752 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&rcc CK_KER_UART8>; 754 dmas = <&hpdma 23 0x20 0x10012>, 755 <&hpdma 24 0x20 0x3021>; 756 dma-names = "rx", "tx"; 757 access-controllers = <&rifsc 38>; 758 status = "disabled"; 759 }; 760 761 rng: rng@42020000 { 762 compatible = "st,stm32mp25-rng"; 763 reg = <0x42020000 0x400>; 764 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 765 clock-names = "core", "bus"; 766 resets = <&rcc RNG_R>; 767 access-controllers = <&rifsc 92>; 768 status = "disabled"; 769 }; 770 771 spi8: spi@46020000 { 772 #address-cells = <1>; 773 #size-cells = <0>; 774 compatible = "st,stm32mp25-spi"; 775 reg = <0x46020000 0x400>; 776 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&rcc CK_KER_SPI8>; 778 resets = <&rcc SPI8_R>; 779 dmas = <&hpdma 171 0x20 0x3012>, 780 <&hpdma 172 0x20 0x3021>; 781 dma-names = "rx", "tx"; 782 access-controllers = <&rifsc 29>; 783 status = "disabled"; 784 }; 785 786 i2c8: i2c@46040000 { 787 compatible = "st,stm32mp25-i2c"; 788 reg = <0x46040000 0x400>; 789 interrupt-names = "event"; 790 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&rcc CK_KER_I2C8>; 792 resets = <&rcc I2C8_R>; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 dmas = <&hpdma 168 0x20 0x3012>, 796 <&hpdma 169 0x20 0x3021>; 797 dma-names = "rx", "tx"; 798 access-controllers = <&rifsc 48>; 799 status = "disabled"; 800 }; 801 802 csi: csi@48020000 { 803 compatible = "st,stm32mp25-csi"; 804 reg = <0x48020000 0x2000>; 805 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 806 resets = <&rcc CSI_R>; 807 clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, 808 <&rcc CK_KER_CSIPHY>; 809 clock-names = "pclk", "txesc", "csi2phy"; 810 access-controllers = <&rifsc 86>; 811 status = "disabled"; 812 }; 813 814 dcmipp: dcmipp@48030000 { 815 compatible = "st,stm32mp25-dcmipp"; 816 reg = <0x48030000 0x1000>; 817 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 818 resets = <&rcc DCMIPP_R>; 819 clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; 820 clock-names = "kclk", "mclk"; 821 access-controllers = <&rifsc 87>; 822 status = "disabled"; 823 }; 824 825 combophy: phy@480c0000 { 826 compatible = "st,stm32mp25-combophy"; 827 reg = <0x480c0000 0x1000>; 828 #phy-cells = <1>; 829 clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>; 830 clock-names = "apb", "ker"; 831 resets = <&rcc USB3PCIEPHY_R>; 832 reset-names = "phy"; 833 access-controllers = <&rifsc 67>; 834 power-domains = <&CLUSTER_PD>; 835 wakeup-source; 836 interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>; 837 status = "disabled"; 838 }; 839 840 sdmmc1: mmc@48220000 { 841 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 842 arm,primecell-periphid = <0x00353180>; 843 reg = <0x48220000 0x400>, <0x44230400 0x8>; 844 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&rcc CK_KER_SDMMC1 >; 846 clock-names = "apb_pclk"; 847 resets = <&rcc SDMMC1_R>; 848 cap-sd-highspeed; 849 cap-mmc-highspeed; 850 max-frequency = <120000000>; 851 access-controllers = <&rifsc 76>; 852 status = "disabled"; 853 }; 854 855 ethernet1: ethernet@482c0000 { 856 compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; 857 reg = <0x482c0000 0x4000>; 858 reg-names = "stmmaceth"; 859 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 860 interrupt-names = "macirq"; 861 clock-names = "stmmaceth", 862 "mac-clk-tx", 863 "mac-clk-rx", 864 "ptp_ref", 865 "ethstp", 866 "eth-ck"; 867 clocks = <&rcc CK_ETH1_MAC>, 868 <&rcc CK_ETH1_TX>, 869 <&rcc CK_ETH1_RX>, 870 <&rcc CK_KER_ETH1PTP>, 871 <&rcc CK_ETH1_STP>, 872 <&rcc CK_KER_ETH1>; 873 snps,axi-config = <&stmmac_axi_config_1>; 874 snps,mixed-burst; 875 snps,mtl-rx-config = <&mtl_rx_setup_1>; 876 snps,mtl-tx-config = <&mtl_tx_setup_1>; 877 snps,pbl = <2>; 878 snps,tso; 879 st,syscon = <&syscfg 0x3000>; 880 access-controllers = <&rifsc 60>; 881 status = "disabled"; 882 883 mtl_rx_setup_1: rx-queues-config { 884 snps,rx-queues-to-use = <2>; 885 queue0 {}; 886 queue1 {}; 887 }; 888 889 mtl_tx_setup_1: tx-queues-config { 890 snps,tx-queues-to-use = <4>; 891 queue0 {}; 892 queue1 {}; 893 queue2 {}; 894 queue3 {}; 895 }; 896 897 stmmac_axi_config_1: stmmac-axi-config { 898 snps,blen = <0 0 0 0 16 8 4>; 899 snps,rd_osr_lmt = <0x7>; 900 snps,wr_osr_lmt = <0x7>; 901 }; 902 }; 903 }; 904 905 bsec: efuse@44000000 { 906 compatible = "st,stm32mp25-bsec"; 907 reg = <0x44000000 0x1000>; 908 #address-cells = <1>; 909 #size-cells = <1>; 910 911 part_number_otp@24 { 912 reg = <0x24 0x4>; 913 }; 914 915 package_otp@1e8 { 916 reg = <0x1e8 0x1>; 917 bits = <0 3>; 918 }; 919 }; 920 921 rcc: clock-controller@44200000 { 922 compatible = "st,stm32mp25-rcc"; 923 reg = <0x44200000 0x10000>; 924 #clock-cells = <1>; 925 #reset-cells = <1>; 926 clocks = <&scmi_clk CK_SCMI_HSE>, 927 <&scmi_clk CK_SCMI_HSI>, 928 <&scmi_clk CK_SCMI_MSI>, 929 <&scmi_clk CK_SCMI_LSE>, 930 <&scmi_clk CK_SCMI_LSI>, 931 <&scmi_clk CK_SCMI_HSE_DIV2>, 932 <&scmi_clk CK_SCMI_ICN_HS_MCU>, 933 <&scmi_clk CK_SCMI_ICN_LS_MCU>, 934 <&scmi_clk CK_SCMI_ICN_SDMMC>, 935 <&scmi_clk CK_SCMI_ICN_DDR>, 936 <&scmi_clk CK_SCMI_ICN_DISPLAY>, 937 <&scmi_clk CK_SCMI_ICN_HSL>, 938 <&scmi_clk CK_SCMI_ICN_NIC>, 939 <&scmi_clk CK_SCMI_ICN_VID>, 940 <&scmi_clk CK_SCMI_FLEXGEN_07>, 941 <&scmi_clk CK_SCMI_FLEXGEN_08>, 942 <&scmi_clk CK_SCMI_FLEXGEN_09>, 943 <&scmi_clk CK_SCMI_FLEXGEN_10>, 944 <&scmi_clk CK_SCMI_FLEXGEN_11>, 945 <&scmi_clk CK_SCMI_FLEXGEN_12>, 946 <&scmi_clk CK_SCMI_FLEXGEN_13>, 947 <&scmi_clk CK_SCMI_FLEXGEN_14>, 948 <&scmi_clk CK_SCMI_FLEXGEN_15>, 949 <&scmi_clk CK_SCMI_FLEXGEN_16>, 950 <&scmi_clk CK_SCMI_FLEXGEN_17>, 951 <&scmi_clk CK_SCMI_FLEXGEN_18>, 952 <&scmi_clk CK_SCMI_FLEXGEN_19>, 953 <&scmi_clk CK_SCMI_FLEXGEN_20>, 954 <&scmi_clk CK_SCMI_FLEXGEN_21>, 955 <&scmi_clk CK_SCMI_FLEXGEN_22>, 956 <&scmi_clk CK_SCMI_FLEXGEN_23>, 957 <&scmi_clk CK_SCMI_FLEXGEN_24>, 958 <&scmi_clk CK_SCMI_FLEXGEN_25>, 959 <&scmi_clk CK_SCMI_FLEXGEN_26>, 960 <&scmi_clk CK_SCMI_FLEXGEN_27>, 961 <&scmi_clk CK_SCMI_FLEXGEN_28>, 962 <&scmi_clk CK_SCMI_FLEXGEN_29>, 963 <&scmi_clk CK_SCMI_FLEXGEN_30>, 964 <&scmi_clk CK_SCMI_FLEXGEN_31>, 965 <&scmi_clk CK_SCMI_FLEXGEN_32>, 966 <&scmi_clk CK_SCMI_FLEXGEN_33>, 967 <&scmi_clk CK_SCMI_FLEXGEN_34>, 968 <&scmi_clk CK_SCMI_FLEXGEN_35>, 969 <&scmi_clk CK_SCMI_FLEXGEN_36>, 970 <&scmi_clk CK_SCMI_FLEXGEN_37>, 971 <&scmi_clk CK_SCMI_FLEXGEN_38>, 972 <&scmi_clk CK_SCMI_FLEXGEN_39>, 973 <&scmi_clk CK_SCMI_FLEXGEN_40>, 974 <&scmi_clk CK_SCMI_FLEXGEN_41>, 975 <&scmi_clk CK_SCMI_FLEXGEN_42>, 976 <&scmi_clk CK_SCMI_FLEXGEN_43>, 977 <&scmi_clk CK_SCMI_FLEXGEN_44>, 978 <&scmi_clk CK_SCMI_FLEXGEN_45>, 979 <&scmi_clk CK_SCMI_FLEXGEN_46>, 980 <&scmi_clk CK_SCMI_FLEXGEN_47>, 981 <&scmi_clk CK_SCMI_FLEXGEN_48>, 982 <&scmi_clk CK_SCMI_FLEXGEN_49>, 983 <&scmi_clk CK_SCMI_FLEXGEN_50>, 984 <&scmi_clk CK_SCMI_FLEXGEN_51>, 985 <&scmi_clk CK_SCMI_FLEXGEN_52>, 986 <&scmi_clk CK_SCMI_FLEXGEN_53>, 987 <&scmi_clk CK_SCMI_FLEXGEN_54>, 988 <&scmi_clk CK_SCMI_FLEXGEN_55>, 989 <&scmi_clk CK_SCMI_FLEXGEN_56>, 990 <&scmi_clk CK_SCMI_FLEXGEN_57>, 991 <&scmi_clk CK_SCMI_FLEXGEN_58>, 992 <&scmi_clk CK_SCMI_FLEXGEN_59>, 993 <&scmi_clk CK_SCMI_FLEXGEN_60>, 994 <&scmi_clk CK_SCMI_FLEXGEN_61>, 995 <&scmi_clk CK_SCMI_FLEXGEN_62>, 996 <&scmi_clk CK_SCMI_FLEXGEN_63>, 997 <&scmi_clk CK_SCMI_ICN_APB1>, 998 <&scmi_clk CK_SCMI_ICN_APB2>, 999 <&scmi_clk CK_SCMI_ICN_APB3>, 1000 <&scmi_clk CK_SCMI_ICN_APB4>, 1001 <&scmi_clk CK_SCMI_ICN_APBDBG>, 1002 <&scmi_clk CK_SCMI_TIMG1>, 1003 <&scmi_clk CK_SCMI_TIMG2>, 1004 <&scmi_clk CK_SCMI_PLL3>, 1005 <&clk_dsi_txbyte>; 1006 access-controllers = <&rifsc 156>; 1007 }; 1008 1009 exti1: interrupt-controller@44220000 { 1010 compatible = "st,stm32mp1-exti", "syscon"; 1011 interrupt-controller; 1012 #interrupt-cells = <2>; 1013 reg = <0x44220000 0x400>; 1014 interrupts-extended = 1015 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 1016 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 1017 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 1018 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 1019 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1020 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1021 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1022 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1023 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 1024 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 1025 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 1026 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1027 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1028 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1029 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1030 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1031 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1032 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1033 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1034 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1035 <0>, /* EXTI_20 */ 1036 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1037 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1038 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1039 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1040 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1041 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1042 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1043 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1044 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1045 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 1046 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1047 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1048 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1049 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1050 <0>, 1051 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1052 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1053 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1054 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1055 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 1056 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1057 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1058 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1059 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1060 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1061 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1062 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1063 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1064 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1065 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 1066 <0>, 1067 <0>, 1068 <0>, 1069 <0>, 1070 <0>, 1071 <0>, 1072 <0>, 1073 <0>, 1074 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1075 <0>, /* EXTI_60 */ 1076 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1077 <0>, 1078 <0>, 1079 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1080 <0>, 1081 <0>, 1082 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1083 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1084 <0>, 1085 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 1086 <0>, 1087 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1088 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1089 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1090 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1091 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1092 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1093 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1094 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1095 <0>, /* EXTI_80 */ 1096 <0>, 1097 <0>, 1098 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1099 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 1100 }; 1101 1102 syscfg: syscon@44230000 { 1103 compatible = "st,stm32mp25-syscfg", "syscon"; 1104 reg = <0x44230000 0x10000>; 1105 }; 1106 1107 pinctrl: pinctrl@44240000 { 1108 #address-cells = <1>; 1109 #size-cells = <1>; 1110 compatible = "st,stm32mp257-pinctrl"; 1111 ranges = <0 0x44240000 0xa0400>; 1112 interrupt-parent = <&exti1>; 1113 st,syscfg = <&exti1 0x60 0xff>; 1114 pins-are-numbered; 1115 1116 gpioa: gpio@44240000 { 1117 gpio-controller; 1118 #gpio-cells = <2>; 1119 interrupt-controller; 1120 #interrupt-cells = <2>; 1121 reg = <0x0 0x400>; 1122 clocks = <&scmi_clk CK_SCMI_GPIOA>; 1123 st,bank-name = "GPIOA"; 1124 status = "disabled"; 1125 }; 1126 1127 gpiob: gpio@44250000 { 1128 gpio-controller; 1129 #gpio-cells = <2>; 1130 interrupt-controller; 1131 #interrupt-cells = <2>; 1132 reg = <0x10000 0x400>; 1133 clocks = <&scmi_clk CK_SCMI_GPIOB>; 1134 st,bank-name = "GPIOB"; 1135 status = "disabled"; 1136 }; 1137 1138 gpioc: gpio@44260000 { 1139 gpio-controller; 1140 #gpio-cells = <2>; 1141 interrupt-controller; 1142 #interrupt-cells = <2>; 1143 reg = <0x20000 0x400>; 1144 clocks = <&scmi_clk CK_SCMI_GPIOC>; 1145 st,bank-name = "GPIOC"; 1146 status = "disabled"; 1147 }; 1148 1149 gpiod: gpio@44270000 { 1150 gpio-controller; 1151 #gpio-cells = <2>; 1152 interrupt-controller; 1153 #interrupt-cells = <2>; 1154 reg = <0x30000 0x400>; 1155 clocks = <&scmi_clk CK_SCMI_GPIOD>; 1156 st,bank-name = "GPIOD"; 1157 status = "disabled"; 1158 }; 1159 1160 gpioe: gpio@44280000 { 1161 gpio-controller; 1162 #gpio-cells = <2>; 1163 interrupt-controller; 1164 #interrupt-cells = <2>; 1165 reg = <0x40000 0x400>; 1166 clocks = <&scmi_clk CK_SCMI_GPIOE>; 1167 st,bank-name = "GPIOE"; 1168 status = "disabled"; 1169 }; 1170 1171 gpiof: gpio@44290000 { 1172 gpio-controller; 1173 #gpio-cells = <2>; 1174 interrupt-controller; 1175 #interrupt-cells = <2>; 1176 reg = <0x50000 0x400>; 1177 clocks = <&scmi_clk CK_SCMI_GPIOF>; 1178 st,bank-name = "GPIOF"; 1179 status = "disabled"; 1180 }; 1181 1182 gpiog: gpio@442a0000 { 1183 gpio-controller; 1184 #gpio-cells = <2>; 1185 interrupt-controller; 1186 #interrupt-cells = <2>; 1187 reg = <0x60000 0x400>; 1188 clocks = <&scmi_clk CK_SCMI_GPIOG>; 1189 st,bank-name = "GPIOG"; 1190 status = "disabled"; 1191 }; 1192 1193 gpioh: gpio@442b0000 { 1194 gpio-controller; 1195 #gpio-cells = <2>; 1196 interrupt-controller; 1197 #interrupt-cells = <2>; 1198 reg = <0x70000 0x400>; 1199 clocks = <&scmi_clk CK_SCMI_GPIOH>; 1200 st,bank-name = "GPIOH"; 1201 status = "disabled"; 1202 }; 1203 1204 gpioi: gpio@442c0000 { 1205 gpio-controller; 1206 #gpio-cells = <2>; 1207 interrupt-controller; 1208 #interrupt-cells = <2>; 1209 reg = <0x80000 0x400>; 1210 clocks = <&scmi_clk CK_SCMI_GPIOI>; 1211 st,bank-name = "GPIOI"; 1212 status = "disabled"; 1213 }; 1214 1215 gpioj: gpio@442d0000 { 1216 gpio-controller; 1217 #gpio-cells = <2>; 1218 interrupt-controller; 1219 #interrupt-cells = <2>; 1220 reg = <0x90000 0x400>; 1221 clocks = <&scmi_clk CK_SCMI_GPIOJ>; 1222 st,bank-name = "GPIOJ"; 1223 status = "disabled"; 1224 }; 1225 1226 gpiok: gpio@442e0000 { 1227 gpio-controller; 1228 #gpio-cells = <2>; 1229 interrupt-controller; 1230 #interrupt-cells = <2>; 1231 reg = <0xa0000 0x400>; 1232 clocks = <&scmi_clk CK_SCMI_GPIOK>; 1233 st,bank-name = "GPIOK"; 1234 status = "disabled"; 1235 }; 1236 }; 1237 1238 rtc: rtc@46000000 { 1239 compatible = "st,stm32mp25-rtc"; 1240 reg = <0x46000000 0x400>; 1241 clocks = <&scmi_clk CK_SCMI_RTC>, 1242 <&scmi_clk CK_SCMI_RTCCK>; 1243 clock-names = "pclk", "rtc_ck"; 1244 interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>; 1245 status = "disabled"; 1246 }; 1247 1248 pinctrl_z: pinctrl@46200000 { 1249 #address-cells = <1>; 1250 #size-cells = <1>; 1251 compatible = "st,stm32mp257-z-pinctrl"; 1252 ranges = <0 0x46200000 0x400>; 1253 interrupt-parent = <&exti1>; 1254 st,syscfg = <&exti1 0x60 0xff>; 1255 pins-are-numbered; 1256 1257 gpioz: gpio@46200000 { 1258 gpio-controller; 1259 #gpio-cells = <2>; 1260 interrupt-controller; 1261 #interrupt-cells = <2>; 1262 reg = <0 0x400>; 1263 clocks = <&scmi_clk CK_SCMI_GPIOZ>; 1264 st,bank-name = "GPIOZ"; 1265 st,bank-ioport = <11>; 1266 status = "disabled"; 1267 }; 1268 1269 }; 1270 1271 exti2: interrupt-controller@46230000 { 1272 compatible = "st,stm32mp1-exti", "syscon"; 1273 interrupt-controller; 1274 #interrupt-cells = <2>; 1275 reg = <0x46230000 0x400>; 1276 interrupts-extended = 1277 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 1278 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1279 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1280 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1281 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1282 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1283 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1284 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1285 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1286 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1287 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 1288 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1289 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1290 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1291 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1292 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1293 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1294 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1295 <0>, 1296 <0>, 1297 <0>, /* EXTI_20 */ 1298 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1299 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1300 <0>, 1301 <0>, 1302 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1303 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1304 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1305 <0>, 1306 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1307 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 1308 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1309 <0>, 1310 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1311 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1312 <0>, 1313 <0>, 1314 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1315 <0>, 1316 <0>, 1317 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 1318 <0>, 1319 <0>, 1320 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1321 <0>, 1322 <0>, 1323 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1324 <0>, 1325 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1326 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1327 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 1328 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1329 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1330 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1331 <0>, 1332 <0>, 1333 <0>, 1334 <0>, 1335 <0>, 1336 <0>, 1337 <0>, /* EXTI_60 */ 1338 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1339 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1340 <0>, 1341 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1342 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1343 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1344 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1345 <0>, 1346 <0>, 1347 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 1348 }; 1349 }; 1350}; 1351