1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * asm-offsets.c: Calculate pt_regs and task_struct offsets.
4  *
5  * Copyright (C) 1996 David S. Miller
6  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle
7  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8  *
9  * Kevin Kissell, [email protected] and Carsten Langgaard, [email protected]
10  * Copyright (C) 2000 MIPS Technologies, Inc.
11  */
12 #include <linux/compat.h>
13 #include <linux/types.h>
14 #include <linux/sched.h>
15 #include <linux/mm.h>
16 #include <linux/kbuild.h>
17 #include <linux/suspend.h>
18 #include <asm/cpu-info.h>
19 #include <asm/pm.h>
20 #include <asm/ptrace.h>
21 #include <asm/processor.h>
22 #include <asm/smp-cps.h>
23 
24 #include <linux/kvm_host.h>
25 
26 void output_ptreg_defines(void);
output_ptreg_defines(void)27 void output_ptreg_defines(void)
28 {
29 	COMMENT("MIPS pt_regs offsets.");
30 #ifdef CONFIG_32BIT
31 	OFFSET(PT_ARG4, pt_regs, args[4]);
32 	OFFSET(PT_ARG5, pt_regs, args[5]);
33 	OFFSET(PT_ARG6, pt_regs, args[6]);
34 	OFFSET(PT_ARG7, pt_regs, args[7]);
35 #endif
36 	OFFSET(PT_R0, pt_regs, regs[0]);
37 	OFFSET(PT_R1, pt_regs, regs[1]);
38 	OFFSET(PT_R2, pt_regs, regs[2]);
39 	OFFSET(PT_R3, pt_regs, regs[3]);
40 	OFFSET(PT_R4, pt_regs, regs[4]);
41 	OFFSET(PT_R5, pt_regs, regs[5]);
42 	OFFSET(PT_R6, pt_regs, regs[6]);
43 	OFFSET(PT_R7, pt_regs, regs[7]);
44 	OFFSET(PT_R8, pt_regs, regs[8]);
45 	OFFSET(PT_R9, pt_regs, regs[9]);
46 	OFFSET(PT_R10, pt_regs, regs[10]);
47 	OFFSET(PT_R11, pt_regs, regs[11]);
48 	OFFSET(PT_R12, pt_regs, regs[12]);
49 	OFFSET(PT_R13, pt_regs, regs[13]);
50 	OFFSET(PT_R14, pt_regs, regs[14]);
51 	OFFSET(PT_R15, pt_regs, regs[15]);
52 	OFFSET(PT_R16, pt_regs, regs[16]);
53 	OFFSET(PT_R17, pt_regs, regs[17]);
54 	OFFSET(PT_R18, pt_regs, regs[18]);
55 	OFFSET(PT_R19, pt_regs, regs[19]);
56 	OFFSET(PT_R20, pt_regs, regs[20]);
57 	OFFSET(PT_R21, pt_regs, regs[21]);
58 	OFFSET(PT_R22, pt_regs, regs[22]);
59 	OFFSET(PT_R23, pt_regs, regs[23]);
60 	OFFSET(PT_R24, pt_regs, regs[24]);
61 	OFFSET(PT_R25, pt_regs, regs[25]);
62 	OFFSET(PT_R26, pt_regs, regs[26]);
63 	OFFSET(PT_R27, pt_regs, regs[27]);
64 	OFFSET(PT_R28, pt_regs, regs[28]);
65 	OFFSET(PT_R29, pt_regs, regs[29]);
66 	OFFSET(PT_R30, pt_regs, regs[30]);
67 	OFFSET(PT_R31, pt_regs, regs[31]);
68 	OFFSET(PT_LO, pt_regs, lo);
69 	OFFSET(PT_HI, pt_regs, hi);
70 #ifdef CONFIG_CPU_HAS_SMARTMIPS
71 	OFFSET(PT_ACX, pt_regs, acx);
72 #endif
73 	OFFSET(PT_EPC, pt_regs, cp0_epc);
74 	OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
75 	OFFSET(PT_STATUS, pt_regs, cp0_status);
76 	OFFSET(PT_CAUSE, pt_regs, cp0_cause);
77 #ifdef CONFIG_CPU_CAVIUM_OCTEON
78 	OFFSET(PT_MPL, pt_regs, mpl);
79 	OFFSET(PT_MTP, pt_regs, mtp);
80 #endif /* CONFIG_CPU_CAVIUM_OCTEON */
81 	DEFINE(PT_SIZE, sizeof(struct pt_regs));
82 	BLANK();
83 }
84 
85 void output_task_defines(void);
output_task_defines(void)86 void output_task_defines(void)
87 {
88 	COMMENT("MIPS task_struct offsets.");
89 	OFFSET(TASK_THREAD_INFO, task_struct, stack);
90 	OFFSET(TASK_FLAGS, task_struct, flags);
91 	OFFSET(TASK_MM, task_struct, mm);
92 	OFFSET(TASK_PID, task_struct, pid);
93 #if defined(CONFIG_STACKPROTECTOR)
94 	OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
95 #endif
96 	DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
97 	BLANK();
98 }
99 
100 void output_thread_info_defines(void);
output_thread_info_defines(void)101 void output_thread_info_defines(void)
102 {
103 	COMMENT("MIPS thread_info offsets.");
104 	OFFSET(TI_TASK, thread_info, task);
105 	OFFSET(TI_FLAGS, thread_info, flags);
106 	OFFSET(TI_TP_VALUE, thread_info, tp_value);
107 	OFFSET(TI_CPU, thread_info, cpu);
108 	OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
109 	OFFSET(TI_REGS, thread_info, regs);
110 	OFFSET(TI_SYSCALL, thread_info, syscall);
111 	DEFINE(_THREAD_SIZE, THREAD_SIZE);
112 	DEFINE(_THREAD_MASK, THREAD_MASK);
113 	DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE);
114 	DEFINE(_IRQ_STACK_START, IRQ_STACK_START);
115 	BLANK();
116 }
117 
118 void output_thread_defines(void);
output_thread_defines(void)119 void output_thread_defines(void)
120 {
121 	COMMENT("MIPS specific thread_struct offsets.");
122 	OFFSET(THREAD_REG16, task_struct, thread.reg16);
123 	OFFSET(THREAD_REG17, task_struct, thread.reg17);
124 	OFFSET(THREAD_REG18, task_struct, thread.reg18);
125 	OFFSET(THREAD_REG19, task_struct, thread.reg19);
126 	OFFSET(THREAD_REG20, task_struct, thread.reg20);
127 	OFFSET(THREAD_REG21, task_struct, thread.reg21);
128 	OFFSET(THREAD_REG22, task_struct, thread.reg22);
129 	OFFSET(THREAD_REG23, task_struct, thread.reg23);
130 	OFFSET(THREAD_REG29, task_struct, thread.reg29);
131 	OFFSET(THREAD_REG30, task_struct, thread.reg30);
132 	OFFSET(THREAD_REG31, task_struct, thread.reg31);
133 	OFFSET(THREAD_STATUS, task_struct,
134 	       thread.cp0_status);
135 
136 	OFFSET(THREAD_BVADDR, task_struct, \
137 	       thread.cp0_badvaddr);
138 	OFFSET(THREAD_BUADDR, task_struct, \
139 	       thread.cp0_baduaddr);
140 	OFFSET(THREAD_ECODE, task_struct, \
141 	       thread.error_code);
142 	OFFSET(THREAD_TRAPNO, task_struct, thread.trap_nr);
143 	BLANK();
144 }
145 
146 #ifdef CONFIG_MIPS_FP_SUPPORT
147 void output_thread_fpu_defines(void);
output_thread_fpu_defines(void)148 void output_thread_fpu_defines(void)
149 {
150 	OFFSET(THREAD_FPU, task_struct, thread.fpu);
151 
152 	OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]);
153 	OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]);
154 	OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]);
155 	OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]);
156 	OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]);
157 	OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]);
158 	OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]);
159 	OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]);
160 	OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]);
161 	OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]);
162 	OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]);
163 	OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]);
164 	OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]);
165 	OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]);
166 	OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]);
167 	OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]);
168 	OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]);
169 	OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]);
170 	OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]);
171 	OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]);
172 	OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]);
173 	OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]);
174 	OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]);
175 	OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]);
176 	OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]);
177 	OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]);
178 	OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]);
179 	OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]);
180 	OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]);
181 	OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]);
182 	OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
183 	OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
184 
185 	OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
186 	OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);
187 	BLANK();
188 }
189 #endif
190 
191 void output_mm_defines(void);
output_mm_defines(void)192 void output_mm_defines(void)
193 {
194 	COMMENT("Size of struct page");
195 	DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page));
196 	BLANK();
197 	COMMENT("Linux mm_struct offsets.");
198 	OFFSET(MM_USERS, mm_struct, mm_users);
199 	OFFSET(MM_PGD, mm_struct, pgd);
200 	OFFSET(MM_CONTEXT, mm_struct, context);
201 	BLANK();
202 	DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
203 	DEFINE(_PMD_T_SIZE, sizeof(pmd_t));
204 	DEFINE(_PTE_T_SIZE, sizeof(pte_t));
205 	BLANK();
206 	DEFINE(_PGD_T_LOG2, PGD_T_LOG2);
207 #ifndef __PAGETABLE_PMD_FOLDED
208 	DEFINE(_PMD_T_LOG2, PMD_T_LOG2);
209 #endif
210 	DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
211 	BLANK();
212 	BLANK();
213 	DEFINE(_PMD_SHIFT, PMD_SHIFT);
214 	DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT);
215 	BLANK();
216 	DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD);
217 	DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD);
218 	DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
219 	BLANK();
220 	DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
221 	DEFINE(_PAGE_SIZE, PAGE_SIZE);
222 	BLANK();
223 }
224 
225 #ifdef CONFIG_32BIT
226 void output_sc_defines(void);
output_sc_defines(void)227 void output_sc_defines(void)
228 {
229 	COMMENT("Linux sigcontext offsets.");
230 	OFFSET(SC_REGS, sigcontext, sc_regs);
231 	OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
232 	OFFSET(SC_ACX, sigcontext, sc_acx);
233 	OFFSET(SC_MDHI, sigcontext, sc_mdhi);
234 	OFFSET(SC_MDLO, sigcontext, sc_mdlo);
235 	OFFSET(SC_PC, sigcontext, sc_pc);
236 	OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
237 	OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir);
238 	OFFSET(SC_HI1, sigcontext, sc_hi1);
239 	OFFSET(SC_LO1, sigcontext, sc_lo1);
240 	OFFSET(SC_HI2, sigcontext, sc_hi2);
241 	OFFSET(SC_LO2, sigcontext, sc_lo2);
242 	OFFSET(SC_HI3, sigcontext, sc_hi3);
243 	OFFSET(SC_LO3, sigcontext, sc_lo3);
244 	BLANK();
245 }
246 #endif
247 
248 #ifdef CONFIG_64BIT
249 void output_sc_defines(void);
output_sc_defines(void)250 void output_sc_defines(void)
251 {
252 	COMMENT("Linux sigcontext offsets.");
253 	OFFSET(SC_REGS, sigcontext, sc_regs);
254 	OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
255 	OFFSET(SC_MDHI, sigcontext, sc_mdhi);
256 	OFFSET(SC_MDLO, sigcontext, sc_mdlo);
257 	OFFSET(SC_PC, sigcontext, sc_pc);
258 	OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
259 	BLANK();
260 }
261 #endif
262 
263 void output_signal_defined(void);
output_signal_defined(void)264 void output_signal_defined(void)
265 {
266 	COMMENT("Linux signal numbers.");
267 	DEFINE(_SIGHUP, SIGHUP);
268 	DEFINE(_SIGINT, SIGINT);
269 	DEFINE(_SIGQUIT, SIGQUIT);
270 	DEFINE(_SIGILL, SIGILL);
271 	DEFINE(_SIGTRAP, SIGTRAP);
272 	DEFINE(_SIGIOT, SIGIOT);
273 	DEFINE(_SIGABRT, SIGABRT);
274 	DEFINE(_SIGEMT, SIGEMT);
275 	DEFINE(_SIGFPE, SIGFPE);
276 	DEFINE(_SIGKILL, SIGKILL);
277 	DEFINE(_SIGBUS, SIGBUS);
278 	DEFINE(_SIGSEGV, SIGSEGV);
279 	DEFINE(_SIGSYS, SIGSYS);
280 	DEFINE(_SIGPIPE, SIGPIPE);
281 	DEFINE(_SIGALRM, SIGALRM);
282 	DEFINE(_SIGTERM, SIGTERM);
283 	DEFINE(_SIGUSR1, SIGUSR1);
284 	DEFINE(_SIGUSR2, SIGUSR2);
285 	DEFINE(_SIGCHLD, SIGCHLD);
286 	DEFINE(_SIGPWR, SIGPWR);
287 	DEFINE(_SIGWINCH, SIGWINCH);
288 	DEFINE(_SIGURG, SIGURG);
289 	DEFINE(_SIGIO, SIGIO);
290 	DEFINE(_SIGSTOP, SIGSTOP);
291 	DEFINE(_SIGTSTP, SIGTSTP);
292 	DEFINE(_SIGCONT, SIGCONT);
293 	DEFINE(_SIGTTIN, SIGTTIN);
294 	DEFINE(_SIGTTOU, SIGTTOU);
295 	DEFINE(_SIGVTALRM, SIGVTALRM);
296 	DEFINE(_SIGPROF, SIGPROF);
297 	DEFINE(_SIGXCPU, SIGXCPU);
298 	DEFINE(_SIGXFSZ, SIGXFSZ);
299 	BLANK();
300 }
301 
302 #ifdef CONFIG_CPU_CAVIUM_OCTEON
303 void output_octeon_cop2_state_defines(void);
output_octeon_cop2_state_defines(void)304 void output_octeon_cop2_state_defines(void)
305 {
306 	COMMENT("Octeon specific octeon_cop2_state offsets.");
307 	OFFSET(OCTEON_CP2_CRC_IV,	octeon_cop2_state, cop2_crc_iv);
308 	OFFSET(OCTEON_CP2_CRC_LENGTH,	octeon_cop2_state, cop2_crc_length);
309 	OFFSET(OCTEON_CP2_CRC_POLY,	octeon_cop2_state, cop2_crc_poly);
310 	OFFSET(OCTEON_CP2_LLM_DAT,	octeon_cop2_state, cop2_llm_dat);
311 	OFFSET(OCTEON_CP2_3DES_IV,	octeon_cop2_state, cop2_3des_iv);
312 	OFFSET(OCTEON_CP2_3DES_KEY,	octeon_cop2_state, cop2_3des_key);
313 	OFFSET(OCTEON_CP2_3DES_RESULT,	octeon_cop2_state, cop2_3des_result);
314 	OFFSET(OCTEON_CP2_AES_INP0,	octeon_cop2_state, cop2_aes_inp0);
315 	OFFSET(OCTEON_CP2_AES_IV,	octeon_cop2_state, cop2_aes_iv);
316 	OFFSET(OCTEON_CP2_AES_KEY,	octeon_cop2_state, cop2_aes_key);
317 	OFFSET(OCTEON_CP2_AES_KEYLEN,	octeon_cop2_state, cop2_aes_keylen);
318 	OFFSET(OCTEON_CP2_AES_RESULT,	octeon_cop2_state, cop2_aes_result);
319 	OFFSET(OCTEON_CP2_GFM_MULT,	octeon_cop2_state, cop2_gfm_mult);
320 	OFFSET(OCTEON_CP2_GFM_POLY,	octeon_cop2_state, cop2_gfm_poly);
321 	OFFSET(OCTEON_CP2_GFM_RESULT,	octeon_cop2_state, cop2_gfm_result);
322 	OFFSET(OCTEON_CP2_HSH_DATW,	octeon_cop2_state, cop2_hsh_datw);
323 	OFFSET(OCTEON_CP2_HSH_IVW,	octeon_cop2_state, cop2_hsh_ivw);
324 	OFFSET(OCTEON_CP2_SHA3,		octeon_cop2_state, cop2_sha3);
325 	OFFSET(THREAD_CP2,	task_struct, thread.cp2);
326 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
327     CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
328 	OFFSET(THREAD_CVMSEG,	task_struct, thread.cvmseg.cvmseg);
329 #endif
330 	BLANK();
331 }
332 #endif
333 
334 #ifdef CONFIG_HIBERNATION
335 void output_pbe_defines(void);
output_pbe_defines(void)336 void output_pbe_defines(void)
337 {
338 	COMMENT(" Linux struct pbe offsets. ");
339 	OFFSET(PBE_ADDRESS, pbe, address);
340 	OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
341 	OFFSET(PBE_NEXT, pbe, next);
342 	DEFINE(PBE_SIZE, sizeof(struct pbe));
343 	BLANK();
344 }
345 #endif
346 
347 #ifdef CONFIG_CPU_PM
348 void output_pm_defines(void);
output_pm_defines(void)349 void output_pm_defines(void)
350 {
351 	COMMENT(" PM offsets. ");
352 #ifdef CONFIG_EVA
353 	OFFSET(SSS_SEGCTL0,	mips_static_suspend_state, segctl[0]);
354 	OFFSET(SSS_SEGCTL1,	mips_static_suspend_state, segctl[1]);
355 	OFFSET(SSS_SEGCTL2,	mips_static_suspend_state, segctl[2]);
356 #endif
357 	OFFSET(SSS_SP,		mips_static_suspend_state, sp);
358 	BLANK();
359 }
360 #endif
361 
362 #ifdef CONFIG_MIPS_FP_SUPPORT
363 void output_kvm_defines(void);
output_kvm_defines(void)364 void output_kvm_defines(void)
365 {
366 	COMMENT(" KVM/MIPS Specific offsets. ");
367 
368 	OFFSET(VCPU_FPR0, kvm_vcpu_arch, fpu.fpr[0]);
369 	OFFSET(VCPU_FPR1, kvm_vcpu_arch, fpu.fpr[1]);
370 	OFFSET(VCPU_FPR2, kvm_vcpu_arch, fpu.fpr[2]);
371 	OFFSET(VCPU_FPR3, kvm_vcpu_arch, fpu.fpr[3]);
372 	OFFSET(VCPU_FPR4, kvm_vcpu_arch, fpu.fpr[4]);
373 	OFFSET(VCPU_FPR5, kvm_vcpu_arch, fpu.fpr[5]);
374 	OFFSET(VCPU_FPR6, kvm_vcpu_arch, fpu.fpr[6]);
375 	OFFSET(VCPU_FPR7, kvm_vcpu_arch, fpu.fpr[7]);
376 	OFFSET(VCPU_FPR8, kvm_vcpu_arch, fpu.fpr[8]);
377 	OFFSET(VCPU_FPR9, kvm_vcpu_arch, fpu.fpr[9]);
378 	OFFSET(VCPU_FPR10, kvm_vcpu_arch, fpu.fpr[10]);
379 	OFFSET(VCPU_FPR11, kvm_vcpu_arch, fpu.fpr[11]);
380 	OFFSET(VCPU_FPR12, kvm_vcpu_arch, fpu.fpr[12]);
381 	OFFSET(VCPU_FPR13, kvm_vcpu_arch, fpu.fpr[13]);
382 	OFFSET(VCPU_FPR14, kvm_vcpu_arch, fpu.fpr[14]);
383 	OFFSET(VCPU_FPR15, kvm_vcpu_arch, fpu.fpr[15]);
384 	OFFSET(VCPU_FPR16, kvm_vcpu_arch, fpu.fpr[16]);
385 	OFFSET(VCPU_FPR17, kvm_vcpu_arch, fpu.fpr[17]);
386 	OFFSET(VCPU_FPR18, kvm_vcpu_arch, fpu.fpr[18]);
387 	OFFSET(VCPU_FPR19, kvm_vcpu_arch, fpu.fpr[19]);
388 	OFFSET(VCPU_FPR20, kvm_vcpu_arch, fpu.fpr[20]);
389 	OFFSET(VCPU_FPR21, kvm_vcpu_arch, fpu.fpr[21]);
390 	OFFSET(VCPU_FPR22, kvm_vcpu_arch, fpu.fpr[22]);
391 	OFFSET(VCPU_FPR23, kvm_vcpu_arch, fpu.fpr[23]);
392 	OFFSET(VCPU_FPR24, kvm_vcpu_arch, fpu.fpr[24]);
393 	OFFSET(VCPU_FPR25, kvm_vcpu_arch, fpu.fpr[25]);
394 	OFFSET(VCPU_FPR26, kvm_vcpu_arch, fpu.fpr[26]);
395 	OFFSET(VCPU_FPR27, kvm_vcpu_arch, fpu.fpr[27]);
396 	OFFSET(VCPU_FPR28, kvm_vcpu_arch, fpu.fpr[28]);
397 	OFFSET(VCPU_FPR29, kvm_vcpu_arch, fpu.fpr[29]);
398 	OFFSET(VCPU_FPR30, kvm_vcpu_arch, fpu.fpr[30]);
399 	OFFSET(VCPU_FPR31, kvm_vcpu_arch, fpu.fpr[31]);
400 
401 	OFFSET(VCPU_FCR31, kvm_vcpu_arch, fpu.fcr31);
402 	OFFSET(VCPU_MSA_CSR, kvm_vcpu_arch, fpu.msacsr);
403 	BLANK();
404 }
405 #endif
406 
407 #ifdef CONFIG_MIPS_CPS
408 void output_cps_defines(void);
output_cps_defines(void)409 void output_cps_defines(void)
410 {
411 	COMMENT(" MIPS CPS offsets. ");
412 
413 	OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask);
414 	OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config);
415 	DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config));
416 
417 	OFFSET(VPEBOOTCFG_PC, vpe_boot_config, pc);
418 	OFFSET(VPEBOOTCFG_SP, vpe_boot_config, sp);
419 	OFFSET(VPEBOOTCFG_GP, vpe_boot_config, gp);
420 	DEFINE(VPEBOOTCFG_SIZE, sizeof(struct vpe_boot_config));
421 }
422 #endif
423