1 /* SPDX-License-Identifier: GPL-2.0 */
2 #include <linux/jump_label.h>
3 #include <asm/unwind_hints.h>
4 #include <asm/cpufeatures.h>
5 #include <asm/page_types.h>
6 #include <asm/percpu.h>
7 #include <asm/asm-offsets.h>
8 #include <asm/processor-flags.h>
9 #include <asm/ptrace-abi.h>
10 #include <asm/msr.h>
11 #include <asm/nospec-branch.h>
12 
13 /*
14 
15  x86 function call convention, 64-bit:
16  -------------------------------------
17   arguments           |  callee-saved      | extra caller-saved | return
18  [callee-clobbered]   |                    | [callee-clobbered] |
19  ---------------------------------------------------------------------------
20  rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11             | rax, rdx [**]
21 
22  ( rsp is obviously invariant across normal function calls. (gcc can 'merge'
23    functions when it sees tail-call optimization possibilities) rflags is
24    clobbered. Leftover arguments are passed over the stack frame.)
25 
26  [*]  In the frame-pointers case rbp is fixed to the stack frame.
27 
28  [**] for struct return values wider than 64 bits the return convention is a
29       bit more complex: up to 128 bits width we return small structures
30       straight in rax, rdx. For structures larger than that (3 words or
31       larger) the caller puts a pointer to an on-stack return struct
32       [allocated in the caller's stack frame] into the first argument - i.e.
33       into rdi. All other arguments shift up by one in this case.
34       Fortunately this case is rare in the kernel.
35 
36 For 32-bit we have the following conventions - kernel is built with
37 -mregparm=3 and -freg-struct-return:
38 
39  x86 function calling convention, 32-bit:
40  ----------------------------------------
41   arguments         | callee-saved        | extra caller-saved | return
42  [callee-clobbered] |                     | [callee-clobbered] |
43  -------------------------------------------------------------------------
44  eax edx ecx        | ebx edi esi ebp [*] | <none>             | eax, edx [**]
45 
46  ( here too esp is obviously invariant across normal function calls. eflags
47    is clobbered. Leftover arguments are passed over the stack frame. )
48 
49  [*]  In the frame-pointers case ebp is fixed to the stack frame.
50 
51  [**] We build with -freg-struct-return, which on 32-bit means similar
52       semantics as on 64-bit: edx can be used for a second return value
53       (i.e. covering integer and structure sizes up to 64 bits) - after that
54       it gets more complex and more expensive: 3-word or larger struct returns
55       get done in the caller's frame and the pointer to the return struct goes
56       into regparm0, i.e. eax - the other arguments shift up and the
57       function's register parameters degenerate to regparm=2 in essence.
58 
59 */
60 
61 #ifdef CONFIG_X86_64
62 
63 /*
64  * 64-bit system call stack frame layout defines and helpers,
65  * for assembly code:
66  */
67 
68 .macro PUSH_REGS rdx=%rdx rcx=%rcx rax=%rax save_ret=0 unwind_hint=1
69 	.if \save_ret
70 	pushq	%rsi		/* pt_regs->si */
71 	movq	8(%rsp), %rsi	/* temporarily store the return address in %rsi */
72 	movq	%rdi, 8(%rsp)	/* pt_regs->di (overwriting original return address) */
73 	/* We just clobbered the return address - use the IRET frame for unwinding: */
74 	UNWIND_HINT_IRET_REGS offset=3*8
75 	.else
76 	pushq   %rdi		/* pt_regs->di */
77 	pushq   %rsi		/* pt_regs->si */
78 	.endif
79 	pushq	\rdx		/* pt_regs->dx */
80 	pushq   \rcx		/* pt_regs->cx */
81 	pushq   \rax		/* pt_regs->ax */
82 	pushq   %r8		/* pt_regs->r8 */
83 	pushq   %r9		/* pt_regs->r9 */
84 	pushq   %r10		/* pt_regs->r10 */
85 	pushq   %r11		/* pt_regs->r11 */
86 	pushq	%rbx		/* pt_regs->rbx */
87 	pushq	%rbp		/* pt_regs->rbp */
88 	pushq	%r12		/* pt_regs->r12 */
89 	pushq	%r13		/* pt_regs->r13 */
90 	pushq	%r14		/* pt_regs->r14 */
91 	pushq	%r15		/* pt_regs->r15 */
92 
93 	.if \unwind_hint
94 	UNWIND_HINT_REGS
95 	.endif
96 
97 	.if \save_ret
98 	pushq	%rsi		/* return address on top of stack */
99 	.endif
100 .endm
101 
102 .macro CLEAR_REGS clear_bp=1
103 	/*
104 	 * Sanitize registers of values that a speculation attack might
105 	 * otherwise want to exploit. The lower registers are likely clobbered
106 	 * well before they could be put to use in a speculative execution
107 	 * gadget.
108 	 */
109 	xorl	%esi,  %esi	/* nospec si  */
110 	xorl	%edx,  %edx	/* nospec dx  */
111 	xorl	%ecx,  %ecx	/* nospec cx  */
112 	xorl	%r8d,  %r8d	/* nospec r8  */
113 	xorl	%r9d,  %r9d	/* nospec r9  */
114 	xorl	%r10d, %r10d	/* nospec r10 */
115 	xorl	%r11d, %r11d	/* nospec r11 */
116 	xorl	%ebx,  %ebx	/* nospec rbx */
117 	.if \clear_bp
118 	xorl	%ebp,  %ebp	/* nospec rbp */
119 	.endif
120 	xorl	%r12d, %r12d	/* nospec r12 */
121 	xorl	%r13d, %r13d	/* nospec r13 */
122 	xorl	%r14d, %r14d	/* nospec r14 */
123 	xorl	%r15d, %r15d	/* nospec r15 */
124 
125 .endm
126 
127 .macro PUSH_AND_CLEAR_REGS rdx=%rdx rcx=%rcx rax=%rax save_ret=0 clear_bp=1 unwind_hint=1
128 	PUSH_REGS rdx=\rdx, rcx=\rcx, rax=\rax, save_ret=\save_ret unwind_hint=\unwind_hint
129 	CLEAR_REGS clear_bp=\clear_bp
130 .endm
131 
132 .macro POP_REGS pop_rdi=1
133 	popq %r15
134 	popq %r14
135 	popq %r13
136 	popq %r12
137 	popq %rbp
138 	popq %rbx
139 	popq %r11
140 	popq %r10
141 	popq %r9
142 	popq %r8
143 	popq %rax
144 	popq %rcx
145 	popq %rdx
146 	popq %rsi
147 	.if \pop_rdi
148 	popq %rdi
149 	.endif
150 .endm
151 
152 #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
153 
154 /*
155  * MITIGATION_PAGE_TABLE_ISOLATION PGDs are 8k.  Flip bit 12 to switch between the two
156  * halves:
157  */
158 #define PTI_USER_PGTABLE_BIT		PAGE_SHIFT
159 #define PTI_USER_PGTABLE_MASK		(1 << PTI_USER_PGTABLE_BIT)
160 #define PTI_USER_PCID_BIT		X86_CR3_PTI_PCID_USER_BIT
161 #define PTI_USER_PCID_MASK		(1 << PTI_USER_PCID_BIT)
162 #define PTI_USER_PGTABLE_AND_PCID_MASK  (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK)
163 
164 .macro SET_NOFLUSH_BIT	reg:req
165 	bts	$X86_CR3_PCID_NOFLUSH_BIT, \reg
166 .endm
167 
168 .macro ADJUST_KERNEL_CR3 reg:req
169 	ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID
170 	/* Clear PCID and "MITIGATION_PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */
171 	andq    $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg
172 .endm
173 
174 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
175 	ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
176 	mov	%cr3, \scratch_reg
177 	ADJUST_KERNEL_CR3 \scratch_reg
178 	mov	\scratch_reg, %cr3
179 .Lend_\@:
180 .endm
181 
182 #define THIS_CPU_user_pcid_flush_mask   \
183 	PER_CPU_VAR(cpu_tlbstate + TLB_STATE_user_pcid_flush_mask)
184 
185 .macro SWITCH_TO_USER_CR3 scratch_reg:req scratch_reg2:req
186 	mov	%cr3, \scratch_reg
187 
188 	ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
189 
190 	/*
191 	 * Test if the ASID needs a flush.
192 	 */
193 	movq	\scratch_reg, \scratch_reg2
194 	andq	$(0x7FF), \scratch_reg		/* mask ASID */
195 	bt	\scratch_reg, THIS_CPU_user_pcid_flush_mask
196 	jnc	.Lnoflush_\@
197 
198 	/* Flush needed, clear the bit */
199 	btr	\scratch_reg, THIS_CPU_user_pcid_flush_mask
200 	movq	\scratch_reg2, \scratch_reg
201 	jmp	.Lwrcr3_pcid_\@
202 
203 .Lnoflush_\@:
204 	movq	\scratch_reg2, \scratch_reg
205 	SET_NOFLUSH_BIT \scratch_reg
206 
207 .Lwrcr3_pcid_\@:
208 	/* Flip the ASID to the user version */
209 	orq	$(PTI_USER_PCID_MASK), \scratch_reg
210 
211 .Lwrcr3_\@:
212 	/* Flip the PGD to the user version */
213 	orq     $(PTI_USER_PGTABLE_MASK), \scratch_reg
214 	mov	\scratch_reg, %cr3
215 .endm
216 
217 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
218 	ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
219 	SWITCH_TO_USER_CR3 \scratch_reg \scratch_reg2
220 .Lend_\@:
221 .endm
222 
223 .macro SWITCH_TO_USER_CR3_STACK	scratch_reg:req
224 	ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
225 	pushq	%rax
226 	SWITCH_TO_USER_CR3 scratch_reg=\scratch_reg scratch_reg2=%rax
227 	popq	%rax
228 .Lend_\@:
229 .endm
230 
231 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
232 	ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI
233 	movq	%cr3, \scratch_reg
234 	movq	\scratch_reg, \save_reg
235 	/*
236 	 * Test the user pagetable bit. If set, then the user page tables
237 	 * are active. If clear CR3 already has the kernel page table
238 	 * active.
239 	 */
240 	bt	$PTI_USER_PGTABLE_BIT, \scratch_reg
241 	jnc	.Ldone_\@
242 
243 	ADJUST_KERNEL_CR3 \scratch_reg
244 	movq	\scratch_reg, %cr3
245 
246 .Ldone_\@:
247 .endm
248 
249 /* Restore CR3 from a kernel context. May restore a user CR3 value. */
250 .macro PARANOID_RESTORE_CR3 scratch_reg:req save_reg:req
251 	ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
252 
253 	/*
254 	 * If CR3 contained the kernel page tables at the paranoid exception
255 	 * entry, then there is nothing to restore as CR3 is not modified while
256 	 * handling the exception.
257 	 */
258 	bt	$PTI_USER_PGTABLE_BIT, \save_reg
259 	jnc	.Lend_\@
260 
261 	ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
262 
263 	/*
264 	 * Check if there's a pending flush for the user ASID we're
265 	 * about to set.
266 	 */
267 	movq	\save_reg, \scratch_reg
268 	andq	$(0x7FF), \scratch_reg
269 	btr	\scratch_reg, THIS_CPU_user_pcid_flush_mask
270 	jc	.Lwrcr3_\@
271 
272 	SET_NOFLUSH_BIT \save_reg
273 
274 .Lwrcr3_\@:
275 	movq	\save_reg, %cr3
276 .Lend_\@:
277 .endm
278 
279 #else /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION=n: */
280 
281 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
282 .endm
283 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
284 .endm
285 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
286 .endm
287 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
288 .endm
289 .macro PARANOID_RESTORE_CR3 scratch_reg:req save_reg:req
290 .endm
291 
292 #endif
293 
294 /*
295  * IBRS kernel mitigation for Spectre_v2.
296  *
297  * Assumes full context is established (PUSH_REGS, CR3 and GS) and it clobbers
298  * the regs it uses (AX, CX, DX). Must be called before the first RET
299  * instruction (NOTE! UNTRAIN_RET includes a RET instruction)
300  *
301  * The optional argument is used to save/restore the current value,
302  * which is used on the paranoid paths.
303  *
304  * Assumes x86_spec_ctrl_{base,current} to have SPEC_CTRL_IBRS set.
305  */
306 .macro IBRS_ENTER save_reg
307 #ifdef CONFIG_MITIGATION_IBRS_ENTRY
308 	ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
309 	movl	$MSR_IA32_SPEC_CTRL, %ecx
310 
311 .ifnb \save_reg
312 	rdmsr
313 	shl	$32, %rdx
314 	or	%rdx, %rax
315 	mov	%rax, \save_reg
316 	test	$SPEC_CTRL_IBRS, %eax
317 	jz	.Ldo_wrmsr_\@
318 	lfence
319 	jmp	.Lend_\@
320 .Ldo_wrmsr_\@:
321 .endif
322 
323 	movq	PER_CPU_VAR(x86_spec_ctrl_current), %rdx
324 	movl	%edx, %eax
325 	shr	$32, %rdx
326 	wrmsr
327 .Lend_\@:
328 #endif
329 .endm
330 
331 /*
332  * Similar to IBRS_ENTER, requires KERNEL GS,CR3 and clobbers (AX, CX, DX)
333  * regs. Must be called after the last RET.
334  */
335 .macro IBRS_EXIT save_reg
336 #ifdef CONFIG_MITIGATION_IBRS_ENTRY
337 	ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
338 	movl	$MSR_IA32_SPEC_CTRL, %ecx
339 
340 .ifnb \save_reg
341 	mov	\save_reg, %rdx
342 .else
343 	movq	PER_CPU_VAR(x86_spec_ctrl_current), %rdx
344 	andl	$(~SPEC_CTRL_IBRS), %edx
345 .endif
346 
347 	movl	%edx, %eax
348 	shr	$32, %rdx
349 	wrmsr
350 .Lend_\@:
351 #endif
352 .endm
353 
354 /*
355  * Mitigate Spectre v1 for conditional swapgs code paths.
356  *
357  * FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to
358  * prevent a speculative swapgs when coming from kernel space.
359  *
360  * FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path,
361  * to prevent the swapgs from getting speculatively skipped when coming from
362  * user space.
363  */
364 .macro FENCE_SWAPGS_USER_ENTRY
365 	ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER
366 .endm
367 .macro FENCE_SWAPGS_KERNEL_ENTRY
368 	ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL
369 .endm
370 
371 .macro STACKLEAK_ERASE_NOCLOBBER
372 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
373 	PUSH_AND_CLEAR_REGS
374 	call stackleak_erase
375 	POP_REGS
376 #endif
377 .endm
378 
379 .macro SAVE_AND_SET_GSBASE scratch_reg:req save_reg:req
380 	rdgsbase \save_reg
381 	GET_PERCPU_BASE \scratch_reg
382 	wrgsbase \scratch_reg
383 .endm
384 
385 #else /* CONFIG_X86_64 */
386 # undef		UNWIND_HINT_IRET_REGS
387 # define	UNWIND_HINT_IRET_REGS
388 #endif /* !CONFIG_X86_64 */
389 
390 .macro STACKLEAK_ERASE
391 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
392 	call stackleak_erase
393 #endif
394 .endm
395 
396 #ifdef CONFIG_SMP
397 
398 /*
399  * CPU/node NR is loaded from the limit (size) field of a special segment
400  * descriptor entry in GDT.
401  */
402 .macro LOAD_CPU_AND_NODE_SEG_LIMIT reg:req
403 	movq	$__CPUNODE_SEG, \reg
404 	lsl	\reg, \reg
405 .endm
406 
407 /*
408  * Fetch the per-CPU GSBASE value for this processor and put it in @reg.
409  * We normally use %gs for accessing per-CPU data, but we are setting up
410  * %gs here and obviously can not use %gs itself to access per-CPU data.
411  *
412  * Do not use RDPID, because KVM loads guest's TSC_AUX on vm-entry and
413  * may not restore the host's value until the CPU returns to userspace.
414  * Thus the kernel would consume a guest's TSC_AUX if an NMI arrives
415  * while running KVM's run loop.
416  */
417 .macro GET_PERCPU_BASE reg:req
418 	LOAD_CPU_AND_NODE_SEG_LIMIT \reg
419 	andq	$VDSO_CPUNODE_MASK, \reg
420 	movq	__per_cpu_offset(, \reg, 8), \reg
421 .endm
422 
423 #else
424 
425 .macro GET_PERCPU_BASE reg:req
426 	movq	pcpu_unit_offsets(%rip), \reg
427 .endm
428 
429 #endif /* CONFIG_SMP */
430 
431 #ifdef CONFIG_X86_64
432 
433 /* rdi:	arg1 ... normal C conventions. rax is saved/restored. */
434 .macro THUNK name, func
435 SYM_FUNC_START(\name)
436 	pushq %rbp
437 	movq %rsp, %rbp
438 
439 	pushq %rdi
440 	pushq %rsi
441 	pushq %rdx
442 	pushq %rcx
443 	pushq %rax
444 	pushq %r8
445 	pushq %r9
446 	pushq %r10
447 	pushq %r11
448 
449 	call \func
450 
451 	popq %r11
452 	popq %r10
453 	popq %r9
454 	popq %r8
455 	popq %rax
456 	popq %rcx
457 	popq %rdx
458 	popq %rsi
459 	popq %rdi
460 	popq %rbp
461 	RET
462 SYM_FUNC_END(\name)
463 	_ASM_NOKPROBE(\name)
464 .endm
465 
466 #else /* CONFIG_X86_32 */
467 
468 /* put return address in eax (arg1) */
469 .macro THUNK name, func, put_ret_addr_in_eax=0
470 SYM_CODE_START_NOALIGN(\name)
471 	pushl %eax
472 	pushl %ecx
473 	pushl %edx
474 
475 	.if \put_ret_addr_in_eax
476 	/* Place EIP in the arg1 */
477 	movl 3*4(%esp), %eax
478 	.endif
479 
480 	call \func
481 	popl %edx
482 	popl %ecx
483 	popl %eax
484 	RET
485 	_ASM_NOKPROBE(\name)
486 SYM_CODE_END(\name)
487 	.endm
488 
489 #endif
490