1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/bitops.h>
3 #include <linux/types.h>
4 #include <linux/slab.h>
5 #include <linux/sched/clock.h>
6
7 #include <asm/cpu_entry_area.h>
8 #include <asm/debugreg.h>
9 #include <asm/perf_event.h>
10 #include <asm/tlbflush.h>
11 #include <asm/insn.h>
12 #include <asm/io.h>
13 #include <asm/timer.h>
14
15 #include "../perf_event.h"
16
17 /* Waste a full page so it can be mapped into the cpu_entry_area */
18 DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
19
20 /* The size of a BTS record in bytes: */
21 #define BTS_RECORD_SIZE 24
22
23 #define PEBS_FIXUP_SIZE PAGE_SIZE
24
25 /*
26 * pebs_record_32 for p4 and core not supported
27
28 struct pebs_record_32 {
29 u32 flags, ip;
30 u32 ax, bc, cx, dx;
31 u32 si, di, bp, sp;
32 };
33
34 */
35
36 union intel_x86_pebs_dse {
37 u64 val;
38 struct {
39 unsigned int ld_dse:4;
40 unsigned int ld_stlb_miss:1;
41 unsigned int ld_locked:1;
42 unsigned int ld_data_blk:1;
43 unsigned int ld_addr_blk:1;
44 unsigned int ld_reserved:24;
45 };
46 struct {
47 unsigned int st_l1d_hit:1;
48 unsigned int st_reserved1:3;
49 unsigned int st_stlb_miss:1;
50 unsigned int st_locked:1;
51 unsigned int st_reserved2:26;
52 };
53 struct {
54 unsigned int st_lat_dse:4;
55 unsigned int st_lat_stlb_miss:1;
56 unsigned int st_lat_locked:1;
57 unsigned int ld_reserved3:26;
58 };
59 struct {
60 unsigned int mtl_dse:5;
61 unsigned int mtl_locked:1;
62 unsigned int mtl_stlb_miss:1;
63 unsigned int mtl_fwd_blk:1;
64 unsigned int ld_reserved4:24;
65 };
66 struct {
67 unsigned int lnc_dse:8;
68 unsigned int ld_reserved5:2;
69 unsigned int lnc_stlb_miss:1;
70 unsigned int lnc_locked:1;
71 unsigned int lnc_data_blk:1;
72 unsigned int lnc_addr_blk:1;
73 unsigned int ld_reserved6:18;
74 };
75 };
76
77
78 /*
79 * Map PEBS Load Latency Data Source encodings to generic
80 * memory data source information
81 */
82 #define P(a, b) PERF_MEM_S(a, b)
83 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
84 #define LEVEL(x) P(LVLNUM, x)
85 #define REM P(REMOTE, REMOTE)
86 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
87
88 /* Version for Sandy Bridge and later */
89 static u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX] = {
90 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
91 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */
92 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
93 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
94 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
95 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
96 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
97 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
98 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
99 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
100 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
101 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
102 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */
103 OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */
104 OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */
105 OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */
106 };
107
108 /* Patch up minor differences in the bits */
intel_pmu_pebs_data_source_nhm(void)109 void __init intel_pmu_pebs_data_source_nhm(void)
110 {
111 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
112 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
113 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
114 }
115
__intel_pmu_pebs_data_source_skl(bool pmem,u64 * data_source)116 static void __init __intel_pmu_pebs_data_source_skl(bool pmem, u64 *data_source)
117 {
118 u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4);
119
120 data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT);
121 data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT);
122 data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
123 data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD);
124 data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM);
125 }
126
intel_pmu_pebs_data_source_skl(bool pmem)127 void __init intel_pmu_pebs_data_source_skl(bool pmem)
128 {
129 __intel_pmu_pebs_data_source_skl(pmem, pebs_data_source);
130 }
131
__intel_pmu_pebs_data_source_grt(u64 * data_source)132 static void __init __intel_pmu_pebs_data_source_grt(u64 *data_source)
133 {
134 data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
135 data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
136 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD);
137 }
138
intel_pmu_pebs_data_source_grt(void)139 void __init intel_pmu_pebs_data_source_grt(void)
140 {
141 __intel_pmu_pebs_data_source_grt(pebs_data_source);
142 }
143
intel_pmu_pebs_data_source_adl(void)144 void __init intel_pmu_pebs_data_source_adl(void)
145 {
146 u64 *data_source;
147
148 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source;
149 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
150 __intel_pmu_pebs_data_source_skl(false, data_source);
151
152 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;
153 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
154 __intel_pmu_pebs_data_source_grt(data_source);
155 }
156
__intel_pmu_pebs_data_source_cmt(u64 * data_source)157 static void __init __intel_pmu_pebs_data_source_cmt(u64 *data_source)
158 {
159 data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD);
160 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
161 data_source[0x0a] = OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, NONE);
162 data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
163 data_source[0x0c] = OP_LH | LEVEL(RAM) | REM | P(SNOOPX, FWD);
164 data_source[0x0d] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, HITM);
165 }
166
intel_pmu_pebs_data_source_mtl(void)167 void __init intel_pmu_pebs_data_source_mtl(void)
168 {
169 u64 *data_source;
170
171 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source;
172 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
173 __intel_pmu_pebs_data_source_skl(false, data_source);
174
175 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;
176 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
177 __intel_pmu_pebs_data_source_cmt(data_source);
178 }
179
intel_pmu_pebs_data_source_arl_h(void)180 void __init intel_pmu_pebs_data_source_arl_h(void)
181 {
182 u64 *data_source;
183
184 intel_pmu_pebs_data_source_lnl();
185
186 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX].pebs_data_source;
187 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
188 __intel_pmu_pebs_data_source_cmt(data_source);
189 }
190
intel_pmu_pebs_data_source_cmt(void)191 void __init intel_pmu_pebs_data_source_cmt(void)
192 {
193 __intel_pmu_pebs_data_source_cmt(pebs_data_source);
194 }
195
196 /* Version for Lion Cove and later */
197 static u64 lnc_pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX] = {
198 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA), /* 0x00: ukn L3 */
199 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 hit */
200 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x02: L1 hit */
201 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x03: LFB/L1 Miss Handling Buffer hit */
202 0, /* 0x04: Reserved */
203 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x05: L2 Hit */
204 OP_LH | LEVEL(L2_MHB) | P(SNOOP, NONE), /* 0x06: L2 Miss Handling Buffer Hit */
205 0, /* 0x07: Reserved */
206 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x08: L3 Hit */
207 0, /* 0x09: Reserved */
208 0, /* 0x0a: Reserved */
209 0, /* 0x0b: Reserved */
210 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD), /* 0x0c: L3 Hit Snoop Fwd */
211 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x0d: L3 Hit Snoop HitM */
212 0, /* 0x0e: Reserved */
213 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x0f: L3 Miss Snoop HitM */
214 OP_LH | LEVEL(MSC) | P(SNOOP, NONE), /* 0x10: Memory-side Cache Hit */
215 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, NONE), /* 0x11: Local Memory Hit */
216 };
217
intel_pmu_pebs_data_source_lnl(void)218 void __init intel_pmu_pebs_data_source_lnl(void)
219 {
220 u64 *data_source;
221
222 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source;
223 memcpy(data_source, lnc_pebs_data_source, sizeof(lnc_pebs_data_source));
224
225 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;
226 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
227 __intel_pmu_pebs_data_source_cmt(data_source);
228 }
229
precise_store_data(u64 status)230 static u64 precise_store_data(u64 status)
231 {
232 union intel_x86_pebs_dse dse;
233 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
234
235 dse.val = status;
236
237 /*
238 * bit 4: TLB access
239 * 1 = stored missed 2nd level TLB
240 *
241 * so it either hit the walker or the OS
242 * otherwise hit 2nd level TLB
243 */
244 if (dse.st_stlb_miss)
245 val |= P(TLB, MISS);
246 else
247 val |= P(TLB, HIT);
248
249 /*
250 * bit 0: hit L1 data cache
251 * if not set, then all we know is that
252 * it missed L1D
253 */
254 if (dse.st_l1d_hit)
255 val |= P(LVL, HIT);
256 else
257 val |= P(LVL, MISS);
258
259 /*
260 * bit 5: Locked prefix
261 */
262 if (dse.st_locked)
263 val |= P(LOCK, LOCKED);
264
265 return val;
266 }
267
precise_datala_hsw(struct perf_event * event,u64 status)268 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
269 {
270 union perf_mem_data_src dse;
271
272 dse.val = PERF_MEM_NA;
273
274 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
275 dse.mem_op = PERF_MEM_OP_STORE;
276 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
277 dse.mem_op = PERF_MEM_OP_LOAD;
278
279 /*
280 * L1 info only valid for following events:
281 *
282 * MEM_UOPS_RETIRED.STLB_MISS_STORES
283 * MEM_UOPS_RETIRED.LOCK_STORES
284 * MEM_UOPS_RETIRED.SPLIT_STORES
285 * MEM_UOPS_RETIRED.ALL_STORES
286 */
287 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
288 if (status & 1)
289 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
290 else
291 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
292 }
293 return dse.val;
294 }
295
pebs_set_tlb_lock(u64 * val,bool tlb,bool lock)296 static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock)
297 {
298 /*
299 * TLB access
300 * 0 = did not miss 2nd level TLB
301 * 1 = missed 2nd level TLB
302 */
303 if (tlb)
304 *val |= P(TLB, MISS) | P(TLB, L2);
305 else
306 *val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
307
308 /* locked prefix */
309 if (lock)
310 *val |= P(LOCK, LOCKED);
311 }
312
313 /* Retrieve the latency data for e-core of ADL */
__grt_latency_data(struct perf_event * event,u64 status,u8 dse,bool tlb,bool lock,bool blk)314 static u64 __grt_latency_data(struct perf_event *event, u64 status,
315 u8 dse, bool tlb, bool lock, bool blk)
316 {
317 u64 val;
318
319 WARN_ON_ONCE(hybrid_pmu(event->pmu)->pmu_type == hybrid_big);
320
321 dse &= PERF_PEBS_DATA_SOURCE_GRT_MASK;
322 val = hybrid_var(event->pmu, pebs_data_source)[dse];
323
324 pebs_set_tlb_lock(&val, tlb, lock);
325
326 if (blk)
327 val |= P(BLK, DATA);
328 else
329 val |= P(BLK, NA);
330
331 return val;
332 }
333
grt_latency_data(struct perf_event * event,u64 status)334 u64 grt_latency_data(struct perf_event *event, u64 status)
335 {
336 union intel_x86_pebs_dse dse;
337
338 dse.val = status;
339
340 return __grt_latency_data(event, status, dse.ld_dse,
341 dse.ld_locked, dse.ld_stlb_miss,
342 dse.ld_data_blk);
343 }
344
345 /* Retrieve the latency data for e-core of MTL */
cmt_latency_data(struct perf_event * event,u64 status)346 u64 cmt_latency_data(struct perf_event *event, u64 status)
347 {
348 union intel_x86_pebs_dse dse;
349
350 dse.val = status;
351
352 return __grt_latency_data(event, status, dse.mtl_dse,
353 dse.mtl_stlb_miss, dse.mtl_locked,
354 dse.mtl_fwd_blk);
355 }
356
lnc_latency_data(struct perf_event * event,u64 status)357 static u64 lnc_latency_data(struct perf_event *event, u64 status)
358 {
359 union intel_x86_pebs_dse dse;
360 union perf_mem_data_src src;
361 u64 val;
362
363 dse.val = status;
364
365 /* LNC core latency data */
366 val = hybrid_var(event->pmu, pebs_data_source)[status & PERF_PEBS_DATA_SOURCE_MASK];
367 if (!val)
368 val = P(OP, LOAD) | LEVEL(NA) | P(SNOOP, NA);
369
370 if (dse.lnc_stlb_miss)
371 val |= P(TLB, MISS) | P(TLB, L2);
372 else
373 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
374
375 if (dse.lnc_locked)
376 val |= P(LOCK, LOCKED);
377
378 if (dse.lnc_data_blk)
379 val |= P(BLK, DATA);
380 if (dse.lnc_addr_blk)
381 val |= P(BLK, ADDR);
382 if (!dse.lnc_data_blk && !dse.lnc_addr_blk)
383 val |= P(BLK, NA);
384
385 src.val = val;
386 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
387 src.mem_op = P(OP, STORE);
388
389 return src.val;
390 }
391
lnl_latency_data(struct perf_event * event,u64 status)392 u64 lnl_latency_data(struct perf_event *event, u64 status)
393 {
394 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
395
396 if (pmu->pmu_type == hybrid_small)
397 return cmt_latency_data(event, status);
398
399 return lnc_latency_data(event, status);
400 }
401
arl_h_latency_data(struct perf_event * event,u64 status)402 u64 arl_h_latency_data(struct perf_event *event, u64 status)
403 {
404 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
405
406 if (pmu->pmu_type == hybrid_tiny)
407 return cmt_latency_data(event, status);
408
409 return lnl_latency_data(event, status);
410 }
411
load_latency_data(struct perf_event * event,u64 status)412 static u64 load_latency_data(struct perf_event *event, u64 status)
413 {
414 union intel_x86_pebs_dse dse;
415 u64 val;
416
417 dse.val = status;
418
419 /*
420 * use the mapping table for bit 0-3
421 */
422 val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse];
423
424 /*
425 * Nehalem models do not support TLB, Lock infos
426 */
427 if (x86_pmu.pebs_no_tlb) {
428 val |= P(TLB, NA) | P(LOCK, NA);
429 return val;
430 }
431
432 pebs_set_tlb_lock(&val, dse.ld_stlb_miss, dse.ld_locked);
433
434 /*
435 * Ice Lake and earlier models do not support block infos.
436 */
437 if (!x86_pmu.pebs_block) {
438 val |= P(BLK, NA);
439 return val;
440 }
441 /*
442 * bit 6: load was blocked since its data could not be forwarded
443 * from a preceding store
444 */
445 if (dse.ld_data_blk)
446 val |= P(BLK, DATA);
447
448 /*
449 * bit 7: load was blocked due to potential address conflict with
450 * a preceding store
451 */
452 if (dse.ld_addr_blk)
453 val |= P(BLK, ADDR);
454
455 if (!dse.ld_data_blk && !dse.ld_addr_blk)
456 val |= P(BLK, NA);
457
458 return val;
459 }
460
store_latency_data(struct perf_event * event,u64 status)461 static u64 store_latency_data(struct perf_event *event, u64 status)
462 {
463 union intel_x86_pebs_dse dse;
464 union perf_mem_data_src src;
465 u64 val;
466
467 dse.val = status;
468
469 /*
470 * use the mapping table for bit 0-3
471 */
472 val = hybrid_var(event->pmu, pebs_data_source)[dse.st_lat_dse];
473
474 pebs_set_tlb_lock(&val, dse.st_lat_stlb_miss, dse.st_lat_locked);
475
476 val |= P(BLK, NA);
477
478 /*
479 * the pebs_data_source table is only for loads
480 * so override the mem_op to say STORE instead
481 */
482 src.val = val;
483 src.mem_op = P(OP,STORE);
484
485 return src.val;
486 }
487
488 struct pebs_record_core {
489 u64 flags, ip;
490 u64 ax, bx, cx, dx;
491 u64 si, di, bp, sp;
492 u64 r8, r9, r10, r11;
493 u64 r12, r13, r14, r15;
494 };
495
496 struct pebs_record_nhm {
497 u64 flags, ip;
498 u64 ax, bx, cx, dx;
499 u64 si, di, bp, sp;
500 u64 r8, r9, r10, r11;
501 u64 r12, r13, r14, r15;
502 u64 status, dla, dse, lat;
503 };
504
505 /*
506 * Same as pebs_record_nhm, with two additional fields.
507 */
508 struct pebs_record_hsw {
509 u64 flags, ip;
510 u64 ax, bx, cx, dx;
511 u64 si, di, bp, sp;
512 u64 r8, r9, r10, r11;
513 u64 r12, r13, r14, r15;
514 u64 status, dla, dse, lat;
515 u64 real_ip, tsx_tuning;
516 };
517
518 union hsw_tsx_tuning {
519 struct {
520 u32 cycles_last_block : 32,
521 hle_abort : 1,
522 rtm_abort : 1,
523 instruction_abort : 1,
524 non_instruction_abort : 1,
525 retry : 1,
526 data_conflict : 1,
527 capacity_writes : 1,
528 capacity_reads : 1;
529 };
530 u64 value;
531 };
532
533 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
534
535 /* Same as HSW, plus TSC */
536
537 struct pebs_record_skl {
538 u64 flags, ip;
539 u64 ax, bx, cx, dx;
540 u64 si, di, bp, sp;
541 u64 r8, r9, r10, r11;
542 u64 r12, r13, r14, r15;
543 u64 status, dla, dse, lat;
544 u64 real_ip, tsx_tuning;
545 u64 tsc;
546 };
547
init_debug_store_on_cpu(int cpu)548 void init_debug_store_on_cpu(int cpu)
549 {
550 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
551
552 if (!ds)
553 return;
554
555 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
556 (u32)((u64)(unsigned long)ds),
557 (u32)((u64)(unsigned long)ds >> 32));
558 }
559
fini_debug_store_on_cpu(int cpu)560 void fini_debug_store_on_cpu(int cpu)
561 {
562 if (!per_cpu(cpu_hw_events, cpu).ds)
563 return;
564
565 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
566 }
567
568 static DEFINE_PER_CPU(void *, insn_buffer);
569
ds_update_cea(void * cea,void * addr,size_t size,pgprot_t prot)570 static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot)
571 {
572 unsigned long start = (unsigned long)cea;
573 phys_addr_t pa;
574 size_t msz = 0;
575
576 pa = virt_to_phys(addr);
577
578 preempt_disable();
579 for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE)
580 cea_set_pte(cea, pa, prot);
581
582 /*
583 * This is a cross-CPU update of the cpu_entry_area, we must shoot down
584 * all TLB entries for it.
585 */
586 flush_tlb_kernel_range(start, start + size);
587 preempt_enable();
588 }
589
ds_clear_cea(void * cea,size_t size)590 static void ds_clear_cea(void *cea, size_t size)
591 {
592 unsigned long start = (unsigned long)cea;
593 size_t msz = 0;
594
595 preempt_disable();
596 for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE)
597 cea_set_pte(cea, 0, PAGE_NONE);
598
599 flush_tlb_kernel_range(start, start + size);
600 preempt_enable();
601 }
602
dsalloc_pages(size_t size,gfp_t flags,int cpu)603 static void *dsalloc_pages(size_t size, gfp_t flags, int cpu)
604 {
605 unsigned int order = get_order(size);
606 int node = cpu_to_node(cpu);
607 struct page *page;
608
609 page = __alloc_pages_node(node, flags | __GFP_ZERO, order);
610 return page ? page_address(page) : NULL;
611 }
612
dsfree_pages(const void * buffer,size_t size)613 static void dsfree_pages(const void *buffer, size_t size)
614 {
615 if (buffer)
616 free_pages((unsigned long)buffer, get_order(size));
617 }
618
alloc_pebs_buffer(int cpu)619 static int alloc_pebs_buffer(int cpu)
620 {
621 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
622 struct debug_store *ds = hwev->ds;
623 size_t bsiz = x86_pmu.pebs_buffer_size;
624 int max, node = cpu_to_node(cpu);
625 void *buffer, *insn_buff, *cea;
626
627 if (!x86_pmu.pebs)
628 return 0;
629
630 buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
631 if (unlikely(!buffer))
632 return -ENOMEM;
633
634 /*
635 * HSW+ already provides us the eventing ip; no need to allocate this
636 * buffer then.
637 */
638 if (x86_pmu.intel_cap.pebs_format < 2) {
639 insn_buff = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
640 if (!insn_buff) {
641 dsfree_pages(buffer, bsiz);
642 return -ENOMEM;
643 }
644 per_cpu(insn_buffer, cpu) = insn_buff;
645 }
646 hwev->ds_pebs_vaddr = buffer;
647 /* Update the cpu entry area mapping */
648 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
649 ds->pebs_buffer_base = (unsigned long) cea;
650 ds_update_cea(cea, buffer, bsiz, PAGE_KERNEL);
651 ds->pebs_index = ds->pebs_buffer_base;
652 max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size);
653 ds->pebs_absolute_maximum = ds->pebs_buffer_base + max;
654 return 0;
655 }
656
release_pebs_buffer(int cpu)657 static void release_pebs_buffer(int cpu)
658 {
659 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
660 void *cea;
661
662 if (!x86_pmu.pebs)
663 return;
664
665 kfree(per_cpu(insn_buffer, cpu));
666 per_cpu(insn_buffer, cpu) = NULL;
667
668 /* Clear the fixmap */
669 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
670 ds_clear_cea(cea, x86_pmu.pebs_buffer_size);
671 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size);
672 hwev->ds_pebs_vaddr = NULL;
673 }
674
alloc_bts_buffer(int cpu)675 static int alloc_bts_buffer(int cpu)
676 {
677 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
678 struct debug_store *ds = hwev->ds;
679 void *buffer, *cea;
680 int max;
681
682 if (!x86_pmu.bts)
683 return 0;
684
685 buffer = dsalloc_pages(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, cpu);
686 if (unlikely(!buffer)) {
687 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
688 return -ENOMEM;
689 }
690 hwev->ds_bts_vaddr = buffer;
691 /* Update the fixmap */
692 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
693 ds->bts_buffer_base = (unsigned long) cea;
694 ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL);
695 ds->bts_index = ds->bts_buffer_base;
696 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
697 ds->bts_absolute_maximum = ds->bts_buffer_base +
698 max * BTS_RECORD_SIZE;
699 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
700 (max / 16) * BTS_RECORD_SIZE;
701 return 0;
702 }
703
release_bts_buffer(int cpu)704 static void release_bts_buffer(int cpu)
705 {
706 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
707 void *cea;
708
709 if (!x86_pmu.bts)
710 return;
711
712 /* Clear the fixmap */
713 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
714 ds_clear_cea(cea, BTS_BUFFER_SIZE);
715 dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE);
716 hwev->ds_bts_vaddr = NULL;
717 }
718
alloc_ds_buffer(int cpu)719 static int alloc_ds_buffer(int cpu)
720 {
721 struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store;
722
723 memset(ds, 0, sizeof(*ds));
724 per_cpu(cpu_hw_events, cpu).ds = ds;
725 return 0;
726 }
727
release_ds_buffer(int cpu)728 static void release_ds_buffer(int cpu)
729 {
730 per_cpu(cpu_hw_events, cpu).ds = NULL;
731 }
732
release_ds_buffers(void)733 void release_ds_buffers(void)
734 {
735 int cpu;
736
737 if (!x86_pmu.bts && !x86_pmu.pebs)
738 return;
739
740 for_each_possible_cpu(cpu)
741 release_ds_buffer(cpu);
742
743 for_each_possible_cpu(cpu) {
744 /*
745 * Again, ignore errors from offline CPUs, they will no longer
746 * observe cpu_hw_events.ds and not program the DS_AREA when
747 * they come up.
748 */
749 fini_debug_store_on_cpu(cpu);
750 }
751
752 for_each_possible_cpu(cpu) {
753 release_pebs_buffer(cpu);
754 release_bts_buffer(cpu);
755 }
756 }
757
reserve_ds_buffers(void)758 void reserve_ds_buffers(void)
759 {
760 int bts_err = 0, pebs_err = 0;
761 int cpu;
762
763 x86_pmu.bts_active = 0;
764 x86_pmu.pebs_active = 0;
765
766 if (!x86_pmu.bts && !x86_pmu.pebs)
767 return;
768
769 if (!x86_pmu.bts)
770 bts_err = 1;
771
772 if (!x86_pmu.pebs)
773 pebs_err = 1;
774
775 for_each_possible_cpu(cpu) {
776 if (alloc_ds_buffer(cpu)) {
777 bts_err = 1;
778 pebs_err = 1;
779 }
780
781 if (!bts_err && alloc_bts_buffer(cpu))
782 bts_err = 1;
783
784 if (!pebs_err && alloc_pebs_buffer(cpu))
785 pebs_err = 1;
786
787 if (bts_err && pebs_err)
788 break;
789 }
790
791 if (bts_err) {
792 for_each_possible_cpu(cpu)
793 release_bts_buffer(cpu);
794 }
795
796 if (pebs_err) {
797 for_each_possible_cpu(cpu)
798 release_pebs_buffer(cpu);
799 }
800
801 if (bts_err && pebs_err) {
802 for_each_possible_cpu(cpu)
803 release_ds_buffer(cpu);
804 } else {
805 if (x86_pmu.bts && !bts_err)
806 x86_pmu.bts_active = 1;
807
808 if (x86_pmu.pebs && !pebs_err)
809 x86_pmu.pebs_active = 1;
810
811 for_each_possible_cpu(cpu) {
812 /*
813 * Ignores wrmsr_on_cpu() errors for offline CPUs they
814 * will get this call through intel_pmu_cpu_starting().
815 */
816 init_debug_store_on_cpu(cpu);
817 }
818 }
819 }
820
821 /*
822 * BTS
823 */
824
825 struct event_constraint bts_constraint =
826 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
827
intel_pmu_enable_bts(u64 config)828 void intel_pmu_enable_bts(u64 config)
829 {
830 unsigned long debugctlmsr;
831
832 debugctlmsr = get_debugctlmsr();
833
834 debugctlmsr |= DEBUGCTLMSR_TR;
835 debugctlmsr |= DEBUGCTLMSR_BTS;
836 if (config & ARCH_PERFMON_EVENTSEL_INT)
837 debugctlmsr |= DEBUGCTLMSR_BTINT;
838
839 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
840 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
841
842 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
843 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
844
845 update_debugctlmsr(debugctlmsr);
846 }
847
intel_pmu_disable_bts(void)848 void intel_pmu_disable_bts(void)
849 {
850 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
851 unsigned long debugctlmsr;
852
853 if (!cpuc->ds)
854 return;
855
856 debugctlmsr = get_debugctlmsr();
857
858 debugctlmsr &=
859 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
860 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
861
862 update_debugctlmsr(debugctlmsr);
863 }
864
intel_pmu_drain_bts_buffer(void)865 int intel_pmu_drain_bts_buffer(void)
866 {
867 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
868 struct debug_store *ds = cpuc->ds;
869 struct bts_record {
870 u64 from;
871 u64 to;
872 u64 flags;
873 };
874 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
875 struct bts_record *at, *base, *top;
876 struct perf_output_handle handle;
877 struct perf_event_header header;
878 struct perf_sample_data data;
879 unsigned long skip = 0;
880 struct pt_regs regs;
881
882 if (!event)
883 return 0;
884
885 if (!x86_pmu.bts_active)
886 return 0;
887
888 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
889 top = (struct bts_record *)(unsigned long)ds->bts_index;
890
891 if (top <= base)
892 return 0;
893
894 memset(®s, 0, sizeof(regs));
895
896 ds->bts_index = ds->bts_buffer_base;
897
898 perf_sample_data_init(&data, 0, event->hw.last_period);
899
900 /*
901 * BTS leaks kernel addresses in branches across the cpl boundary,
902 * such as traps or system calls, so unless the user is asking for
903 * kernel tracing (and right now it's not possible), we'd need to
904 * filter them out. But first we need to count how many of those we
905 * have in the current batch. This is an extra O(n) pass, however,
906 * it's much faster than the other one especially considering that
907 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
908 * alloc_bts_buffer()).
909 */
910 for (at = base; at < top; at++) {
911 /*
912 * Note that right now *this* BTS code only works if
913 * attr::exclude_kernel is set, but let's keep this extra
914 * check here in case that changes.
915 */
916 if (event->attr.exclude_kernel &&
917 (kernel_ip(at->from) || kernel_ip(at->to)))
918 skip++;
919 }
920
921 /*
922 * Prepare a generic sample, i.e. fill in the invariant fields.
923 * We will overwrite the from and to address before we output
924 * the sample.
925 */
926 rcu_read_lock();
927 perf_prepare_sample(&data, event, ®s);
928 perf_prepare_header(&header, &data, event, ®s);
929
930 if (perf_output_begin(&handle, &data, event,
931 header.size * (top - base - skip)))
932 goto unlock;
933
934 for (at = base; at < top; at++) {
935 /* Filter out any records that contain kernel addresses. */
936 if (event->attr.exclude_kernel &&
937 (kernel_ip(at->from) || kernel_ip(at->to)))
938 continue;
939
940 data.ip = at->from;
941 data.addr = at->to;
942
943 perf_output_sample(&handle, &header, &data, event);
944 }
945
946 perf_output_end(&handle);
947
948 /* There's new data available. */
949 event->hw.interrupts++;
950 event->pending_kill = POLL_IN;
951 unlock:
952 rcu_read_unlock();
953 return 1;
954 }
955
intel_pmu_drain_pebs_buffer(void)956 void intel_pmu_drain_pebs_buffer(void)
957 {
958 struct perf_sample_data data;
959
960 static_call(x86_pmu_drain_pebs)(NULL, &data);
961 }
962
963 /*
964 * PEBS
965 */
966 struct event_constraint intel_core2_pebs_event_constraints[] = {
967 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
968 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
969 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
970 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
971 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
972 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
973 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
974 EVENT_CONSTRAINT_END
975 };
976
977 struct event_constraint intel_atom_pebs_event_constraints[] = {
978 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
979 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
980 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
981 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
982 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
983 /* Allow all events as PEBS with no flags */
984 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
985 EVENT_CONSTRAINT_END
986 };
987
988 struct event_constraint intel_slm_pebs_event_constraints[] = {
989 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
990 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x1),
991 /* Allow all events as PEBS with no flags */
992 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
993 EVENT_CONSTRAINT_END
994 };
995
996 struct event_constraint intel_glm_pebs_event_constraints[] = {
997 /* Allow all events as PEBS with no flags */
998 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
999 EVENT_CONSTRAINT_END
1000 };
1001
1002 struct event_constraint intel_grt_pebs_event_constraints[] = {
1003 /* Allow all events as PEBS with no flags */
1004 INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
1005 INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xf),
1006 EVENT_CONSTRAINT_END
1007 };
1008
1009 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
1010 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
1011 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
1012 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
1013 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
1014 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
1015 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
1016 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
1017 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
1018 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
1019 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
1020 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
1021 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
1022 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
1023 EVENT_CONSTRAINT_END
1024 };
1025
1026 struct event_constraint intel_westmere_pebs_event_constraints[] = {
1027 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
1028 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
1029 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
1030 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
1031 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
1032 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
1033 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
1034 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
1035 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
1036 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
1037 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
1038 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
1039 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
1040 EVENT_CONSTRAINT_END
1041 };
1042
1043 struct event_constraint intel_snb_pebs_event_constraints[] = {
1044 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
1045 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
1046 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
1047 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
1048 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
1049 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
1050 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
1051 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
1052 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
1053 /* Allow all events as PEBS with no flags */
1054 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
1055 EVENT_CONSTRAINT_END
1056 };
1057
1058 struct event_constraint intel_ivb_pebs_event_constraints[] = {
1059 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
1060 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
1061 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
1062 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
1063 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
1064 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
1065 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
1066 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
1067 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
1068 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
1069 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
1070 /* Allow all events as PEBS with no flags */
1071 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
1072 EVENT_CONSTRAINT_END
1073 };
1074
1075 struct event_constraint intel_hsw_pebs_event_constraints[] = {
1076 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
1077 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
1078 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
1079 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
1080 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
1081 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
1082 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
1083 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
1084 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
1085 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
1086 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
1087 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
1088 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
1089 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
1090 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
1091 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
1092 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
1093 /* Allow all events as PEBS with no flags */
1094 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
1095 EVENT_CONSTRAINT_END
1096 };
1097
1098 struct event_constraint intel_bdw_pebs_event_constraints[] = {
1099 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
1100 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
1101 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
1102 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
1103 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
1104 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
1105 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
1106 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
1107 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
1108 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
1109 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
1110 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
1111 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
1112 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
1113 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
1114 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
1115 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
1116 /* Allow all events as PEBS with no flags */
1117 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
1118 EVENT_CONSTRAINT_END
1119 };
1120
1121
1122 struct event_constraint intel_skl_pebs_event_constraints[] = {
1123 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
1124 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
1125 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
1126 /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
1127 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
1128 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
1129 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
1130 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
1131 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
1132 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
1133 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
1134 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
1135 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
1136 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
1137 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
1138 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
1139 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
1140 /* Allow all events as PEBS with no flags */
1141 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
1142 EVENT_CONSTRAINT_END
1143 };
1144
1145 struct event_constraint intel_icl_pebs_event_constraints[] = {
1146 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x100000000ULL), /* old INST_RETIRED.PREC_DIST */
1147 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
1148 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), /* SLOTS */
1149
1150 INTEL_PLD_CONSTRAINT(0x1cd, 0xff), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
1151 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
1152 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
1153 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
1154 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
1155 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
1156 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
1157 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
1158
1159 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), /* MEM_LOAD_*_RETIRED.* */
1160
1161 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
1162
1163 /*
1164 * Everything else is handled by PMU_FL_PEBS_ALL, because we
1165 * need the full constraints from the main table.
1166 */
1167
1168 EVENT_CONSTRAINT_END
1169 };
1170
1171 struct event_constraint intel_glc_pebs_event_constraints[] = {
1172 INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
1173 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
1174
1175 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe),
1176 INTEL_PLD_CONSTRAINT(0x1cd, 0xfe),
1177 INTEL_PSD_CONSTRAINT(0x2cd, 0x1),
1178 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
1179 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
1180 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
1181 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
1182 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
1183 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
1184 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
1185
1186 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
1187
1188 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),
1189
1190 /*
1191 * Everything else is handled by PMU_FL_PEBS_ALL, because we
1192 * need the full constraints from the main table.
1193 */
1194
1195 EVENT_CONSTRAINT_END
1196 };
1197
1198 struct event_constraint intel_lnc_pebs_event_constraints[] = {
1199 INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
1200 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
1201
1202 INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0x3fc),
1203 INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3),
1204 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
1205 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
1206 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
1207 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
1208 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
1209 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
1210 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
1211
1212 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
1213
1214 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),
1215
1216 /*
1217 * Everything else is handled by PMU_FL_PEBS_ALL, because we
1218 * need the full constraints from the main table.
1219 */
1220
1221 EVENT_CONSTRAINT_END
1222 };
1223
intel_pebs_constraints(struct perf_event * event)1224 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
1225 {
1226 struct event_constraint *pebs_constraints = hybrid(event->pmu, pebs_constraints);
1227 struct event_constraint *c;
1228
1229 if (!event->attr.precise_ip)
1230 return NULL;
1231
1232 if (pebs_constraints) {
1233 for_each_event_constraint(c, pebs_constraints) {
1234 if (constraint_match(c, event->hw.config)) {
1235 event->hw.flags |= c->flags;
1236 return c;
1237 }
1238 }
1239 }
1240
1241 /*
1242 * Extended PEBS support
1243 * Makes the PEBS code search the normal constraints.
1244 */
1245 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
1246 return NULL;
1247
1248 return &emptyconstraint;
1249 }
1250
1251 /*
1252 * We need the sched_task callback even for per-cpu events when we use
1253 * the large interrupt threshold, such that we can provide PID and TID
1254 * to PEBS samples.
1255 */
pebs_needs_sched_cb(struct cpu_hw_events * cpuc)1256 static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc)
1257 {
1258 if (cpuc->n_pebs == cpuc->n_pebs_via_pt)
1259 return false;
1260
1261 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs);
1262 }
1263
intel_pmu_pebs_sched_task(struct perf_event_pmu_context * pmu_ctx,bool sched_in)1264 void intel_pmu_pebs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in)
1265 {
1266 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1267
1268 if (!sched_in && pebs_needs_sched_cb(cpuc))
1269 intel_pmu_drain_pebs_buffer();
1270 }
1271
pebs_update_threshold(struct cpu_hw_events * cpuc)1272 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
1273 {
1274 struct debug_store *ds = cpuc->ds;
1275 int max_pebs_events = intel_pmu_max_num_pebs(cpuc->pmu);
1276 u64 threshold;
1277 int reserved;
1278
1279 if (cpuc->n_pebs_via_pt)
1280 return;
1281
1282 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
1283 reserved = max_pebs_events + x86_pmu_max_num_counters_fixed(cpuc->pmu);
1284 else
1285 reserved = max_pebs_events;
1286
1287 if (cpuc->n_pebs == cpuc->n_large_pebs) {
1288 threshold = ds->pebs_absolute_maximum -
1289 reserved * cpuc->pebs_record_size;
1290 } else {
1291 threshold = ds->pebs_buffer_base + cpuc->pebs_record_size;
1292 }
1293
1294 ds->pebs_interrupt_threshold = threshold;
1295 }
1296
adaptive_pebs_record_size_update(void)1297 static void adaptive_pebs_record_size_update(void)
1298 {
1299 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1300 u64 pebs_data_cfg = cpuc->pebs_data_cfg;
1301 int sz = sizeof(struct pebs_basic);
1302
1303 if (pebs_data_cfg & PEBS_DATACFG_MEMINFO)
1304 sz += sizeof(struct pebs_meminfo);
1305 if (pebs_data_cfg & PEBS_DATACFG_GP)
1306 sz += sizeof(struct pebs_gprs);
1307 if (pebs_data_cfg & PEBS_DATACFG_XMMS)
1308 sz += sizeof(struct pebs_xmm);
1309 if (pebs_data_cfg & PEBS_DATACFG_LBRS)
1310 sz += x86_pmu.lbr_nr * sizeof(struct lbr_entry);
1311
1312 cpuc->pebs_record_size = sz;
1313 }
1314
1315 #define PERF_PEBS_MEMINFO_TYPE (PERF_SAMPLE_ADDR | PERF_SAMPLE_DATA_SRC | \
1316 PERF_SAMPLE_PHYS_ADDR | \
1317 PERF_SAMPLE_WEIGHT_TYPE | \
1318 PERF_SAMPLE_TRANSACTION | \
1319 PERF_SAMPLE_DATA_PAGE_SIZE)
1320
pebs_update_adaptive_cfg(struct perf_event * event)1321 static u64 pebs_update_adaptive_cfg(struct perf_event *event)
1322 {
1323 struct perf_event_attr *attr = &event->attr;
1324 u64 sample_type = attr->sample_type;
1325 u64 pebs_data_cfg = 0;
1326 bool gprs, tsx_weight;
1327
1328 if (!(sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) &&
1329 attr->precise_ip > 1)
1330 return pebs_data_cfg;
1331
1332 if (sample_type & PERF_PEBS_MEMINFO_TYPE)
1333 pebs_data_cfg |= PEBS_DATACFG_MEMINFO;
1334
1335 /*
1336 * We need GPRs when:
1337 * + user requested them
1338 * + precise_ip < 2 for the non event IP
1339 * + For RTM TSX weight we need GPRs for the abort code.
1340 */
1341 gprs = ((sample_type & PERF_SAMPLE_REGS_INTR) &&
1342 (attr->sample_regs_intr & PEBS_GP_REGS)) ||
1343 ((sample_type & PERF_SAMPLE_REGS_USER) &&
1344 (attr->sample_regs_user & PEBS_GP_REGS));
1345
1346 tsx_weight = (sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
1347 ((attr->config & INTEL_ARCH_EVENT_MASK) ==
1348 x86_pmu.rtm_abort_event);
1349
1350 if (gprs || (attr->precise_ip < 2) || tsx_weight)
1351 pebs_data_cfg |= PEBS_DATACFG_GP;
1352
1353 if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
1354 (attr->sample_regs_intr & PERF_REG_EXTENDED_MASK))
1355 pebs_data_cfg |= PEBS_DATACFG_XMMS;
1356
1357 if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
1358 /*
1359 * For now always log all LBRs. Could configure this
1360 * later.
1361 */
1362 pebs_data_cfg |= PEBS_DATACFG_LBRS |
1363 ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT);
1364 }
1365
1366 return pebs_data_cfg;
1367 }
1368
1369 static void
pebs_update_state(bool needed_cb,struct cpu_hw_events * cpuc,struct perf_event * event,bool add)1370 pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc,
1371 struct perf_event *event, bool add)
1372 {
1373 struct pmu *pmu = event->pmu;
1374
1375 /*
1376 * Make sure we get updated with the first PEBS event.
1377 * During removal, ->pebs_data_cfg is still valid for
1378 * the last PEBS event. Don't clear it.
1379 */
1380 if ((cpuc->n_pebs == 1) && add)
1381 cpuc->pebs_data_cfg = PEBS_UPDATE_DS_SW;
1382
1383 if (needed_cb != pebs_needs_sched_cb(cpuc)) {
1384 if (!needed_cb)
1385 perf_sched_cb_inc(pmu);
1386 else
1387 perf_sched_cb_dec(pmu);
1388
1389 cpuc->pebs_data_cfg |= PEBS_UPDATE_DS_SW;
1390 }
1391
1392 /*
1393 * The PEBS record doesn't shrink on pmu::del(). Doing so would require
1394 * iterating all remaining PEBS events to reconstruct the config.
1395 */
1396 if (x86_pmu.intel_cap.pebs_baseline && add) {
1397 u64 pebs_data_cfg;
1398
1399 pebs_data_cfg = pebs_update_adaptive_cfg(event);
1400 /*
1401 * Be sure to update the thresholds when we change the record.
1402 */
1403 if (pebs_data_cfg & ~cpuc->pebs_data_cfg)
1404 cpuc->pebs_data_cfg |= pebs_data_cfg | PEBS_UPDATE_DS_SW;
1405 }
1406 }
1407
intel_pmu_pebs_add(struct perf_event * event)1408 void intel_pmu_pebs_add(struct perf_event *event)
1409 {
1410 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1411 struct hw_perf_event *hwc = &event->hw;
1412 bool needed_cb = pebs_needs_sched_cb(cpuc);
1413
1414 cpuc->n_pebs++;
1415 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
1416 cpuc->n_large_pebs++;
1417 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1418 cpuc->n_pebs_via_pt++;
1419
1420 pebs_update_state(needed_cb, cpuc, event, true);
1421 }
1422
intel_pmu_pebs_via_pt_disable(struct perf_event * event)1423 static void intel_pmu_pebs_via_pt_disable(struct perf_event *event)
1424 {
1425 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1426
1427 if (!is_pebs_pt(event))
1428 return;
1429
1430 if (!(cpuc->pebs_enabled & ~PEBS_VIA_PT_MASK))
1431 cpuc->pebs_enabled &= ~PEBS_VIA_PT_MASK;
1432 }
1433
intel_pmu_pebs_via_pt_enable(struct perf_event * event)1434 static void intel_pmu_pebs_via_pt_enable(struct perf_event *event)
1435 {
1436 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1437 struct hw_perf_event *hwc = &event->hw;
1438 struct debug_store *ds = cpuc->ds;
1439 u64 value = ds->pebs_event_reset[hwc->idx];
1440 u32 base = MSR_RELOAD_PMC0;
1441 unsigned int idx = hwc->idx;
1442
1443 if (!is_pebs_pt(event))
1444 return;
1445
1446 if (!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
1447 cpuc->pebs_enabled |= PEBS_PMI_AFTER_EACH_RECORD;
1448
1449 cpuc->pebs_enabled |= PEBS_OUTPUT_PT;
1450
1451 if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
1452 base = MSR_RELOAD_FIXED_CTR0;
1453 idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1454 if (x86_pmu.intel_cap.pebs_format < 5)
1455 value = ds->pebs_event_reset[MAX_PEBS_EVENTS_FMT4 + idx];
1456 else
1457 value = ds->pebs_event_reset[MAX_PEBS_EVENTS + idx];
1458 }
1459 wrmsrl(base + idx, value);
1460 }
1461
intel_pmu_drain_large_pebs(struct cpu_hw_events * cpuc)1462 static inline void intel_pmu_drain_large_pebs(struct cpu_hw_events *cpuc)
1463 {
1464 if (cpuc->n_pebs == cpuc->n_large_pebs &&
1465 cpuc->n_pebs != cpuc->n_pebs_via_pt)
1466 intel_pmu_drain_pebs_buffer();
1467 }
1468
intel_pmu_pebs_enable(struct perf_event * event)1469 void intel_pmu_pebs_enable(struct perf_event *event)
1470 {
1471 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1472 u64 pebs_data_cfg = cpuc->pebs_data_cfg & ~PEBS_UPDATE_DS_SW;
1473 struct hw_perf_event *hwc = &event->hw;
1474 struct debug_store *ds = cpuc->ds;
1475 unsigned int idx = hwc->idx;
1476
1477 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
1478
1479 cpuc->pebs_enabled |= 1ULL << hwc->idx;
1480
1481 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5))
1482 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
1483 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
1484 cpuc->pebs_enabled |= 1ULL << 63;
1485
1486 if (x86_pmu.intel_cap.pebs_baseline) {
1487 hwc->config |= ICL_EVENTSEL_ADAPTIVE;
1488 if (pebs_data_cfg != cpuc->active_pebs_data_cfg) {
1489 /*
1490 * drain_pebs() assumes uniform record size;
1491 * hence we need to drain when changing said
1492 * size.
1493 */
1494 intel_pmu_drain_pebs_buffer();
1495 adaptive_pebs_record_size_update();
1496 wrmsrl(MSR_PEBS_DATA_CFG, pebs_data_cfg);
1497 cpuc->active_pebs_data_cfg = pebs_data_cfg;
1498 }
1499 }
1500 if (cpuc->pebs_data_cfg & PEBS_UPDATE_DS_SW) {
1501 cpuc->pebs_data_cfg = pebs_data_cfg;
1502 pebs_update_threshold(cpuc);
1503 }
1504
1505 if (idx >= INTEL_PMC_IDX_FIXED) {
1506 if (x86_pmu.intel_cap.pebs_format < 5)
1507 idx = MAX_PEBS_EVENTS_FMT4 + (idx - INTEL_PMC_IDX_FIXED);
1508 else
1509 idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);
1510 }
1511
1512 /*
1513 * Use auto-reload if possible to save a MSR write in the PMI.
1514 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
1515 */
1516 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
1517 ds->pebs_event_reset[idx] =
1518 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
1519 } else {
1520 ds->pebs_event_reset[idx] = 0;
1521 }
1522
1523 intel_pmu_pebs_via_pt_enable(event);
1524 }
1525
intel_pmu_pebs_del(struct perf_event * event)1526 void intel_pmu_pebs_del(struct perf_event *event)
1527 {
1528 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1529 struct hw_perf_event *hwc = &event->hw;
1530 bool needed_cb = pebs_needs_sched_cb(cpuc);
1531
1532 cpuc->n_pebs--;
1533 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
1534 cpuc->n_large_pebs--;
1535 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1536 cpuc->n_pebs_via_pt--;
1537
1538 pebs_update_state(needed_cb, cpuc, event, false);
1539 }
1540
intel_pmu_pebs_disable(struct perf_event * event)1541 void intel_pmu_pebs_disable(struct perf_event *event)
1542 {
1543 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1544 struct hw_perf_event *hwc = &event->hw;
1545
1546 intel_pmu_drain_large_pebs(cpuc);
1547
1548 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
1549
1550 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) &&
1551 (x86_pmu.version < 5))
1552 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
1553 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
1554 cpuc->pebs_enabled &= ~(1ULL << 63);
1555
1556 intel_pmu_pebs_via_pt_disable(event);
1557
1558 if (cpuc->enabled)
1559 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1560
1561 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
1562 }
1563
intel_pmu_pebs_enable_all(void)1564 void intel_pmu_pebs_enable_all(void)
1565 {
1566 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1567
1568 if (cpuc->pebs_enabled)
1569 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1570 }
1571
intel_pmu_pebs_disable_all(void)1572 void intel_pmu_pebs_disable_all(void)
1573 {
1574 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1575
1576 if (cpuc->pebs_enabled)
1577 __intel_pmu_pebs_disable_all();
1578 }
1579
intel_pmu_pebs_fixup_ip(struct pt_regs * regs)1580 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
1581 {
1582 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1583 unsigned long from = cpuc->lbr_entries[0].from;
1584 unsigned long old_to, to = cpuc->lbr_entries[0].to;
1585 unsigned long ip = regs->ip;
1586 int is_64bit = 0;
1587 void *kaddr;
1588 int size;
1589
1590 /*
1591 * We don't need to fixup if the PEBS assist is fault like
1592 */
1593 if (!x86_pmu.intel_cap.pebs_trap)
1594 return 1;
1595
1596 /*
1597 * No LBR entry, no basic block, no rewinding
1598 */
1599 if (!cpuc->lbr_stack.nr || !from || !to)
1600 return 0;
1601
1602 /*
1603 * Basic blocks should never cross user/kernel boundaries
1604 */
1605 if (kernel_ip(ip) != kernel_ip(to))
1606 return 0;
1607
1608 /*
1609 * unsigned math, either ip is before the start (impossible) or
1610 * the basic block is larger than 1 page (sanity)
1611 */
1612 if ((ip - to) > PEBS_FIXUP_SIZE)
1613 return 0;
1614
1615 /*
1616 * We sampled a branch insn, rewind using the LBR stack
1617 */
1618 if (ip == to) {
1619 set_linear_ip(regs, from);
1620 return 1;
1621 }
1622
1623 size = ip - to;
1624 if (!kernel_ip(ip)) {
1625 int bytes;
1626 u8 *buf = this_cpu_read(insn_buffer);
1627
1628 /* 'size' must fit our buffer, see above */
1629 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
1630 if (bytes != 0)
1631 return 0;
1632
1633 kaddr = buf;
1634 } else {
1635 kaddr = (void *)to;
1636 }
1637
1638 do {
1639 struct insn insn;
1640
1641 old_to = to;
1642
1643 #ifdef CONFIG_X86_64
1644 is_64bit = kernel_ip(to) || any_64bit_mode(regs);
1645 #endif
1646 insn_init(&insn, kaddr, size, is_64bit);
1647
1648 /*
1649 * Make sure there was not a problem decoding the instruction.
1650 * This is doubly important because we have an infinite loop if
1651 * insn.length=0.
1652 */
1653 if (insn_get_length(&insn))
1654 break;
1655
1656 to += insn.length;
1657 kaddr += insn.length;
1658 size -= insn.length;
1659 } while (to < ip);
1660
1661 if (to == ip) {
1662 set_linear_ip(regs, old_to);
1663 return 1;
1664 }
1665
1666 /*
1667 * Even though we decoded the basic block, the instruction stream
1668 * never matched the given IP, either the TO or the IP got corrupted.
1669 */
1670 return 0;
1671 }
1672
intel_get_tsx_weight(u64 tsx_tuning)1673 static inline u64 intel_get_tsx_weight(u64 tsx_tuning)
1674 {
1675 if (tsx_tuning) {
1676 union hsw_tsx_tuning tsx = { .value = tsx_tuning };
1677 return tsx.cycles_last_block;
1678 }
1679 return 0;
1680 }
1681
intel_get_tsx_transaction(u64 tsx_tuning,u64 ax)1682 static inline u64 intel_get_tsx_transaction(u64 tsx_tuning, u64 ax)
1683 {
1684 u64 txn = (tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
1685
1686 /* For RTM XABORTs also log the abort code from AX */
1687 if ((txn & PERF_TXN_TRANSACTION) && (ax & 1))
1688 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1689 return txn;
1690 }
1691
get_pebs_status(void * n)1692 static inline u64 get_pebs_status(void *n)
1693 {
1694 if (x86_pmu.intel_cap.pebs_format < 4)
1695 return ((struct pebs_record_nhm *)n)->status;
1696 return ((struct pebs_basic *)n)->applicable_counters;
1697 }
1698
1699 #define PERF_X86_EVENT_PEBS_HSW_PREC \
1700 (PERF_X86_EVENT_PEBS_ST_HSW | \
1701 PERF_X86_EVENT_PEBS_LD_HSW | \
1702 PERF_X86_EVENT_PEBS_NA_HSW)
1703
get_data_src(struct perf_event * event,u64 aux)1704 static u64 get_data_src(struct perf_event *event, u64 aux)
1705 {
1706 u64 val = PERF_MEM_NA;
1707 int fl = event->hw.flags;
1708 bool fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1709
1710 if (fl & PERF_X86_EVENT_PEBS_LDLAT)
1711 val = load_latency_data(event, aux);
1712 else if (fl & PERF_X86_EVENT_PEBS_STLAT)
1713 val = store_latency_data(event, aux);
1714 else if (fl & PERF_X86_EVENT_PEBS_LAT_HYBRID)
1715 val = x86_pmu.pebs_latency_data(event, aux);
1716 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1717 val = precise_datala_hsw(event, aux);
1718 else if (fst)
1719 val = precise_store_data(aux);
1720 return val;
1721 }
1722
setup_pebs_time(struct perf_event * event,struct perf_sample_data * data,u64 tsc)1723 static void setup_pebs_time(struct perf_event *event,
1724 struct perf_sample_data *data,
1725 u64 tsc)
1726 {
1727 /* Converting to a user-defined clock is not supported yet. */
1728 if (event->attr.use_clockid != 0)
1729 return;
1730
1731 /*
1732 * Doesn't support the conversion when the TSC is unstable.
1733 * The TSC unstable case is a corner case and very unlikely to
1734 * happen. If it happens, the TSC in a PEBS record will be
1735 * dropped and fall back to perf_event_clock().
1736 */
1737 if (!using_native_sched_clock() || !sched_clock_stable())
1738 return;
1739
1740 data->time = native_sched_clock_from_tsc(tsc) + __sched_clock_offset;
1741 data->sample_flags |= PERF_SAMPLE_TIME;
1742 }
1743
1744 #define PERF_SAMPLE_ADDR_TYPE (PERF_SAMPLE_ADDR | \
1745 PERF_SAMPLE_PHYS_ADDR | \
1746 PERF_SAMPLE_DATA_PAGE_SIZE)
1747
setup_pebs_fixed_sample_data(struct perf_event * event,struct pt_regs * iregs,void * __pebs,struct perf_sample_data * data,struct pt_regs * regs)1748 static void setup_pebs_fixed_sample_data(struct perf_event *event,
1749 struct pt_regs *iregs, void *__pebs,
1750 struct perf_sample_data *data,
1751 struct pt_regs *regs)
1752 {
1753 /*
1754 * We cast to the biggest pebs_record but are careful not to
1755 * unconditionally access the 'extra' entries.
1756 */
1757 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1758 struct pebs_record_skl *pebs = __pebs;
1759 u64 sample_type;
1760 int fll;
1761
1762 if (pebs == NULL)
1763 return;
1764
1765 sample_type = event->attr.sample_type;
1766 fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
1767
1768 perf_sample_data_init(data, 0, event->hw.last_period);
1769
1770 data->period = event->hw.last_period;
1771
1772 /*
1773 * Use latency for weight (only avail with PEBS-LL)
1774 */
1775 if (fll && (sample_type & PERF_SAMPLE_WEIGHT_TYPE)) {
1776 data->weight.full = pebs->lat;
1777 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
1778 }
1779
1780 /*
1781 * data.data_src encodes the data source
1782 */
1783 if (sample_type & PERF_SAMPLE_DATA_SRC) {
1784 data->data_src.val = get_data_src(event, pebs->dse);
1785 data->sample_flags |= PERF_SAMPLE_DATA_SRC;
1786 }
1787
1788 /*
1789 * We must however always use iregs for the unwinder to stay sane; the
1790 * record BP,SP,IP can point into thin air when the record is from a
1791 * previous PMI context or an (I)RET happened between the record and
1792 * PMI.
1793 */
1794 perf_sample_save_callchain(data, event, iregs);
1795
1796 /*
1797 * We use the interrupt regs as a base because the PEBS record does not
1798 * contain a full regs set, specifically it seems to lack segment
1799 * descriptors, which get used by things like user_mode().
1800 *
1801 * In the simple case fix up only the IP for PERF_SAMPLE_IP.
1802 */
1803 *regs = *iregs;
1804
1805 /*
1806 * Initialize regs_>flags from PEBS,
1807 * Clear exact bit (which uses x86 EFLAGS Reserved bit 3),
1808 * i.e., do not rely on it being zero:
1809 */
1810 regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT;
1811
1812 if (sample_type & PERF_SAMPLE_REGS_INTR) {
1813 regs->ax = pebs->ax;
1814 regs->bx = pebs->bx;
1815 regs->cx = pebs->cx;
1816 regs->dx = pebs->dx;
1817 regs->si = pebs->si;
1818 regs->di = pebs->di;
1819
1820 regs->bp = pebs->bp;
1821 regs->sp = pebs->sp;
1822
1823 #ifndef CONFIG_X86_32
1824 regs->r8 = pebs->r8;
1825 regs->r9 = pebs->r9;
1826 regs->r10 = pebs->r10;
1827 regs->r11 = pebs->r11;
1828 regs->r12 = pebs->r12;
1829 regs->r13 = pebs->r13;
1830 regs->r14 = pebs->r14;
1831 regs->r15 = pebs->r15;
1832 #endif
1833 }
1834
1835 if (event->attr.precise_ip > 1) {
1836 /*
1837 * Haswell and later processors have an 'eventing IP'
1838 * (real IP) which fixes the off-by-1 skid in hardware.
1839 * Use it when precise_ip >= 2 :
1840 */
1841 if (x86_pmu.intel_cap.pebs_format >= 2) {
1842 set_linear_ip(regs, pebs->real_ip);
1843 regs->flags |= PERF_EFLAGS_EXACT;
1844 } else {
1845 /* Otherwise, use PEBS off-by-1 IP: */
1846 set_linear_ip(regs, pebs->ip);
1847
1848 /*
1849 * With precise_ip >= 2, try to fix up the off-by-1 IP
1850 * using the LBR. If successful, the fixup function
1851 * corrects regs->ip and calls set_linear_ip() on regs:
1852 */
1853 if (intel_pmu_pebs_fixup_ip(regs))
1854 regs->flags |= PERF_EFLAGS_EXACT;
1855 }
1856 } else {
1857 /*
1858 * When precise_ip == 1, return the PEBS off-by-1 IP,
1859 * no fixup attempted:
1860 */
1861 set_linear_ip(regs, pebs->ip);
1862 }
1863
1864
1865 if ((sample_type & PERF_SAMPLE_ADDR_TYPE) &&
1866 x86_pmu.intel_cap.pebs_format >= 1) {
1867 data->addr = pebs->dla;
1868 data->sample_flags |= PERF_SAMPLE_ADDR;
1869 }
1870
1871 if (x86_pmu.intel_cap.pebs_format >= 2) {
1872 /* Only set the TSX weight when no memory weight. */
1873 if ((sample_type & PERF_SAMPLE_WEIGHT_TYPE) && !fll) {
1874 data->weight.full = intel_get_tsx_weight(pebs->tsx_tuning);
1875 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
1876 }
1877 if (sample_type & PERF_SAMPLE_TRANSACTION) {
1878 data->txn = intel_get_tsx_transaction(pebs->tsx_tuning,
1879 pebs->ax);
1880 data->sample_flags |= PERF_SAMPLE_TRANSACTION;
1881 }
1882 }
1883
1884 /*
1885 * v3 supplies an accurate time stamp, so we use that
1886 * for the time stamp.
1887 *
1888 * We can only do this for the default trace clock.
1889 */
1890 if (x86_pmu.intel_cap.pebs_format >= 3)
1891 setup_pebs_time(event, data, pebs->tsc);
1892
1893 perf_sample_save_brstack(data, event, &cpuc->lbr_stack, NULL);
1894 }
1895
adaptive_pebs_save_regs(struct pt_regs * regs,struct pebs_gprs * gprs)1896 static void adaptive_pebs_save_regs(struct pt_regs *regs,
1897 struct pebs_gprs *gprs)
1898 {
1899 regs->ax = gprs->ax;
1900 regs->bx = gprs->bx;
1901 regs->cx = gprs->cx;
1902 regs->dx = gprs->dx;
1903 regs->si = gprs->si;
1904 regs->di = gprs->di;
1905 regs->bp = gprs->bp;
1906 regs->sp = gprs->sp;
1907 #ifndef CONFIG_X86_32
1908 regs->r8 = gprs->r8;
1909 regs->r9 = gprs->r9;
1910 regs->r10 = gprs->r10;
1911 regs->r11 = gprs->r11;
1912 regs->r12 = gprs->r12;
1913 regs->r13 = gprs->r13;
1914 regs->r14 = gprs->r14;
1915 regs->r15 = gprs->r15;
1916 #endif
1917 }
1918
1919 #define PEBS_LATENCY_MASK 0xffff
1920
1921 /*
1922 * With adaptive PEBS the layout depends on what fields are configured.
1923 */
1924
setup_pebs_adaptive_sample_data(struct perf_event * event,struct pt_regs * iregs,void * __pebs,struct perf_sample_data * data,struct pt_regs * regs)1925 static void setup_pebs_adaptive_sample_data(struct perf_event *event,
1926 struct pt_regs *iregs, void *__pebs,
1927 struct perf_sample_data *data,
1928 struct pt_regs *regs)
1929 {
1930 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1931 struct pebs_basic *basic = __pebs;
1932 void *next_record = basic + 1;
1933 u64 sample_type, format_group;
1934 struct pebs_meminfo *meminfo = NULL;
1935 struct pebs_gprs *gprs = NULL;
1936 struct x86_perf_regs *perf_regs;
1937
1938 if (basic == NULL)
1939 return;
1940
1941 perf_regs = container_of(regs, struct x86_perf_regs, regs);
1942 perf_regs->xmm_regs = NULL;
1943
1944 sample_type = event->attr.sample_type;
1945 format_group = basic->format_group;
1946 perf_sample_data_init(data, 0, event->hw.last_period);
1947 data->period = event->hw.last_period;
1948
1949 setup_pebs_time(event, data, basic->tsc);
1950
1951 /*
1952 * We must however always use iregs for the unwinder to stay sane; the
1953 * record BP,SP,IP can point into thin air when the record is from a
1954 * previous PMI context or an (I)RET happened between the record and
1955 * PMI.
1956 */
1957 perf_sample_save_callchain(data, event, iregs);
1958
1959 *regs = *iregs;
1960 /* The ip in basic is EventingIP */
1961 set_linear_ip(regs, basic->ip);
1962 regs->flags = PERF_EFLAGS_EXACT;
1963
1964 if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT) {
1965 if (x86_pmu.flags & PMU_FL_RETIRE_LATENCY)
1966 data->weight.var3_w = basic->retire_latency;
1967 else
1968 data->weight.var3_w = 0;
1969 }
1970
1971 /*
1972 * The record for MEMINFO is in front of GP
1973 * But PERF_SAMPLE_TRANSACTION needs gprs->ax.
1974 * Save the pointer here but process later.
1975 */
1976 if (format_group & PEBS_DATACFG_MEMINFO) {
1977 meminfo = next_record;
1978 next_record = meminfo + 1;
1979 }
1980
1981 if (format_group & PEBS_DATACFG_GP) {
1982 gprs = next_record;
1983 next_record = gprs + 1;
1984
1985 if (event->attr.precise_ip < 2) {
1986 set_linear_ip(regs, gprs->ip);
1987 regs->flags &= ~PERF_EFLAGS_EXACT;
1988 }
1989
1990 if (sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER))
1991 adaptive_pebs_save_regs(regs, gprs);
1992 }
1993
1994 if (format_group & PEBS_DATACFG_MEMINFO) {
1995 if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) {
1996 u64 latency = x86_pmu.flags & PMU_FL_INSTR_LATENCY ?
1997 meminfo->cache_latency : meminfo->mem_latency;
1998
1999 if (x86_pmu.flags & PMU_FL_INSTR_LATENCY)
2000 data->weight.var2_w = meminfo->instr_latency;
2001
2002 /*
2003 * Although meminfo::latency is defined as a u64,
2004 * only the lower 32 bits include the valid data
2005 * in practice on Ice Lake and earlier platforms.
2006 */
2007 if (sample_type & PERF_SAMPLE_WEIGHT) {
2008 data->weight.full = latency ?:
2009 intel_get_tsx_weight(meminfo->tsx_tuning);
2010 } else {
2011 data->weight.var1_dw = (u32)latency ?:
2012 intel_get_tsx_weight(meminfo->tsx_tuning);
2013 }
2014
2015 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
2016 }
2017
2018 if (sample_type & PERF_SAMPLE_DATA_SRC) {
2019 data->data_src.val = get_data_src(event, meminfo->aux);
2020 data->sample_flags |= PERF_SAMPLE_DATA_SRC;
2021 }
2022
2023 if (sample_type & PERF_SAMPLE_ADDR_TYPE) {
2024 data->addr = meminfo->address;
2025 data->sample_flags |= PERF_SAMPLE_ADDR;
2026 }
2027
2028 if (sample_type & PERF_SAMPLE_TRANSACTION) {
2029 data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning,
2030 gprs ? gprs->ax : 0);
2031 data->sample_flags |= PERF_SAMPLE_TRANSACTION;
2032 }
2033 }
2034
2035 if (format_group & PEBS_DATACFG_XMMS) {
2036 struct pebs_xmm *xmm = next_record;
2037
2038 next_record = xmm + 1;
2039 perf_regs->xmm_regs = xmm->xmm;
2040 }
2041
2042 if (format_group & PEBS_DATACFG_LBRS) {
2043 struct lbr_entry *lbr = next_record;
2044 int num_lbr = ((format_group >> PEBS_DATACFG_LBR_SHIFT)
2045 & 0xff) + 1;
2046 next_record = next_record + num_lbr * sizeof(struct lbr_entry);
2047
2048 if (has_branch_stack(event)) {
2049 intel_pmu_store_pebs_lbrs(lbr);
2050 intel_pmu_lbr_save_brstack(data, cpuc, event);
2051 }
2052 }
2053
2054 WARN_ONCE(next_record != __pebs + basic->format_size,
2055 "PEBS record size %u, expected %llu, config %llx\n",
2056 basic->format_size,
2057 (u64)(next_record - __pebs),
2058 format_group);
2059 }
2060
2061 static inline void *
get_next_pebs_record_by_bit(void * base,void * top,int bit)2062 get_next_pebs_record_by_bit(void *base, void *top, int bit)
2063 {
2064 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2065 void *at;
2066 u64 pebs_status;
2067
2068 /*
2069 * fmt0 does not have a status bitfield (does not use
2070 * perf_record_nhm format)
2071 */
2072 if (x86_pmu.intel_cap.pebs_format < 1)
2073 return base;
2074
2075 if (base == NULL)
2076 return NULL;
2077
2078 for (at = base; at < top; at += cpuc->pebs_record_size) {
2079 unsigned long status = get_pebs_status(at);
2080
2081 if (test_bit(bit, (unsigned long *)&status)) {
2082 /* PEBS v3 has accurate status bits */
2083 if (x86_pmu.intel_cap.pebs_format >= 3)
2084 return at;
2085
2086 if (status == (1 << bit))
2087 return at;
2088
2089 /* clear non-PEBS bit and re-check */
2090 pebs_status = status & cpuc->pebs_enabled;
2091 pebs_status &= PEBS_COUNTER_MASK;
2092 if (pebs_status == (1 << bit))
2093 return at;
2094 }
2095 }
2096 return NULL;
2097 }
2098
2099 /*
2100 * Special variant of intel_pmu_save_and_restart() for auto-reload.
2101 */
2102 static int
intel_pmu_save_and_restart_reload(struct perf_event * event,int count)2103 intel_pmu_save_and_restart_reload(struct perf_event *event, int count)
2104 {
2105 struct hw_perf_event *hwc = &event->hw;
2106 int shift = 64 - x86_pmu.cntval_bits;
2107 u64 period = hwc->sample_period;
2108 u64 prev_raw_count, new_raw_count;
2109 s64 new, old;
2110
2111 WARN_ON(!period);
2112
2113 /*
2114 * drain_pebs() only happens when the PMU is disabled.
2115 */
2116 WARN_ON(this_cpu_read(cpu_hw_events.enabled));
2117
2118 prev_raw_count = local64_read(&hwc->prev_count);
2119 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
2120 local64_set(&hwc->prev_count, new_raw_count);
2121
2122 /*
2123 * Since the counter increments a negative counter value and
2124 * overflows on the sign switch, giving the interval:
2125 *
2126 * [-period, 0]
2127 *
2128 * the difference between two consecutive reads is:
2129 *
2130 * A) value2 - value1;
2131 * when no overflows have happened in between,
2132 *
2133 * B) (0 - value1) + (value2 - (-period));
2134 * when one overflow happened in between,
2135 *
2136 * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period));
2137 * when @n overflows happened in between.
2138 *
2139 * Here A) is the obvious difference, B) is the extension to the
2140 * discrete interval, where the first term is to the top of the
2141 * interval and the second term is from the bottom of the next
2142 * interval and C) the extension to multiple intervals, where the
2143 * middle term is the whole intervals covered.
2144 *
2145 * An equivalent of C, by reduction, is:
2146 *
2147 * value2 - value1 + n * period
2148 */
2149 new = ((s64)(new_raw_count << shift) >> shift);
2150 old = ((s64)(prev_raw_count << shift) >> shift);
2151 local64_add(new - old + count * period, &event->count);
2152
2153 local64_set(&hwc->period_left, -new);
2154
2155 perf_event_update_userpage(event);
2156
2157 return 0;
2158 }
2159
2160 typedef void (*setup_fn)(struct perf_event *, struct pt_regs *, void *,
2161 struct perf_sample_data *, struct pt_regs *);
2162
2163 static struct pt_regs dummy_iregs;
2164
2165 static __always_inline void
__intel_pmu_pebs_event(struct perf_event * event,struct pt_regs * iregs,struct pt_regs * regs,struct perf_sample_data * data,void * at,setup_fn setup_sample)2166 __intel_pmu_pebs_event(struct perf_event *event,
2167 struct pt_regs *iregs,
2168 struct pt_regs *regs,
2169 struct perf_sample_data *data,
2170 void *at,
2171 setup_fn setup_sample)
2172 {
2173 setup_sample(event, iregs, at, data, regs);
2174 perf_event_output(event, data, regs);
2175 }
2176
2177 static __always_inline void
__intel_pmu_pebs_last_event(struct perf_event * event,struct pt_regs * iregs,struct pt_regs * regs,struct perf_sample_data * data,void * at,int count,setup_fn setup_sample)2178 __intel_pmu_pebs_last_event(struct perf_event *event,
2179 struct pt_regs *iregs,
2180 struct pt_regs *regs,
2181 struct perf_sample_data *data,
2182 void *at,
2183 int count,
2184 setup_fn setup_sample)
2185 {
2186 struct hw_perf_event *hwc = &event->hw;
2187
2188 setup_sample(event, iregs, at, data, regs);
2189 if (iregs == &dummy_iregs) {
2190 /*
2191 * The PEBS records may be drained in the non-overflow context,
2192 * e.g., large PEBS + context switch. Perf should treat the
2193 * last record the same as other PEBS records, and doesn't
2194 * invoke the generic overflow handler.
2195 */
2196 perf_event_output(event, data, regs);
2197 } else {
2198 /*
2199 * All but the last records are processed.
2200 * The last one is left to be able to call the overflow handler.
2201 */
2202 if (perf_event_overflow(event, data, regs))
2203 x86_pmu_stop(event, 0);
2204 }
2205
2206 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
2207 /*
2208 * Now, auto-reload is only enabled in fixed period mode.
2209 * The reload value is always hwc->sample_period.
2210 * May need to change it, if auto-reload is enabled in
2211 * freq mode later.
2212 */
2213 intel_pmu_save_and_restart_reload(event, count);
2214 } else
2215 intel_pmu_save_and_restart(event);
2216 }
2217
2218 static __always_inline void
__intel_pmu_pebs_events(struct perf_event * event,struct pt_regs * iregs,struct perf_sample_data * data,void * base,void * top,int bit,int count,setup_fn setup_sample)2219 __intel_pmu_pebs_events(struct perf_event *event,
2220 struct pt_regs *iregs,
2221 struct perf_sample_data *data,
2222 void *base, void *top,
2223 int bit, int count,
2224 setup_fn setup_sample)
2225 {
2226 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2227 struct x86_perf_regs perf_regs;
2228 struct pt_regs *regs = &perf_regs.regs;
2229 void *at = get_next_pebs_record_by_bit(base, top, bit);
2230 int cnt = count;
2231
2232 if (!iregs)
2233 iregs = &dummy_iregs;
2234
2235 while (cnt > 1) {
2236 __intel_pmu_pebs_event(event, iregs, regs, data, at, setup_sample);
2237 at += cpuc->pebs_record_size;
2238 at = get_next_pebs_record_by_bit(at, top, bit);
2239 cnt--;
2240 }
2241
2242 __intel_pmu_pebs_last_event(event, iregs, regs, data, at, count, setup_sample);
2243 }
2244
intel_pmu_drain_pebs_core(struct pt_regs * iregs,struct perf_sample_data * data)2245 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs, struct perf_sample_data *data)
2246 {
2247 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2248 struct debug_store *ds = cpuc->ds;
2249 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
2250 struct pebs_record_core *at, *top;
2251 int n;
2252
2253 if (!x86_pmu.pebs_active)
2254 return;
2255
2256 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
2257 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
2258
2259 /*
2260 * Whatever else happens, drain the thing
2261 */
2262 ds->pebs_index = ds->pebs_buffer_base;
2263
2264 if (!test_bit(0, cpuc->active_mask))
2265 return;
2266
2267 WARN_ON_ONCE(!event);
2268
2269 if (!event->attr.precise_ip)
2270 return;
2271
2272 n = top - at;
2273 if (n <= 0) {
2274 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2275 intel_pmu_save_and_restart_reload(event, 0);
2276 return;
2277 }
2278
2279 __intel_pmu_pebs_events(event, iregs, data, at, top, 0, n,
2280 setup_pebs_fixed_sample_data);
2281 }
2282
intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events * cpuc,int size)2283 static void intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events *cpuc, int size)
2284 {
2285 struct perf_event *event;
2286 int bit;
2287
2288 /*
2289 * The drain_pebs() could be called twice in a short period
2290 * for auto-reload event in pmu::read(). There are no
2291 * overflows have happened in between.
2292 * It needs to call intel_pmu_save_and_restart_reload() to
2293 * update the event->count for this case.
2294 */
2295 for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, size) {
2296 event = cpuc->events[bit];
2297 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2298 intel_pmu_save_and_restart_reload(event, 0);
2299 }
2300 }
2301
intel_pmu_drain_pebs_nhm(struct pt_regs * iregs,struct perf_sample_data * data)2302 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_data *data)
2303 {
2304 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2305 struct debug_store *ds = cpuc->ds;
2306 struct perf_event *event;
2307 void *base, *at, *top;
2308 short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2309 short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2310 int max_pebs_events = intel_pmu_max_num_pebs(NULL);
2311 int bit, i, size;
2312 u64 mask;
2313
2314 if (!x86_pmu.pebs_active)
2315 return;
2316
2317 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
2318 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
2319
2320 ds->pebs_index = ds->pebs_buffer_base;
2321
2322 mask = x86_pmu.pebs_events_mask;
2323 size = max_pebs_events;
2324 if (x86_pmu.flags & PMU_FL_PEBS_ALL) {
2325 mask |= x86_pmu.fixed_cntr_mask64 << INTEL_PMC_IDX_FIXED;
2326 size = INTEL_PMC_IDX_FIXED + x86_pmu_max_num_counters_fixed(NULL);
2327 }
2328
2329 if (unlikely(base >= top)) {
2330 intel_pmu_pebs_event_update_no_drain(cpuc, size);
2331 return;
2332 }
2333
2334 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
2335 struct pebs_record_nhm *p = at;
2336 u64 pebs_status;
2337
2338 pebs_status = p->status & cpuc->pebs_enabled;
2339 pebs_status &= mask;
2340
2341 /* PEBS v3 has more accurate status bits */
2342 if (x86_pmu.intel_cap.pebs_format >= 3) {
2343 for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
2344 counts[bit]++;
2345
2346 continue;
2347 }
2348
2349 /*
2350 * On some CPUs the PEBS status can be zero when PEBS is
2351 * racing with clearing of GLOBAL_STATUS.
2352 *
2353 * Normally we would drop that record, but in the
2354 * case when there is only a single active PEBS event
2355 * we can assume it's for that event.
2356 */
2357 if (!pebs_status && cpuc->pebs_enabled &&
2358 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
2359 pebs_status = p->status = cpuc->pebs_enabled;
2360
2361 bit = find_first_bit((unsigned long *)&pebs_status,
2362 max_pebs_events);
2363
2364 if (!(x86_pmu.pebs_events_mask & (1 << bit)))
2365 continue;
2366
2367 /*
2368 * The PEBS hardware does not deal well with the situation
2369 * when events happen near to each other and multiple bits
2370 * are set. But it should happen rarely.
2371 *
2372 * If these events include one PEBS and multiple non-PEBS
2373 * events, it doesn't impact PEBS record. The record will
2374 * be handled normally. (slow path)
2375 *
2376 * If these events include two or more PEBS events, the
2377 * records for the events can be collapsed into a single
2378 * one, and it's not possible to reconstruct all events
2379 * that caused the PEBS record. It's called collision.
2380 * If collision happened, the record will be dropped.
2381 */
2382 if (pebs_status != (1ULL << bit)) {
2383 for_each_set_bit(i, (unsigned long *)&pebs_status, size)
2384 error[i]++;
2385 continue;
2386 }
2387
2388 counts[bit]++;
2389 }
2390
2391 for_each_set_bit(bit, (unsigned long *)&mask, size) {
2392 if ((counts[bit] == 0) && (error[bit] == 0))
2393 continue;
2394
2395 event = cpuc->events[bit];
2396 if (WARN_ON_ONCE(!event))
2397 continue;
2398
2399 if (WARN_ON_ONCE(!event->attr.precise_ip))
2400 continue;
2401
2402 /* log dropped samples number */
2403 if (error[bit]) {
2404 perf_log_lost_samples(event, error[bit]);
2405
2406 if (iregs && perf_event_account_interrupt(event))
2407 x86_pmu_stop(event, 0);
2408 }
2409
2410 if (counts[bit]) {
2411 __intel_pmu_pebs_events(event, iregs, data, base,
2412 top, bit, counts[bit],
2413 setup_pebs_fixed_sample_data);
2414 }
2415 }
2416 }
2417
intel_pmu_drain_pebs_icl(struct pt_regs * iregs,struct perf_sample_data * data)2418 static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_data *data)
2419 {
2420 short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2421 void *last[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS];
2422 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2423 struct debug_store *ds = cpuc->ds;
2424 struct x86_perf_regs perf_regs;
2425 struct pt_regs *regs = &perf_regs.regs;
2426 struct pebs_basic *basic;
2427 struct perf_event *event;
2428 void *base, *at, *top;
2429 int bit;
2430 u64 mask;
2431
2432 if (!x86_pmu.pebs_active)
2433 return;
2434
2435 base = (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base;
2436 top = (struct pebs_basic *)(unsigned long)ds->pebs_index;
2437
2438 ds->pebs_index = ds->pebs_buffer_base;
2439
2440 mask = hybrid(cpuc->pmu, pebs_events_mask) |
2441 (hybrid(cpuc->pmu, fixed_cntr_mask64) << INTEL_PMC_IDX_FIXED);
2442
2443 if (unlikely(base >= top)) {
2444 intel_pmu_pebs_event_update_no_drain(cpuc, X86_PMC_IDX_MAX);
2445 return;
2446 }
2447
2448 if (!iregs)
2449 iregs = &dummy_iregs;
2450
2451 /* Process all but the last event for each counter. */
2452 for (at = base; at < top; at += basic->format_size) {
2453 u64 pebs_status;
2454
2455 basic = at;
2456 if (basic->format_size != cpuc->pebs_record_size)
2457 continue;
2458
2459 pebs_status = basic->applicable_counters & cpuc->pebs_enabled & mask;
2460 for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) {
2461 event = cpuc->events[bit];
2462
2463 if (WARN_ON_ONCE(!event) ||
2464 WARN_ON_ONCE(!event->attr.precise_ip))
2465 continue;
2466
2467 if (counts[bit]++) {
2468 __intel_pmu_pebs_event(event, iregs, regs, data, last[bit],
2469 setup_pebs_adaptive_sample_data);
2470 }
2471 last[bit] = at;
2472 }
2473 }
2474
2475 for_each_set_bit(bit, (unsigned long *)&mask, X86_PMC_IDX_MAX) {
2476 if (!counts[bit])
2477 continue;
2478
2479 event = cpuc->events[bit];
2480
2481 __intel_pmu_pebs_last_event(event, iregs, regs, data, last[bit],
2482 counts[bit], setup_pebs_adaptive_sample_data);
2483 }
2484 }
2485
2486 /*
2487 * BTS, PEBS probe and setup
2488 */
2489
intel_ds_init(void)2490 void __init intel_ds_init(void)
2491 {
2492 /*
2493 * No support for 32bit formats
2494 */
2495 if (!boot_cpu_has(X86_FEATURE_DTES64))
2496 return;
2497
2498 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
2499 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
2500 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
2501 if (x86_pmu.version <= 4)
2502 x86_pmu.pebs_no_isolation = 1;
2503
2504 if (x86_pmu.pebs) {
2505 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
2506 char *pebs_qual = "";
2507 int format = x86_pmu.intel_cap.pebs_format;
2508
2509 if (format < 4)
2510 x86_pmu.intel_cap.pebs_baseline = 0;
2511
2512 switch (format) {
2513 case 0:
2514 pr_cont("PEBS fmt0%c, ", pebs_type);
2515 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
2516 /*
2517 * Using >PAGE_SIZE buffers makes the WRMSR to
2518 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
2519 * mysteriously hang on Core2.
2520 *
2521 * As a workaround, we don't do this.
2522 */
2523 x86_pmu.pebs_buffer_size = PAGE_SIZE;
2524 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
2525 break;
2526
2527 case 1:
2528 pr_cont("PEBS fmt1%c, ", pebs_type);
2529 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
2530 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2531 break;
2532
2533 case 2:
2534 pr_cont("PEBS fmt2%c, ", pebs_type);
2535 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
2536 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2537 break;
2538
2539 case 3:
2540 pr_cont("PEBS fmt3%c, ", pebs_type);
2541 x86_pmu.pebs_record_size =
2542 sizeof(struct pebs_record_skl);
2543 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2544 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
2545 break;
2546
2547 case 6:
2548 case 5:
2549 x86_pmu.pebs_ept = 1;
2550 fallthrough;
2551 case 4:
2552 x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;
2553 x86_pmu.pebs_record_size = sizeof(struct pebs_basic);
2554 if (x86_pmu.intel_cap.pebs_baseline) {
2555 x86_pmu.large_pebs_flags |=
2556 PERF_SAMPLE_BRANCH_STACK |
2557 PERF_SAMPLE_TIME;
2558 x86_pmu.flags |= PMU_FL_PEBS_ALL;
2559 x86_pmu.pebs_capable = ~0ULL;
2560 pebs_qual = "-baseline";
2561 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
2562 } else {
2563 /* Only basic record supported */
2564 x86_pmu.large_pebs_flags &=
2565 ~(PERF_SAMPLE_ADDR |
2566 PERF_SAMPLE_TIME |
2567 PERF_SAMPLE_DATA_SRC |
2568 PERF_SAMPLE_TRANSACTION |
2569 PERF_SAMPLE_REGS_USER |
2570 PERF_SAMPLE_REGS_INTR);
2571 }
2572 pr_cont("PEBS fmt4%c%s, ", pebs_type, pebs_qual);
2573
2574 /*
2575 * The PEBS-via-PT is not supported on hybrid platforms,
2576 * because not all CPUs of a hybrid machine support it.
2577 * The global x86_pmu.intel_cap, which only contains the
2578 * common capabilities, is used to check the availability
2579 * of the feature. The per-PMU pebs_output_pt_available
2580 * in a hybrid machine should be ignored.
2581 */
2582 if (x86_pmu.intel_cap.pebs_output_pt_available) {
2583 pr_cont("PEBS-via-PT, ");
2584 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_AUX_OUTPUT;
2585 }
2586
2587 break;
2588
2589 default:
2590 pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
2591 x86_pmu.pebs = 0;
2592 }
2593 }
2594 }
2595
perf_restore_debug_store(void)2596 void perf_restore_debug_store(void)
2597 {
2598 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2599
2600 if (!x86_pmu.bts && !x86_pmu.pebs)
2601 return;
2602
2603 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
2604 }
2605