1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Bluetooth supports for Qualcomm Atheros ROME chips
4 *
5 * Copyright (c) 2015 The Linux Foundation. All rights reserved.
6 */
7
8 #define EDL_PATCH_CMD_OPCODE 0xFC00
9 #define EDL_NVM_ACCESS_OPCODE 0xFC0B
10 #define EDL_WRITE_BD_ADDR_OPCODE 0xFC14
11 #define EDL_PATCH_CMD_LEN 1
12 #define EDL_PATCH_VER_REQ_CMD 0x19
13 #define EDL_PATCH_TLV_REQ_CMD 0x1E
14 #define EDL_GET_BUILD_INFO_CMD 0x20
15 #define EDL_GET_BID_REQ_CMD 0x23
16 #define EDL_NVM_ACCESS_SET_REQ_CMD 0x01
17 #define EDL_PATCH_CONFIG_CMD 0x28
18 #define MAX_SIZE_PER_TLV_SEGMENT 243
19 #define QCA_PRE_SHUTDOWN_CMD 0xFC08
20 #define QCA_DISABLE_LOGGING 0xFC17
21
22 #define EDL_CMD_REQ_RES_EVT 0x00
23 #define EDL_PATCH_VER_RES_EVT 0x19
24 #define EDL_APP_VER_RES_EVT 0x02
25 #define EDL_TVL_DNLD_RES_EVT 0x04
26 #define EDL_CMD_EXE_STATUS_EVT 0x00
27 #define EDL_SET_BAUDRATE_RSP_EVT 0x92
28 #define EDL_NVM_ACCESS_CODE_EVT 0x0B
29 #define EDL_PATCH_CONFIG_RES_EVT 0x00
30 #define QCA_DISABLE_LOGGING_SUB_OP 0x14
31
32 #define EDL_TAG_ID_BD_ADDR 2
33 #define EDL_TAG_ID_HCI 17
34 #define EDL_TAG_ID_DEEP_SLEEP 27
35
36 #define QCA_WCN3990_POWERON_PULSE 0xFC
37 #define QCA_WCN3990_POWEROFF_PULSE 0xC0
38
39 #define QCA_HCI_CC_OPCODE 0xFC00
40 #define QCA_HCI_CC_SUCCESS 0x00
41
42 #define QCA_WCN3991_SOC_ID 0x40014320
43
44 #define QCA_WCN3950_SOC_ID_T 0x40074130
45 #define QCA_WCN3950_SOC_ID_S 0x40075130
46
47 /* QCA chipset version can be decided by patch and SoC
48 * version, combination with upper 2 bytes from SoC
49 * and lower 2 bytes from patch will be used.
50 */
51 #define get_soc_ver(soc_id, rom_ver) \
52 ((le32_to_cpu(soc_id) << 16) | (le16_to_cpu(rom_ver)))
53
54 #define QCA_HSP_GF_SOC_ID 0x1200
55 #define QCA_HSP_GF_SOC_MASK 0x0000ff00
56
57 enum qca_baudrate {
58 QCA_BAUDRATE_115200 = 0,
59 QCA_BAUDRATE_57600,
60 QCA_BAUDRATE_38400,
61 QCA_BAUDRATE_19200,
62 QCA_BAUDRATE_9600,
63 QCA_BAUDRATE_230400,
64 QCA_BAUDRATE_250000,
65 QCA_BAUDRATE_460800,
66 QCA_BAUDRATE_500000,
67 QCA_BAUDRATE_720000,
68 QCA_BAUDRATE_921600,
69 QCA_BAUDRATE_1000000,
70 QCA_BAUDRATE_1250000,
71 QCA_BAUDRATE_2000000,
72 QCA_BAUDRATE_3000000,
73 QCA_BAUDRATE_4000000,
74 QCA_BAUDRATE_1600000,
75 QCA_BAUDRATE_3200000,
76 QCA_BAUDRATE_3500000,
77 QCA_BAUDRATE_AUTO = 0xFE,
78 QCA_BAUDRATE_RESERVED
79 };
80
81 enum qca_tlv_dnld_mode {
82 QCA_SKIP_EVT_NONE,
83 QCA_SKIP_EVT_VSE,
84 QCA_SKIP_EVT_CC,
85 QCA_SKIP_EVT_VSE_CC
86 };
87
88 enum qca_tlv_type {
89 TLV_TYPE_PATCH = 1,
90 TLV_TYPE_NVM,
91 ELF_TYPE_PATCH,
92 };
93
94 struct qca_fw_config {
95 u8 type;
96 char fwname[64];
97 uint8_t user_baud_rate;
98 enum qca_tlv_dnld_mode dnld_mode;
99 enum qca_tlv_dnld_mode dnld_type;
100 bdaddr_t bdaddr;
101 };
102
103 struct edl_event_hdr {
104 __u8 cresp;
105 __u8 rtype;
106 __u8 data[];
107 } __packed;
108
109 struct qca_btsoc_version {
110 __le32 product_id;
111 __le16 patch_ver;
112 __le16 rom_ver;
113 __le32 soc_id;
114 } __packed;
115
116 struct tlv_seg_resp {
117 __u8 result;
118 } __packed;
119
120 struct tlv_type_patch {
121 __le32 total_size;
122 __le32 data_length;
123 __u8 format_version;
124 __u8 signature;
125 __u8 download_mode;
126 __u8 reserved1;
127 __le16 product_id;
128 __le16 rom_build;
129 __le16 patch_version;
130 __le16 reserved2;
131 __le32 entry;
132 } __packed;
133
134 struct tlv_type_nvm {
135 __le16 tag_id;
136 __le16 tag_len;
137 __le32 reserve1;
138 __le32 reserve2;
139 __u8 data[];
140 } __packed;
141
142 struct tlv_type_hdr {
143 __le32 type_len;
144 __u8 data[];
145 } __packed;
146
147 enum qca_btsoc_type {
148 QCA_INVALID = -1,
149 QCA_AR3002,
150 QCA_ROME,
151 QCA_WCN3950,
152 QCA_WCN3988,
153 QCA_WCN3990,
154 QCA_WCN3998,
155 QCA_WCN3991,
156 QCA_QCA2066,
157 QCA_QCA6390,
158 QCA_WCN6750,
159 QCA_WCN6855,
160 QCA_WCN7850,
161 };
162
163 #if IS_ENABLED(CONFIG_BT_QCA)
164
165 int qca_set_bdaddr_rome(struct hci_dev *hdev, const bdaddr_t *bdaddr);
166 int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,
167 enum qca_btsoc_type soc_type, struct qca_btsoc_version ver,
168 const char *firmware_name, const char *rampatch_name);
169 int qca_read_soc_version(struct hci_dev *hdev, struct qca_btsoc_version *ver,
170 enum qca_btsoc_type);
171 int qca_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr);
172 int qca_send_pre_shutdown_cmd(struct hci_dev *hdev);
173 #else
174
qca_set_bdaddr_rome(struct hci_dev * hdev,const bdaddr_t * bdaddr)175 static inline int qca_set_bdaddr_rome(struct hci_dev *hdev, const bdaddr_t *bdaddr)
176 {
177 return -EOPNOTSUPP;
178 }
179
qca_uart_setup(struct hci_dev * hdev,uint8_t baudrate,enum qca_btsoc_type soc_type,struct qca_btsoc_version ver,const char * firmware_name,const char * rampatch_name)180 static inline int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,
181 enum qca_btsoc_type soc_type,
182 struct qca_btsoc_version ver,
183 const char *firmware_name,
184 const char *rampatch_name)
185 {
186 return -EOPNOTSUPP;
187 }
188
qca_read_soc_version(struct hci_dev * hdev,struct qca_btsoc_version * ver,enum qca_btsoc_type)189 static inline int qca_read_soc_version(struct hci_dev *hdev,
190 struct qca_btsoc_version *ver,
191 enum qca_btsoc_type)
192 {
193 return -EOPNOTSUPP;
194 }
195
qca_set_bdaddr(struct hci_dev * hdev,const bdaddr_t * bdaddr)196 static inline int qca_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr)
197 {
198 return -EOPNOTSUPP;
199 }
200
qca_send_pre_shutdown_cmd(struct hci_dev * hdev)201 static inline int qca_send_pre_shutdown_cmd(struct hci_dev *hdev)
202 {
203 return -EOPNOTSUPP;
204 }
205 #endif
206