1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * StarFive JH7110 Video-Output Clock Driver
4 *
5 * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/io.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/reset.h>
14
15 #include <dt-bindings/clock/starfive,jh7110-crg.h>
16
17 #include "clk-starfive-jh7110.h"
18
19 /* external clocks */
20 #define JH7110_VOUTCLK_VOUT_SRC (JH7110_VOUTCLK_END + 0)
21 #define JH7110_VOUTCLK_VOUT_TOP_AHB (JH7110_VOUTCLK_END + 1)
22 #define JH7110_VOUTCLK_VOUT_TOP_AXI (JH7110_VOUTCLK_END + 2)
23 #define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK (JH7110_VOUTCLK_END + 3)
24 #define JH7110_VOUTCLK_I2STX0_BCLK (JH7110_VOUTCLK_END + 4)
25 #define JH7110_VOUTCLK_HDMITX0_PIXELCLK (JH7110_VOUTCLK_END + 5)
26 #define JH7110_VOUTCLK_EXT_END (JH7110_VOUTCLK_END + 6)
27
28 static struct clk_bulk_data jh7110_vout_top_clks[] = {
29 { .id = "vout_src" },
30 { .id = "vout_top_ahb" }
31 };
32
33 static const struct jh71x0_clk_data jh7110_voutclk_data[] = {
34 /* divider */
35 JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB),
36 JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC),
37 JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC),
38 JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB),
39 /* dc8200 */
40 JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
41 JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
42 JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB),
43 JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2,
44 JH7110_VOUTCLK_DC8200_PIX,
45 JH7110_VOUTCLK_HDMITX0_PIXELCLK),
46 JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2,
47 JH7110_VOUTCLK_DC8200_PIX,
48 JH7110_VOUTCLK_HDMITX0_PIXELCLK),
49 /* LCD */
50 JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2,
51 JH7110_VOUTCLK_DC8200_PIX0,
52 JH7110_VOUTCLK_DC8200_PIX1),
53 /* dsiTx */
54 JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS),
55 JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS),
56 JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2,
57 JH7110_VOUTCLK_DC8200_PIX,
58 JH7110_VOUTCLK_HDMITX0_PIXELCLK),
59 JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC),
60 /* mipitx DPHY */
61 JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0,
62 JH7110_VOUTCLK_TX_ESC),
63 /* hdmi */
64 JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0,
65 JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK),
66 JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0,
67 JH7110_VOUTCLK_I2STX0_BCLK),
68 JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB),
69 };
70
jh7110_vout_top_rst_init(struct jh71x0_clk_priv * priv)71 static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv)
72 {
73 struct reset_control *top_rst;
74
75 /* The reset should be shared and other Vout modules will use its. */
76 top_rst = devm_reset_control_get_shared(priv->dev, NULL);
77 if (IS_ERR(top_rst))
78 return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n");
79
80 return reset_control_deassert(top_rst);
81 }
82
83 #ifdef CONFIG_PM
jh7110_voutcrg_suspend(struct device * dev)84 static int jh7110_voutcrg_suspend(struct device *dev)
85 {
86 struct jh7110_top_sysclk *top = dev_get_drvdata(dev);
87
88 clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
89
90 return 0;
91 }
92
jh7110_voutcrg_resume(struct device * dev)93 static int jh7110_voutcrg_resume(struct device *dev)
94 {
95 struct jh7110_top_sysclk *top = dev_get_drvdata(dev);
96
97 return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks);
98 }
99
100 static const struct dev_pm_ops jh7110_voutcrg_pm_ops = {
101 RUNTIME_PM_OPS(jh7110_voutcrg_suspend, jh7110_voutcrg_resume, NULL)
102 };
103 #endif
104
jh7110_voutcrg_probe(struct platform_device * pdev)105 static int jh7110_voutcrg_probe(struct platform_device *pdev)
106 {
107 struct jh71x0_clk_priv *priv;
108 struct jh7110_top_sysclk *top;
109 unsigned int idx;
110 int ret;
111
112 priv = devm_kzalloc(&pdev->dev,
113 struct_size(priv, reg, JH7110_VOUTCLK_END),
114 GFP_KERNEL);
115 if (!priv)
116 return -ENOMEM;
117
118 top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL);
119 if (!top)
120 return -ENOMEM;
121
122 spin_lock_init(&priv->rmw_lock);
123 priv->num_reg = JH7110_VOUTCLK_END;
124 priv->dev = &pdev->dev;
125 priv->base = devm_platform_ioremap_resource(pdev, 0);
126 if (IS_ERR(priv->base))
127 return PTR_ERR(priv->base);
128
129 top->top_clks = jh7110_vout_top_clks;
130 top->top_clks_num = ARRAY_SIZE(jh7110_vout_top_clks);
131 ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks);
132 if (ret)
133 return dev_err_probe(priv->dev, ret, "failed to get top clocks\n");
134 dev_set_drvdata(priv->dev, top);
135
136 /* enable power domain and clocks */
137 pm_runtime_enable(priv->dev);
138 ret = pm_runtime_resume_and_get(priv->dev);
139 if (ret < 0)
140 return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
141
142 ret = jh7110_vout_top_rst_init(priv);
143 if (ret)
144 goto err_exit;
145
146 for (idx = 0; idx < JH7110_VOUTCLK_END; idx++) {
147 u32 max = jh7110_voutclk_data[idx].max;
148 struct clk_parent_data parents[4] = {};
149 struct clk_init_data init = {
150 .name = jh7110_voutclk_data[idx].name,
151 .ops = starfive_jh71x0_clk_ops(max),
152 .parent_data = parents,
153 .num_parents =
154 ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
155 .flags = jh7110_voutclk_data[idx].flags,
156 };
157 struct jh71x0_clk *clk = &priv->reg[idx];
158 unsigned int i;
159 const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = {
160 "vout_src",
161 "vout_top_ahb",
162 "vout_top_axi",
163 "vout_top_hdmitx0_mclk",
164 "i2stx0_bclk",
165 "hdmitx0_pixelclk"
166 };
167
168 for (i = 0; i < init.num_parents; i++) {
169 unsigned int pidx = jh7110_voutclk_data[idx].parents[i];
170
171 if (pidx < JH7110_VOUTCLK_END)
172 parents[i].hw = &priv->reg[pidx].hw;
173 else if (pidx < JH7110_VOUTCLK_EXT_END)
174 parents[i].fw_name = fw_name[pidx - JH7110_VOUTCLK_END];
175 }
176
177 clk->hw.init = &init;
178 clk->idx = idx;
179 clk->max_div = max & JH71X0_CLK_DIV_MASK;
180
181 ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
182 if (ret)
183 goto err_exit;
184 }
185
186 ret = devm_of_clk_add_hw_provider(&pdev->dev, jh71x0_clk_get, priv);
187 if (ret)
188 goto err_exit;
189
190 ret = jh7110_reset_controller_register(priv, "rst-vo", 4);
191 if (ret)
192 goto err_exit;
193
194 return 0;
195
196 err_exit:
197 pm_runtime_put_sync(priv->dev);
198 pm_runtime_disable(priv->dev);
199 return ret;
200 }
201
jh7110_voutcrg_remove(struct platform_device * pdev)202 static void jh7110_voutcrg_remove(struct platform_device *pdev)
203 {
204 pm_runtime_put_sync(&pdev->dev);
205 pm_runtime_disable(&pdev->dev);
206 }
207
208 static const struct of_device_id jh7110_voutcrg_match[] = {
209 { .compatible = "starfive,jh7110-voutcrg" },
210 { /* sentinel */ }
211 };
212 MODULE_DEVICE_TABLE(of, jh7110_voutcrg_match);
213
214 static struct platform_driver jh7110_voutcrg_driver = {
215 .probe = jh7110_voutcrg_probe,
216 .remove = jh7110_voutcrg_remove,
217 .driver = {
218 .name = "clk-starfive-jh7110-vout",
219 .of_match_table = jh7110_voutcrg_match,
220 .pm = pm_ptr(&jh7110_voutcrg_pm_ops),
221 },
222 };
223 module_platform_driver(jh7110_voutcrg_driver);
224
225 MODULE_AUTHOR("Xingyu Wu <[email protected]>");
226 MODULE_DESCRIPTION("StarFive JH7110 Video-Output clock driver");
227 MODULE_LICENSE("GPL");
228