1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
4 *
5 * device name digital output 7-bit I2C slave address (pin selectable)
6 * ---------------------------------------------------------------------
7 * MMA8451Q 14 bit 0x1c / 0x1d
8 * MMA8452Q 12 bit 0x1c / 0x1d
9 * MMA8453Q 10 bit 0x1c / 0x1d
10 * MMA8652FC 12 bit 0x1d
11 * MMA8653FC 10 bit 0x1d
12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f
13 *
14 * Copyright 2015 Martin Kepplinger <[email protected]>
15 * Copyright 2014 Peter Meerwald <[email protected]>
16 *
17 *
18 * TODO: orientation events
19 */
20
21 #include <linux/module.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/property.h>
24 #include <linux/i2c.h>
25 #include <linux/iio/iio.h>
26 #include <linux/iio/sysfs.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/trigger.h>
29 #include <linux/iio/trigger_consumer.h>
30 #include <linux/iio/triggered_buffer.h>
31 #include <linux/iio/events.h>
32 #include <linux/delay.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/types.h>
36
37 #define MMA8452_STATUS 0x00
38 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
39 #define MMA8452_OUT_X 0x01 /* MSB first */
40 #define MMA8452_OUT_Y 0x03
41 #define MMA8452_OUT_Z 0x05
42 #define MMA8452_INT_SRC 0x0c
43 #define MMA8452_WHO_AM_I 0x0d
44 #define MMA8452_DATA_CFG 0x0e
45 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
46 #define MMA8452_DATA_CFG_FS_2G 0
47 #define MMA8452_DATA_CFG_FS_4G 1
48 #define MMA8452_DATA_CFG_FS_8G 2
49 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
50 #define MMA8452_HP_FILTER_CUTOFF 0x0f
51 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
52 #define MMA8452_FF_MT_CFG 0x15
53 #define MMA8452_FF_MT_CFG_OAE BIT(6)
54 #define MMA8452_FF_MT_CFG_ELE BIT(7)
55 #define MMA8452_FF_MT_SRC 0x16
56 #define MMA8452_FF_MT_SRC_XHE BIT(1)
57 #define MMA8452_FF_MT_SRC_YHE BIT(3)
58 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
59 #define MMA8452_FF_MT_THS 0x17
60 #define MMA8452_FF_MT_THS_MASK 0x7f
61 #define MMA8452_FF_MT_COUNT 0x18
62 #define MMA8452_FF_MT_CHAN_SHIFT 3
63 #define MMA8452_TRANSIENT_CFG 0x1d
64 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
65 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
66 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
67 #define MMA8452_TRANSIENT_SRC 0x1e
68 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
69 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
70 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
71 #define MMA8452_TRANSIENT_THS 0x1f
72 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
73 #define MMA8452_TRANSIENT_COUNT 0x20
74 #define MMA8452_TRANSIENT_CHAN_SHIFT 1
75 #define MMA8452_CTRL_REG1 0x2a
76 #define MMA8452_CTRL_ACTIVE BIT(0)
77 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
78 #define MMA8452_CTRL_DR_SHIFT 3
79 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
80 #define MMA8452_CTRL_REG2 0x2b
81 #define MMA8452_CTRL_REG2_RST BIT(6)
82 #define MMA8452_CTRL_REG2_MODS_SHIFT 3
83 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b
84 #define MMA8452_CTRL_REG4 0x2d
85 #define MMA8452_CTRL_REG5 0x2e
86 #define MMA8452_OFF_X 0x2f
87 #define MMA8452_OFF_Y 0x30
88 #define MMA8452_OFF_Z 0x31
89
90 #define MMA8452_MAX_REG 0x31
91
92 #define MMA8452_INT_DRDY BIT(0)
93 #define MMA8452_INT_FF_MT BIT(2)
94 #define MMA8452_INT_TRANS BIT(5)
95
96 #define MMA8451_DEVICE_ID 0x1a
97 #define MMA8452_DEVICE_ID 0x2a
98 #define MMA8453_DEVICE_ID 0x3a
99 #define MMA8652_DEVICE_ID 0x4a
100 #define MMA8653_DEVICE_ID 0x5a
101 #define FXLS8471_DEVICE_ID 0x6a
102
103 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
104
105 struct mma8452_data {
106 struct i2c_client *client;
107 struct mutex lock;
108 struct iio_mount_matrix orientation;
109 u8 ctrl_reg1;
110 u8 data_cfg;
111 const struct mma_chip_info *chip_info;
112 int sleep_val;
113 struct regulator *vdd_reg;
114 struct regulator *vddio_reg;
115
116 /* Ensure correct alignment of time stamp when present */
117 struct {
118 __be16 channels[3];
119 aligned_s64 ts;
120 } buffer;
121 };
122
123 /**
124 * struct mma8452_event_regs - chip specific data related to events
125 * @ev_cfg: event config register address
126 * @ev_cfg_ele: latch bit in event config register
127 * @ev_cfg_chan_shift: number of the bit to enable events in X
128 * direction; in event config register
129 * @ev_src: event source register address
130 * @ev_ths: event threshold register address
131 * @ev_ths_mask: mask for the threshold value
132 * @ev_count: event count (period) register address
133 *
134 * Since not all chips supported by the driver support comparing high pass
135 * filtered data for events (interrupts), different interrupt sources are
136 * used for different chips and the relevant registers are included here.
137 */
138 struct mma8452_event_regs {
139 u8 ev_cfg;
140 u8 ev_cfg_ele;
141 u8 ev_cfg_chan_shift;
142 u8 ev_src;
143 u8 ev_ths;
144 u8 ev_ths_mask;
145 u8 ev_count;
146 };
147
148 static const struct mma8452_event_regs ff_mt_ev_regs = {
149 .ev_cfg = MMA8452_FF_MT_CFG,
150 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
151 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT,
152 .ev_src = MMA8452_FF_MT_SRC,
153 .ev_ths = MMA8452_FF_MT_THS,
154 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
155 .ev_count = MMA8452_FF_MT_COUNT
156 };
157
158 static const struct mma8452_event_regs trans_ev_regs = {
159 .ev_cfg = MMA8452_TRANSIENT_CFG,
160 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
161 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT,
162 .ev_src = MMA8452_TRANSIENT_SRC,
163 .ev_ths = MMA8452_TRANSIENT_THS,
164 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
165 .ev_count = MMA8452_TRANSIENT_COUNT,
166 };
167
168 /**
169 * struct mma_chip_info - chip specific data
170 * @name: part number of device reported via 'name' attr
171 * @chip_id: WHO_AM_I register's value
172 * @channels: struct iio_chan_spec matching the device's
173 * capabilities
174 * @num_channels: number of channels
175 * @mma_scales: scale factors for converting register values
176 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
177 * per mode: m/s^2 and micro m/s^2
178 * @all_events: all events supported by this chip
179 * @enabled_events: event flags enabled and handled by this driver
180 */
181 struct mma_chip_info {
182 const char *name;
183 u8 chip_id;
184 const struct iio_chan_spec *channels;
185 int num_channels;
186 const int mma_scales[3][2];
187 int all_events;
188 int enabled_events;
189 };
190
191 enum {
192 idx_x,
193 idx_y,
194 idx_z,
195 idx_ts,
196 };
197
mma8452_drdy(struct mma8452_data * data)198 static int mma8452_drdy(struct mma8452_data *data)
199 {
200 int tries = 150;
201
202 while (tries-- > 0) {
203 int ret = i2c_smbus_read_byte_data(data->client,
204 MMA8452_STATUS);
205 if (ret < 0)
206 return ret;
207 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
208 return 0;
209
210 if (data->sleep_val <= 20)
211 usleep_range(data->sleep_val * 250,
212 data->sleep_val * 500);
213 else
214 msleep(20);
215 }
216
217 dev_err(&data->client->dev, "data not ready\n");
218
219 return -EIO;
220 }
221
mma8452_set_runtime_pm_state(struct i2c_client * client,bool on)222 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
223 {
224 #ifdef CONFIG_PM
225 int ret;
226
227 if (on) {
228 ret = pm_runtime_resume_and_get(&client->dev);
229 } else {
230 pm_runtime_mark_last_busy(&client->dev);
231 ret = pm_runtime_put_autosuspend(&client->dev);
232 }
233
234 if (ret < 0) {
235 dev_err(&client->dev,
236 "failed to change power state to %d\n", on);
237
238 return ret;
239 }
240 #endif
241
242 return 0;
243 }
244
mma8452_read(struct mma8452_data * data,__be16 buf[3])245 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
246 {
247 int ret = mma8452_drdy(data);
248
249 if (ret < 0)
250 return ret;
251
252 ret = mma8452_set_runtime_pm_state(data->client, true);
253 if (ret)
254 return ret;
255
256 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
257 3 * sizeof(__be16), (u8 *)buf);
258
259 ret = mma8452_set_runtime_pm_state(data->client, false);
260
261 return ret;
262 }
263
mma8452_show_int_plus_micros(char * buf,const int (* vals)[2],int n)264 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
265 int n)
266 {
267 size_t len = 0;
268
269 while (n-- > 0)
270 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
271 vals[n][0], vals[n][1]);
272
273 /* replace trailing space by newline */
274 buf[len - 1] = '\n';
275
276 return len;
277 }
278
mma8452_get_int_plus_micros_index(const int (* vals)[2],int n,int val,int val2)279 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
280 int val, int val2)
281 {
282 while (n-- > 0)
283 if (val == vals[n][0] && val2 == vals[n][1])
284 return n;
285
286 return -EINVAL;
287 }
288
mma8452_get_odr_index(struct mma8452_data * data)289 static unsigned int mma8452_get_odr_index(struct mma8452_data *data)
290 {
291 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
292 MMA8452_CTRL_DR_SHIFT;
293 }
294
295 static const int mma8452_samp_freq[8][2] = {
296 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
297 {6, 250000}, {1, 560000}
298 };
299
300 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
301 static const unsigned int mma8452_time_step_us[4][8] = {
302 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */
303 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */
304 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/
305 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
306 };
307
308 /* Datasheet table "High-Pass Filter Cutoff Options" */
309 static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
310 { /* normal */
311 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
312 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
313 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
314 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
315 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
316 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
317 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
318 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
319 },
320 { /* low noise low power */
321 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
322 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
323 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
324 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
325 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
326 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
327 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
328 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
329 },
330 { /* high resolution */
331 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
332 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
334 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
335 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
336 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
337 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
338 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
339 },
340 { /* low power */
341 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
342 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
343 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
344 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
345 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
346 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
347 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
348 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
349 }
350 };
351
352 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
353 static const u16 mma8452_os_ratio[4][8] = {
354 /* 800 Hz, 400 Hz, ... , 1.56 Hz */
355 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */
356 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */
357 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */
358 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */
359 };
360
mma8452_get_power_mode(struct mma8452_data * data)361 static int mma8452_get_power_mode(struct mma8452_data *data)
362 {
363 int reg;
364
365 reg = i2c_smbus_read_byte_data(data->client,
366 MMA8452_CTRL_REG2);
367 if (reg < 0)
368 return reg;
369
370 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
371 MMA8452_CTRL_REG2_MODS_SHIFT);
372 }
373
mma8452_show_samp_freq_avail(struct device * dev,struct device_attribute * attr,char * buf)374 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
375 struct device_attribute *attr,
376 char *buf)
377 {
378 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
379 ARRAY_SIZE(mma8452_samp_freq));
380 }
381
mma8452_show_scale_avail(struct device * dev,struct device_attribute * attr,char * buf)382 static ssize_t mma8452_show_scale_avail(struct device *dev,
383 struct device_attribute *attr,
384 char *buf)
385 {
386 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
387 struct mma8452_data *data = iio_priv(indio_dev);
388
389 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
390 ARRAY_SIZE(data->chip_info->mma_scales));
391 }
392
mma8452_show_hp_cutoff_avail(struct device * dev,struct device_attribute * attr,char * buf)393 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
394 struct device_attribute *attr,
395 char *buf)
396 {
397 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
398 struct mma8452_data *data = iio_priv(indio_dev);
399 int i, j;
400
401 i = mma8452_get_odr_index(data);
402 j = mma8452_get_power_mode(data);
403 if (j < 0)
404 return j;
405
406 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
407 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
408 }
409
mma8452_show_os_ratio_avail(struct device * dev,struct device_attribute * attr,char * buf)410 static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
411 struct device_attribute *attr,
412 char *buf)
413 {
414 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
415 struct mma8452_data *data = iio_priv(indio_dev);
416 int i = mma8452_get_odr_index(data);
417 int j;
418 u16 val = 0;
419 size_t len = 0;
420
421 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
422 if (val == mma8452_os_ratio[j][i])
423 continue;
424
425 val = mma8452_os_ratio[j][i];
426
427 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
428 }
429 buf[len - 1] = '\n';
430
431 return len;
432 }
433
434 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
435 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444,
436 mma8452_show_scale_avail, NULL, 0);
437 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
438 0444, mma8452_show_hp_cutoff_avail, NULL, 0);
439 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444,
440 mma8452_show_os_ratio_avail, NULL, 0);
441
mma8452_get_samp_freq_index(struct mma8452_data * data,int val,int val2)442 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
443 int val, int val2)
444 {
445 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
446 ARRAY_SIZE(mma8452_samp_freq),
447 val, val2);
448 }
449
mma8452_get_scale_index(struct mma8452_data * data,int val,int val2)450 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
451 {
452 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
453 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
454 }
455
mma8452_get_hp_filter_index(struct mma8452_data * data,int val,int val2)456 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
457 int val, int val2)
458 {
459 int i, j;
460
461 i = mma8452_get_odr_index(data);
462 j = mma8452_get_power_mode(data);
463 if (j < 0)
464 return j;
465
466 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
467 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
468 }
469
mma8452_read_hp_filter(struct mma8452_data * data,int * hz,int * uHz)470 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
471 {
472 int j, i, ret;
473
474 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
475 if (ret < 0)
476 return ret;
477
478 i = mma8452_get_odr_index(data);
479 j = mma8452_get_power_mode(data);
480 if (j < 0)
481 return j;
482
483 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
484 *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
485 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
486
487 return 0;
488 }
489
mma8452_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)490 static int mma8452_read_raw(struct iio_dev *indio_dev,
491 struct iio_chan_spec const *chan,
492 int *val, int *val2, long mask)
493 {
494 struct mma8452_data *data = iio_priv(indio_dev);
495 __be16 buffer[3];
496 int i, ret;
497
498 switch (mask) {
499 case IIO_CHAN_INFO_RAW:
500 ret = iio_device_claim_direct_mode(indio_dev);
501 if (ret)
502 return ret;
503
504 mutex_lock(&data->lock);
505 ret = mma8452_read(data, buffer);
506 mutex_unlock(&data->lock);
507 iio_device_release_direct_mode(indio_dev);
508 if (ret < 0)
509 return ret;
510
511 *val = sign_extend32(be16_to_cpu(
512 buffer[chan->scan_index]) >> chan->scan_type.shift,
513 chan->scan_type.realbits - 1);
514
515 return IIO_VAL_INT;
516 case IIO_CHAN_INFO_SCALE:
517 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
518 *val = data->chip_info->mma_scales[i][0];
519 *val2 = data->chip_info->mma_scales[i][1];
520
521 return IIO_VAL_INT_PLUS_MICRO;
522 case IIO_CHAN_INFO_SAMP_FREQ:
523 i = mma8452_get_odr_index(data);
524 *val = mma8452_samp_freq[i][0];
525 *val2 = mma8452_samp_freq[i][1];
526
527 return IIO_VAL_INT_PLUS_MICRO;
528 case IIO_CHAN_INFO_CALIBBIAS:
529 ret = i2c_smbus_read_byte_data(data->client,
530 MMA8452_OFF_X +
531 chan->scan_index);
532 if (ret < 0)
533 return ret;
534
535 *val = sign_extend32(ret, 7);
536
537 return IIO_VAL_INT;
538 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
539 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
540 ret = mma8452_read_hp_filter(data, val, val2);
541 if (ret < 0)
542 return ret;
543 } else {
544 *val = 0;
545 *val2 = 0;
546 }
547
548 return IIO_VAL_INT_PLUS_MICRO;
549 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
550 ret = mma8452_get_power_mode(data);
551 if (ret < 0)
552 return ret;
553
554 i = mma8452_get_odr_index(data);
555
556 *val = mma8452_os_ratio[ret][i];
557 return IIO_VAL_INT;
558 }
559
560 return -EINVAL;
561 }
562
mma8452_calculate_sleep(struct mma8452_data * data)563 static int mma8452_calculate_sleep(struct mma8452_data *data)
564 {
565 int ret, i = mma8452_get_odr_index(data);
566
567 if (mma8452_samp_freq[i][0] > 0)
568 ret = 1000 / mma8452_samp_freq[i][0];
569 else
570 ret = 1000;
571
572 return ret == 0 ? 1 : ret;
573 }
574
mma8452_standby(struct mma8452_data * data)575 static int mma8452_standby(struct mma8452_data *data)
576 {
577 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
578 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
579 }
580
mma8452_active(struct mma8452_data * data)581 static int mma8452_active(struct mma8452_data *data)
582 {
583 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
584 data->ctrl_reg1);
585 }
586
587 /* returns >0 if active, 0 if in standby and <0 on error */
mma8452_is_active(struct mma8452_data * data)588 static int mma8452_is_active(struct mma8452_data *data)
589 {
590 int reg;
591
592 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
593 if (reg < 0)
594 return reg;
595
596 return reg & MMA8452_CTRL_ACTIVE;
597 }
598
mma8452_change_config(struct mma8452_data * data,u8 reg,u8 val)599 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
600 {
601 int ret;
602 int is_active;
603
604 mutex_lock(&data->lock);
605
606 is_active = mma8452_is_active(data);
607 if (is_active < 0) {
608 ret = is_active;
609 goto fail;
610 }
611
612 /* config can only be changed when in standby */
613 if (is_active > 0) {
614 ret = mma8452_standby(data);
615 if (ret < 0)
616 goto fail;
617 }
618
619 ret = i2c_smbus_write_byte_data(data->client, reg, val);
620 if (ret < 0)
621 goto fail;
622
623 if (is_active > 0) {
624 ret = mma8452_active(data);
625 if (ret < 0)
626 goto fail;
627 }
628
629 ret = 0;
630 fail:
631 mutex_unlock(&data->lock);
632
633 return ret;
634 }
635
mma8452_set_power_mode(struct mma8452_data * data,u8 mode)636 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
637 {
638 int reg;
639
640 reg = i2c_smbus_read_byte_data(data->client,
641 MMA8452_CTRL_REG2);
642 if (reg < 0)
643 return reg;
644
645 reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
646 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
647
648 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
649 }
650
651 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
mma8452_freefall_mode_enabled(struct mma8452_data * data)652 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
653 {
654 int val;
655
656 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
657 if (val < 0)
658 return val;
659
660 return !(val & MMA8452_FF_MT_CFG_OAE);
661 }
662
mma8452_set_freefall_mode(struct mma8452_data * data,bool state)663 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
664 {
665 int val;
666
667 if ((state && mma8452_freefall_mode_enabled(data)) ||
668 (!state && !(mma8452_freefall_mode_enabled(data))))
669 return 0;
670
671 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
672 if (val < 0)
673 return val;
674
675 if (state) {
676 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
677 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
678 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
679 val &= ~MMA8452_FF_MT_CFG_OAE;
680 } else {
681 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
682 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
683 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
684 val |= MMA8452_FF_MT_CFG_OAE;
685 }
686
687 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val);
688 }
689
mma8452_set_hp_filter_frequency(struct mma8452_data * data,int val,int val2)690 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
691 int val, int val2)
692 {
693 int i, reg;
694
695 i = mma8452_get_hp_filter_index(data, val, val2);
696 if (i < 0)
697 return i;
698
699 reg = i2c_smbus_read_byte_data(data->client,
700 MMA8452_HP_FILTER_CUTOFF);
701 if (reg < 0)
702 return reg;
703
704 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
705 reg |= i;
706
707 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
708 }
709
mma8452_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)710 static int mma8452_write_raw(struct iio_dev *indio_dev,
711 struct iio_chan_spec const *chan,
712 int val, int val2, long mask)
713 {
714 struct mma8452_data *data = iio_priv(indio_dev);
715 int i, j, ret;
716
717 ret = iio_device_claim_direct_mode(indio_dev);
718 if (ret)
719 return ret;
720
721 switch (mask) {
722 case IIO_CHAN_INFO_SAMP_FREQ:
723 i = mma8452_get_samp_freq_index(data, val, val2);
724 if (i < 0) {
725 ret = i;
726 break;
727 }
728 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
729 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
730
731 data->sleep_val = mma8452_calculate_sleep(data);
732
733 ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
734 data->ctrl_reg1);
735 break;
736 case IIO_CHAN_INFO_SCALE:
737 i = mma8452_get_scale_index(data, val, val2);
738 if (i < 0) {
739 ret = i;
740 break;
741 }
742
743 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
744 data->data_cfg |= i;
745
746 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
747 data->data_cfg);
748 break;
749 case IIO_CHAN_INFO_CALIBBIAS:
750 if (val < -128 || val > 127) {
751 ret = -EINVAL;
752 break;
753 }
754
755 ret = mma8452_change_config(data,
756 MMA8452_OFF_X + chan->scan_index,
757 val);
758 break;
759
760 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
761 if (val == 0 && val2 == 0) {
762 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
763 } else {
764 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
765 ret = mma8452_set_hp_filter_frequency(data, val, val2);
766 if (ret < 0)
767 break;
768 }
769
770 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
771 data->data_cfg);
772 break;
773
774 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
775 j = mma8452_get_odr_index(data);
776
777 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
778 if (mma8452_os_ratio[i][j] == val) {
779 ret = mma8452_set_power_mode(data, i);
780 break;
781 }
782 }
783 if (i == ARRAY_SIZE(mma8452_os_ratio)) {
784 ret = -EINVAL;
785 break;
786 }
787 break;
788 default:
789 ret = -EINVAL;
790 break;
791 }
792
793 iio_device_release_direct_mode(indio_dev);
794 return ret;
795 }
796
mma8452_get_event_regs(struct mma8452_data * data,const struct iio_chan_spec * chan,enum iio_event_direction dir,const struct mma8452_event_regs ** ev_reg)797 static int mma8452_get_event_regs(struct mma8452_data *data,
798 const struct iio_chan_spec *chan, enum iio_event_direction dir,
799 const struct mma8452_event_regs **ev_reg)
800 {
801 if (!chan)
802 return -EINVAL;
803
804 switch (chan->type) {
805 case IIO_ACCEL:
806 switch (dir) {
807 case IIO_EV_DIR_RISING:
808 if ((data->chip_info->all_events
809 & MMA8452_INT_TRANS) &&
810 (data->chip_info->enabled_events
811 & MMA8452_INT_TRANS))
812 *ev_reg = &trans_ev_regs;
813 else
814 *ev_reg = &ff_mt_ev_regs;
815 return 0;
816 case IIO_EV_DIR_FALLING:
817 *ev_reg = &ff_mt_ev_regs;
818 return 0;
819 default:
820 return -EINVAL;
821 }
822 default:
823 return -EINVAL;
824 }
825 }
826
mma8452_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)827 static int mma8452_read_event_value(struct iio_dev *indio_dev,
828 const struct iio_chan_spec *chan,
829 enum iio_event_type type,
830 enum iio_event_direction dir,
831 enum iio_event_info info,
832 int *val, int *val2)
833 {
834 struct mma8452_data *data = iio_priv(indio_dev);
835 int ret, us, power_mode;
836 const struct mma8452_event_regs *ev_regs;
837
838 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
839 if (ret)
840 return ret;
841
842 switch (info) {
843 case IIO_EV_INFO_VALUE:
844 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths);
845 if (ret < 0)
846 return ret;
847
848 *val = ret & ev_regs->ev_ths_mask;
849
850 return IIO_VAL_INT;
851
852 case IIO_EV_INFO_PERIOD:
853 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count);
854 if (ret < 0)
855 return ret;
856
857 power_mode = mma8452_get_power_mode(data);
858 if (power_mode < 0)
859 return power_mode;
860
861 us = ret * mma8452_time_step_us[power_mode][
862 mma8452_get_odr_index(data)];
863 *val = us / USEC_PER_SEC;
864 *val2 = us % USEC_PER_SEC;
865
866 return IIO_VAL_INT_PLUS_MICRO;
867
868 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
869 ret = i2c_smbus_read_byte_data(data->client,
870 MMA8452_TRANSIENT_CFG);
871 if (ret < 0)
872 return ret;
873
874 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
875 *val = 0;
876 *val2 = 0;
877 } else {
878 ret = mma8452_read_hp_filter(data, val, val2);
879 if (ret < 0)
880 return ret;
881 }
882
883 return IIO_VAL_INT_PLUS_MICRO;
884
885 default:
886 return -EINVAL;
887 }
888 }
889
mma8452_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)890 static int mma8452_write_event_value(struct iio_dev *indio_dev,
891 const struct iio_chan_spec *chan,
892 enum iio_event_type type,
893 enum iio_event_direction dir,
894 enum iio_event_info info,
895 int val, int val2)
896 {
897 struct mma8452_data *data = iio_priv(indio_dev);
898 int ret, reg, steps;
899 const struct mma8452_event_regs *ev_regs;
900
901 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
902 if (ret)
903 return ret;
904
905 switch (info) {
906 case IIO_EV_INFO_VALUE:
907 if (val < 0 || val > ev_regs->ev_ths_mask)
908 return -EINVAL;
909
910 return mma8452_change_config(data, ev_regs->ev_ths, val);
911
912 case IIO_EV_INFO_PERIOD:
913 ret = mma8452_get_power_mode(data);
914 if (ret < 0)
915 return ret;
916
917 steps = (val * USEC_PER_SEC + val2) /
918 mma8452_time_step_us[ret][
919 mma8452_get_odr_index(data)];
920
921 if (steps < 0 || steps > 0xff)
922 return -EINVAL;
923
924 return mma8452_change_config(data, ev_regs->ev_count, steps);
925
926 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
927 reg = i2c_smbus_read_byte_data(data->client,
928 MMA8452_TRANSIENT_CFG);
929 if (reg < 0)
930 return reg;
931
932 if (val == 0 && val2 == 0) {
933 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
934 } else {
935 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
936 ret = mma8452_set_hp_filter_frequency(data, val, val2);
937 if (ret < 0)
938 return ret;
939 }
940
941 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
942
943 default:
944 return -EINVAL;
945 }
946 }
947
mma8452_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)948 static int mma8452_read_event_config(struct iio_dev *indio_dev,
949 const struct iio_chan_spec *chan,
950 enum iio_event_type type,
951 enum iio_event_direction dir)
952 {
953 struct mma8452_data *data = iio_priv(indio_dev);
954 int ret;
955 const struct mma8452_event_regs *ev_regs;
956
957 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
958 if (ret)
959 return ret;
960
961 switch (dir) {
962 case IIO_EV_DIR_FALLING:
963 return mma8452_freefall_mode_enabled(data);
964 case IIO_EV_DIR_RISING:
965 ret = i2c_smbus_read_byte_data(data->client,
966 ev_regs->ev_cfg);
967 if (ret < 0)
968 return ret;
969
970 return !!(ret & BIT(chan->scan_index +
971 ev_regs->ev_cfg_chan_shift));
972 default:
973 return -EINVAL;
974 }
975 }
976
mma8452_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)977 static int mma8452_write_event_config(struct iio_dev *indio_dev,
978 const struct iio_chan_spec *chan,
979 enum iio_event_type type,
980 enum iio_event_direction dir,
981 bool state)
982 {
983 struct mma8452_data *data = iio_priv(indio_dev);
984 int val, ret;
985 const struct mma8452_event_regs *ev_regs;
986
987 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
988 if (ret)
989 return ret;
990
991 ret = mma8452_set_runtime_pm_state(data->client, state);
992 if (ret)
993 return ret;
994
995 switch (dir) {
996 case IIO_EV_DIR_FALLING:
997 return mma8452_set_freefall_mode(data, state);
998 case IIO_EV_DIR_RISING:
999 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg);
1000 if (val < 0)
1001 return val;
1002
1003 if (state) {
1004 if (mma8452_freefall_mode_enabled(data)) {
1005 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift);
1006 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift);
1007 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift);
1008 val |= MMA8452_FF_MT_CFG_OAE;
1009 }
1010 val |= BIT(chan->scan_index +
1011 ev_regs->ev_cfg_chan_shift);
1012 } else {
1013 if (mma8452_freefall_mode_enabled(data))
1014 return 0;
1015
1016 val &= ~BIT(chan->scan_index +
1017 ev_regs->ev_cfg_chan_shift);
1018 }
1019
1020 val |= ev_regs->ev_cfg_ele;
1021
1022 return mma8452_change_config(data, ev_regs->ev_cfg, val);
1023 default:
1024 return -EINVAL;
1025 }
1026 }
1027
mma8452_transient_interrupt(struct iio_dev * indio_dev)1028 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
1029 {
1030 struct mma8452_data *data = iio_priv(indio_dev);
1031 s64 ts = iio_get_time_ns(indio_dev);
1032 int src;
1033
1034 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
1035 if (src < 0)
1036 return;
1037
1038 if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
1039 iio_push_event(indio_dev,
1040 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1041 IIO_EV_TYPE_MAG,
1042 IIO_EV_DIR_RISING),
1043 ts);
1044
1045 if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
1046 iio_push_event(indio_dev,
1047 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
1048 IIO_EV_TYPE_MAG,
1049 IIO_EV_DIR_RISING),
1050 ts);
1051
1052 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
1053 iio_push_event(indio_dev,
1054 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
1055 IIO_EV_TYPE_MAG,
1056 IIO_EV_DIR_RISING),
1057 ts);
1058 }
1059
mma8452_interrupt(int irq,void * p)1060 static irqreturn_t mma8452_interrupt(int irq, void *p)
1061 {
1062 struct iio_dev *indio_dev = p;
1063 struct mma8452_data *data = iio_priv(indio_dev);
1064 irqreturn_t ret = IRQ_NONE;
1065 int src;
1066
1067 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
1068 if (src < 0)
1069 return IRQ_NONE;
1070
1071 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY)))
1072 return IRQ_NONE;
1073
1074 if (src & MMA8452_INT_DRDY) {
1075 iio_trigger_poll_nested(indio_dev->trig);
1076 ret = IRQ_HANDLED;
1077 }
1078
1079 if (src & MMA8452_INT_FF_MT) {
1080 if (mma8452_freefall_mode_enabled(data)) {
1081 s64 ts = iio_get_time_ns(indio_dev);
1082
1083 iio_push_event(indio_dev,
1084 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1085 IIO_MOD_X_AND_Y_AND_Z,
1086 IIO_EV_TYPE_MAG,
1087 IIO_EV_DIR_FALLING),
1088 ts);
1089 }
1090 ret = IRQ_HANDLED;
1091 }
1092
1093 if (src & MMA8452_INT_TRANS) {
1094 mma8452_transient_interrupt(indio_dev);
1095 ret = IRQ_HANDLED;
1096 }
1097
1098 return ret;
1099 }
1100
mma8452_trigger_handler(int irq,void * p)1101 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
1102 {
1103 struct iio_poll_func *pf = p;
1104 struct iio_dev *indio_dev = pf->indio_dev;
1105 struct mma8452_data *data = iio_priv(indio_dev);
1106 int ret;
1107
1108 ret = mma8452_read(data, data->buffer.channels);
1109 if (ret < 0)
1110 goto done;
1111
1112 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
1113 iio_get_time_ns(indio_dev));
1114
1115 done:
1116 iio_trigger_notify_done(indio_dev->trig);
1117
1118 return IRQ_HANDLED;
1119 }
1120
mma8452_reg_access_dbg(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)1121 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1122 unsigned int reg, unsigned int writeval,
1123 unsigned int *readval)
1124 {
1125 int ret;
1126 struct mma8452_data *data = iio_priv(indio_dev);
1127
1128 if (reg > MMA8452_MAX_REG)
1129 return -EINVAL;
1130
1131 if (!readval)
1132 return mma8452_change_config(data, reg, writeval);
1133
1134 ret = i2c_smbus_read_byte_data(data->client, reg);
1135 if (ret < 0)
1136 return ret;
1137
1138 *readval = ret;
1139
1140 return 0;
1141 }
1142
1143 static const struct iio_event_spec mma8452_freefall_event[] = {
1144 {
1145 .type = IIO_EV_TYPE_MAG,
1146 .dir = IIO_EV_DIR_FALLING,
1147 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1148 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1149 BIT(IIO_EV_INFO_PERIOD) |
1150 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1151 },
1152 };
1153
1154 static const struct iio_event_spec mma8652_freefall_event[] = {
1155 {
1156 .type = IIO_EV_TYPE_MAG,
1157 .dir = IIO_EV_DIR_FALLING,
1158 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1159 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1160 BIT(IIO_EV_INFO_PERIOD)
1161 },
1162 };
1163
1164 static const struct iio_event_spec mma8452_transient_event[] = {
1165 {
1166 .type = IIO_EV_TYPE_MAG,
1167 .dir = IIO_EV_DIR_RISING,
1168 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1169 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1170 BIT(IIO_EV_INFO_PERIOD) |
1171 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1172 },
1173 };
1174
1175 static const struct iio_event_spec mma8452_motion_event[] = {
1176 {
1177 .type = IIO_EV_TYPE_MAG,
1178 .dir = IIO_EV_DIR_RISING,
1179 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1180 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1181 BIT(IIO_EV_INFO_PERIOD)
1182 },
1183 };
1184
1185 /*
1186 * Threshold is configured in fixed 8G/127 steps regardless of
1187 * currently selected scale for measurement.
1188 */
1189 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1190
1191 static struct attribute *mma8452_event_attributes[] = {
1192 &iio_const_attr_accel_transient_scale.dev_attr.attr,
1193 NULL,
1194 };
1195
1196 static const struct attribute_group mma8452_event_attribute_group = {
1197 .attrs = mma8452_event_attributes,
1198 };
1199
1200 static const struct iio_mount_matrix *
mma8452_get_mount_matrix(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)1201 mma8452_get_mount_matrix(const struct iio_dev *indio_dev,
1202 const struct iio_chan_spec *chan)
1203 {
1204 struct mma8452_data *data = iio_priv(indio_dev);
1205
1206 return &data->orientation;
1207 }
1208
1209 static const struct iio_chan_spec_ext_info mma8452_ext_info[] = {
1210 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mma8452_get_mount_matrix),
1211 { }
1212 };
1213
1214 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
1215 .type = IIO_ACCEL, \
1216 .modified = 1, \
1217 .channel2 = modifier, \
1218 .scan_index = -1, \
1219 .event_spec = mma8452_freefall_event, \
1220 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1221 }
1222
1223 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
1224 .type = IIO_ACCEL, \
1225 .modified = 1, \
1226 .channel2 = modifier, \
1227 .scan_index = -1, \
1228 .event_spec = mma8652_freefall_event, \
1229 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1230 }
1231
1232 #define MMA8452_CHANNEL(axis, idx, bits) { \
1233 .type = IIO_ACCEL, \
1234 .modified = 1, \
1235 .channel2 = IIO_MOD_##axis, \
1236 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1237 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1238 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1239 BIT(IIO_CHAN_INFO_SCALE) | \
1240 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1241 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1242 .scan_index = idx, \
1243 .scan_type = { \
1244 .sign = 's', \
1245 .realbits = (bits), \
1246 .storagebits = 16, \
1247 .shift = 16 - (bits), \
1248 .endianness = IIO_BE, \
1249 }, \
1250 .event_spec = mma8452_transient_event, \
1251 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1252 .ext_info = mma8452_ext_info, \
1253 }
1254
1255 #define MMA8652_CHANNEL(axis, idx, bits) { \
1256 .type = IIO_ACCEL, \
1257 .modified = 1, \
1258 .channel2 = IIO_MOD_##axis, \
1259 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1260 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1261 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1262 BIT(IIO_CHAN_INFO_SCALE) | \
1263 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1264 .scan_index = idx, \
1265 .scan_type = { \
1266 .sign = 's', \
1267 .realbits = (bits), \
1268 .storagebits = 16, \
1269 .shift = 16 - (bits), \
1270 .endianness = IIO_BE, \
1271 }, \
1272 .event_spec = mma8452_motion_event, \
1273 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1274 .ext_info = mma8452_ext_info, \
1275 }
1276
1277 static const struct iio_chan_spec mma8451_channels[] = {
1278 MMA8452_CHANNEL(X, idx_x, 14),
1279 MMA8452_CHANNEL(Y, idx_y, 14),
1280 MMA8452_CHANNEL(Z, idx_z, 14),
1281 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1282 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1283 };
1284
1285 static const struct iio_chan_spec mma8452_channels[] = {
1286 MMA8452_CHANNEL(X, idx_x, 12),
1287 MMA8452_CHANNEL(Y, idx_y, 12),
1288 MMA8452_CHANNEL(Z, idx_z, 12),
1289 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1290 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1291 };
1292
1293 static const struct iio_chan_spec mma8453_channels[] = {
1294 MMA8452_CHANNEL(X, idx_x, 10),
1295 MMA8452_CHANNEL(Y, idx_y, 10),
1296 MMA8452_CHANNEL(Z, idx_z, 10),
1297 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1298 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1299 };
1300
1301 static const struct iio_chan_spec mma8652_channels[] = {
1302 MMA8652_CHANNEL(X, idx_x, 12),
1303 MMA8652_CHANNEL(Y, idx_y, 12),
1304 MMA8652_CHANNEL(Z, idx_z, 12),
1305 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1306 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1307 };
1308
1309 static const struct iio_chan_spec mma8653_channels[] = {
1310 MMA8652_CHANNEL(X, idx_x, 10),
1311 MMA8652_CHANNEL(Y, idx_y, 10),
1312 MMA8652_CHANNEL(Z, idx_z, 10),
1313 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1314 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1315 };
1316
1317 enum {
1318 mma8451,
1319 mma8452,
1320 mma8453,
1321 mma8652,
1322 mma8653,
1323 fxls8471,
1324 };
1325
1326 static const struct mma_chip_info mma_chip_info_table[] = {
1327 [mma8451] = {
1328 .name = "mma8451",
1329 .chip_id = MMA8451_DEVICE_ID,
1330 .channels = mma8451_channels,
1331 .num_channels = ARRAY_SIZE(mma8451_channels),
1332 /*
1333 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1334 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1335 * bit.
1336 * The userspace interface uses m/s^2 and we declare micro units
1337 * So scale factor for 12 bit here is given by:
1338 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1339 */
1340 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1341 /*
1342 * Although we enable the interrupt sources once and for
1343 * all here the event detection itself is not enabled until
1344 * userspace asks for it by mma8452_write_event_config()
1345 */
1346 .all_events = MMA8452_INT_DRDY |
1347 MMA8452_INT_TRANS |
1348 MMA8452_INT_FF_MT,
1349 .enabled_events = MMA8452_INT_TRANS |
1350 MMA8452_INT_FF_MT,
1351 },
1352 [mma8452] = {
1353 .name = "mma8452",
1354 .chip_id = MMA8452_DEVICE_ID,
1355 .channels = mma8452_channels,
1356 .num_channels = ARRAY_SIZE(mma8452_channels),
1357 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1358 /*
1359 * Although we enable the interrupt sources once and for
1360 * all here the event detection itself is not enabled until
1361 * userspace asks for it by mma8452_write_event_config()
1362 */
1363 .all_events = MMA8452_INT_DRDY |
1364 MMA8452_INT_TRANS |
1365 MMA8452_INT_FF_MT,
1366 .enabled_events = MMA8452_INT_TRANS |
1367 MMA8452_INT_FF_MT,
1368 },
1369 [mma8453] = {
1370 .name = "mma8453",
1371 .chip_id = MMA8453_DEVICE_ID,
1372 .channels = mma8453_channels,
1373 .num_channels = ARRAY_SIZE(mma8453_channels),
1374 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1375 /*
1376 * Although we enable the interrupt sources once and for
1377 * all here the event detection itself is not enabled until
1378 * userspace asks for it by mma8452_write_event_config()
1379 */
1380 .all_events = MMA8452_INT_DRDY |
1381 MMA8452_INT_TRANS |
1382 MMA8452_INT_FF_MT,
1383 .enabled_events = MMA8452_INT_TRANS |
1384 MMA8452_INT_FF_MT,
1385 },
1386 [mma8652] = {
1387 .name = "mma8652",
1388 .chip_id = MMA8652_DEVICE_ID,
1389 .channels = mma8652_channels,
1390 .num_channels = ARRAY_SIZE(mma8652_channels),
1391 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1392 .all_events = MMA8452_INT_DRDY |
1393 MMA8452_INT_FF_MT,
1394 .enabled_events = MMA8452_INT_FF_MT,
1395 },
1396 [mma8653] = {
1397 .name = "mma8653",
1398 .chip_id = MMA8653_DEVICE_ID,
1399 .channels = mma8653_channels,
1400 .num_channels = ARRAY_SIZE(mma8653_channels),
1401 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1402 /*
1403 * Although we enable the interrupt sources once and for
1404 * all here the event detection itself is not enabled until
1405 * userspace asks for it by mma8452_write_event_config()
1406 */
1407 .all_events = MMA8452_INT_DRDY |
1408 MMA8452_INT_FF_MT,
1409 .enabled_events = MMA8452_INT_FF_MT,
1410 },
1411 [fxls8471] = {
1412 .name = "fxls8471",
1413 .chip_id = FXLS8471_DEVICE_ID,
1414 .channels = mma8451_channels,
1415 .num_channels = ARRAY_SIZE(mma8451_channels),
1416 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1417 /*
1418 * Although we enable the interrupt sources once and for
1419 * all here the event detection itself is not enabled until
1420 * userspace asks for it by mma8452_write_event_config()
1421 */
1422 .all_events = MMA8452_INT_DRDY |
1423 MMA8452_INT_TRANS |
1424 MMA8452_INT_FF_MT,
1425 .enabled_events = MMA8452_INT_TRANS |
1426 MMA8452_INT_FF_MT,
1427 },
1428 };
1429
1430 static struct attribute *mma8452_attributes[] = {
1431 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1432 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1433 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1434 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1435 NULL
1436 };
1437
1438 static const struct attribute_group mma8452_group = {
1439 .attrs = mma8452_attributes,
1440 };
1441
1442 static const struct iio_info mma8452_info = {
1443 .attrs = &mma8452_group,
1444 .read_raw = &mma8452_read_raw,
1445 .write_raw = &mma8452_write_raw,
1446 .event_attrs = &mma8452_event_attribute_group,
1447 .read_event_value = &mma8452_read_event_value,
1448 .write_event_value = &mma8452_write_event_value,
1449 .read_event_config = &mma8452_read_event_config,
1450 .write_event_config = &mma8452_write_event_config,
1451 .debugfs_reg_access = &mma8452_reg_access_dbg,
1452 };
1453
1454 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1455
mma8452_data_rdy_trigger_set_state(struct iio_trigger * trig,bool state)1456 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1457 bool state)
1458 {
1459 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1460 struct mma8452_data *data = iio_priv(indio_dev);
1461 int reg, ret;
1462
1463 ret = mma8452_set_runtime_pm_state(data->client, state);
1464 if (ret)
1465 return ret;
1466
1467 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1468 if (reg < 0)
1469 return reg;
1470
1471 if (state)
1472 reg |= MMA8452_INT_DRDY;
1473 else
1474 reg &= ~MMA8452_INT_DRDY;
1475
1476 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1477 }
1478
1479 static const struct iio_trigger_ops mma8452_trigger_ops = {
1480 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1481 .validate_device = iio_trigger_validate_own_device,
1482 };
1483
mma8452_trigger_setup(struct iio_dev * indio_dev)1484 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1485 {
1486 struct mma8452_data *data = iio_priv(indio_dev);
1487 struct iio_trigger *trig;
1488 int ret;
1489
1490 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1491 indio_dev->name,
1492 iio_device_id(indio_dev));
1493 if (!trig)
1494 return -ENOMEM;
1495
1496 trig->ops = &mma8452_trigger_ops;
1497 iio_trigger_set_drvdata(trig, indio_dev);
1498
1499 ret = iio_trigger_register(trig);
1500 if (ret)
1501 return ret;
1502
1503 indio_dev->trig = iio_trigger_get(trig);
1504
1505 return 0;
1506 }
1507
mma8452_trigger_cleanup(struct iio_dev * indio_dev)1508 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1509 {
1510 if (indio_dev->trig)
1511 iio_trigger_unregister(indio_dev->trig);
1512 }
1513
mma8452_reset(struct i2c_client * client)1514 static int mma8452_reset(struct i2c_client *client)
1515 {
1516 int i;
1517 int ret;
1518
1519 /*
1520 * Find on fxls8471, after config reset bit, it reset immediately,
1521 * and will not give ACK, so here do not check the return value.
1522 * The following code will read the reset register, and check whether
1523 * this reset works.
1524 */
1525 i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1526 MMA8452_CTRL_REG2_RST);
1527
1528 for (i = 0; i < 10; i++) {
1529 usleep_range(100, 200);
1530 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1531 if (ret == -EIO)
1532 continue; /* I2C comm reset */
1533 if (ret < 0)
1534 return ret;
1535 if (!(ret & MMA8452_CTRL_REG2_RST))
1536 return 0;
1537 }
1538
1539 return -ETIMEDOUT;
1540 }
1541
1542 static const struct of_device_id mma8452_dt_ids[] = {
1543 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1544 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1545 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1546 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1547 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1548 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1549 { }
1550 };
1551 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1552
mma8452_probe(struct i2c_client * client)1553 static int mma8452_probe(struct i2c_client *client)
1554 {
1555 struct mma8452_data *data;
1556 struct iio_dev *indio_dev;
1557 int ret;
1558
1559 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1560 if (!indio_dev)
1561 return -ENOMEM;
1562
1563 data = iio_priv(indio_dev);
1564 data->client = client;
1565 mutex_init(&data->lock);
1566
1567 data->chip_info = i2c_get_match_data(client);
1568 if (!data->chip_info)
1569 return dev_err_probe(&client->dev, -ENODEV,
1570 "unknown device model\n");
1571
1572 ret = iio_read_mount_matrix(&client->dev, &data->orientation);
1573 if (ret)
1574 return ret;
1575
1576 data->vdd_reg = devm_regulator_get(&client->dev, "vdd");
1577 if (IS_ERR(data->vdd_reg))
1578 return dev_err_probe(&client->dev, PTR_ERR(data->vdd_reg),
1579 "failed to get VDD regulator!\n");
1580
1581 data->vddio_reg = devm_regulator_get(&client->dev, "vddio");
1582 if (IS_ERR(data->vddio_reg))
1583 return dev_err_probe(&client->dev, PTR_ERR(data->vddio_reg),
1584 "failed to get VDDIO regulator!\n");
1585
1586 ret = regulator_enable(data->vdd_reg);
1587 if (ret) {
1588 dev_err(&client->dev, "failed to enable VDD regulator!\n");
1589 return ret;
1590 }
1591
1592 ret = regulator_enable(data->vddio_reg);
1593 if (ret) {
1594 dev_err(&client->dev, "failed to enable VDDIO regulator!\n");
1595 goto disable_regulator_vdd;
1596 }
1597
1598 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1599 if (ret < 0)
1600 goto disable_regulators;
1601
1602 switch (ret) {
1603 case MMA8451_DEVICE_ID:
1604 case MMA8452_DEVICE_ID:
1605 case MMA8453_DEVICE_ID:
1606 case MMA8652_DEVICE_ID:
1607 case MMA8653_DEVICE_ID:
1608 case FXLS8471_DEVICE_ID:
1609 if (ret == data->chip_info->chip_id)
1610 break;
1611 fallthrough;
1612 default:
1613 ret = -ENODEV;
1614 goto disable_regulators;
1615 }
1616
1617 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1618 data->chip_info->name, data->chip_info->chip_id);
1619
1620 i2c_set_clientdata(client, indio_dev);
1621 indio_dev->info = &mma8452_info;
1622 indio_dev->name = data->chip_info->name;
1623 indio_dev->modes = INDIO_DIRECT_MODE;
1624 indio_dev->channels = data->chip_info->channels;
1625 indio_dev->num_channels = data->chip_info->num_channels;
1626 indio_dev->available_scan_masks = mma8452_scan_masks;
1627
1628 ret = mma8452_reset(client);
1629 if (ret < 0)
1630 goto disable_regulators;
1631
1632 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1633 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1634 data->data_cfg);
1635 if (ret < 0)
1636 goto disable_regulators;
1637
1638 /*
1639 * By default set transient threshold to max to avoid events if
1640 * enabling without configuring threshold.
1641 */
1642 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1643 MMA8452_TRANSIENT_THS_MASK);
1644 if (ret < 0)
1645 goto disable_regulators;
1646
1647 if (client->irq) {
1648 int irq2;
1649
1650 irq2 = fwnode_irq_get_byname(dev_fwnode(&client->dev), "INT2");
1651
1652 if (irq2 == client->irq) {
1653 dev_dbg(&client->dev, "using interrupt line INT2\n");
1654 } else {
1655 ret = i2c_smbus_write_byte_data(client,
1656 MMA8452_CTRL_REG5,
1657 data->chip_info->all_events);
1658 if (ret < 0)
1659 goto disable_regulators;
1660
1661 dev_dbg(&client->dev, "using interrupt line INT1\n");
1662 }
1663
1664 ret = i2c_smbus_write_byte_data(client,
1665 MMA8452_CTRL_REG4,
1666 data->chip_info->enabled_events);
1667 if (ret < 0)
1668 goto disable_regulators;
1669
1670 ret = mma8452_trigger_setup(indio_dev);
1671 if (ret < 0)
1672 goto disable_regulators;
1673 }
1674
1675 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1676 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1677
1678 data->sleep_val = mma8452_calculate_sleep(data);
1679
1680 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1681 data->ctrl_reg1);
1682 if (ret < 0)
1683 goto trigger_cleanup;
1684
1685 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1686 mma8452_trigger_handler, NULL);
1687 if (ret < 0)
1688 goto trigger_cleanup;
1689
1690 if (client->irq) {
1691 ret = devm_request_threaded_irq(&client->dev,
1692 client->irq,
1693 NULL, mma8452_interrupt,
1694 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1695 client->name, indio_dev);
1696 if (ret)
1697 goto buffer_cleanup;
1698 }
1699
1700 ret = pm_runtime_set_active(&client->dev);
1701 if (ret < 0)
1702 goto buffer_cleanup;
1703
1704 pm_runtime_enable(&client->dev);
1705 pm_runtime_set_autosuspend_delay(&client->dev,
1706 MMA8452_AUTO_SUSPEND_DELAY_MS);
1707 pm_runtime_use_autosuspend(&client->dev);
1708
1709 ret = iio_device_register(indio_dev);
1710 if (ret < 0)
1711 goto buffer_cleanup;
1712
1713 ret = mma8452_set_freefall_mode(data, false);
1714 if (ret < 0)
1715 goto unregister_device;
1716
1717 return 0;
1718
1719 unregister_device:
1720 iio_device_unregister(indio_dev);
1721
1722 buffer_cleanup:
1723 iio_triggered_buffer_cleanup(indio_dev);
1724
1725 trigger_cleanup:
1726 mma8452_trigger_cleanup(indio_dev);
1727
1728 disable_regulators:
1729 regulator_disable(data->vddio_reg);
1730
1731 disable_regulator_vdd:
1732 regulator_disable(data->vdd_reg);
1733
1734 return ret;
1735 }
1736
mma8452_remove(struct i2c_client * client)1737 static void mma8452_remove(struct i2c_client *client)
1738 {
1739 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1740 struct mma8452_data *data = iio_priv(indio_dev);
1741
1742 iio_device_unregister(indio_dev);
1743
1744 pm_runtime_disable(&client->dev);
1745 pm_runtime_set_suspended(&client->dev);
1746
1747 iio_triggered_buffer_cleanup(indio_dev);
1748 mma8452_trigger_cleanup(indio_dev);
1749 mma8452_standby(iio_priv(indio_dev));
1750
1751 regulator_disable(data->vddio_reg);
1752 regulator_disable(data->vdd_reg);
1753 }
1754
1755 #ifdef CONFIG_PM
mma8452_runtime_suspend(struct device * dev)1756 static int mma8452_runtime_suspend(struct device *dev)
1757 {
1758 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1759 struct mma8452_data *data = iio_priv(indio_dev);
1760 int ret;
1761
1762 mutex_lock(&data->lock);
1763 ret = mma8452_standby(data);
1764 mutex_unlock(&data->lock);
1765 if (ret < 0) {
1766 dev_err(&data->client->dev, "powering off device failed\n");
1767 return -EAGAIN;
1768 }
1769
1770 ret = regulator_disable(data->vddio_reg);
1771 if (ret) {
1772 dev_err(dev, "failed to disable VDDIO regulator\n");
1773 return ret;
1774 }
1775
1776 ret = regulator_disable(data->vdd_reg);
1777 if (ret) {
1778 dev_err(dev, "failed to disable VDD regulator\n");
1779 return ret;
1780 }
1781
1782 return 0;
1783 }
1784
mma8452_runtime_resume(struct device * dev)1785 static int mma8452_runtime_resume(struct device *dev)
1786 {
1787 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1788 struct mma8452_data *data = iio_priv(indio_dev);
1789 int ret, sleep_val;
1790
1791 ret = regulator_enable(data->vdd_reg);
1792 if (ret) {
1793 dev_err(dev, "failed to enable VDD regulator\n");
1794 return ret;
1795 }
1796
1797 ret = regulator_enable(data->vddio_reg);
1798 if (ret) {
1799 dev_err(dev, "failed to enable VDDIO regulator\n");
1800 regulator_disable(data->vdd_reg);
1801 return ret;
1802 }
1803
1804 ret = mma8452_active(data);
1805 if (ret < 0)
1806 goto runtime_resume_failed;
1807
1808 ret = mma8452_get_odr_index(data);
1809 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1810 if (sleep_val < 20)
1811 usleep_range(sleep_val * 1000, 20000);
1812 else
1813 msleep_interruptible(sleep_val);
1814
1815 return 0;
1816
1817 runtime_resume_failed:
1818 regulator_disable(data->vddio_reg);
1819 regulator_disable(data->vdd_reg);
1820
1821 return ret;
1822 }
1823 #endif
1824
1825 static const struct dev_pm_ops mma8452_pm_ops = {
1826 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1827 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1828 mma8452_runtime_resume, NULL)
1829 };
1830
1831 static const struct i2c_device_id mma8452_id[] = {
1832 { "fxls8471", (kernel_ulong_t)&mma_chip_info_table[fxls8471] },
1833 { "mma8451", (kernel_ulong_t)&mma_chip_info_table[mma8451] },
1834 { "mma8452", (kernel_ulong_t)&mma_chip_info_table[mma8452] },
1835 { "mma8453", (kernel_ulong_t)&mma_chip_info_table[mma8453] },
1836 { "mma8652", (kernel_ulong_t)&mma_chip_info_table[mma8652] },
1837 { "mma8653", (kernel_ulong_t)&mma_chip_info_table[mma8653] },
1838 { }
1839 };
1840 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1841
1842 static struct i2c_driver mma8452_driver = {
1843 .driver = {
1844 .name = "mma8452",
1845 .of_match_table = mma8452_dt_ids,
1846 .pm = &mma8452_pm_ops,
1847 },
1848 .probe = mma8452_probe,
1849 .remove = mma8452_remove,
1850 .id_table = mma8452_id,
1851 };
1852 module_i2c_driver(mma8452_driver);
1853
1854 MODULE_AUTHOR("Peter Meerwald <[email protected]>");
1855 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1856 MODULE_LICENSE("GPL");
1857