1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD7770, AD7771, AD7779 ADC
4 *
5 * Copyright 2023-2024 Analog Devices Inc.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bitmap.h>
10 #include <linux/clk.h>
11 #include <linux/crc8.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/math.h>
18 #include <linux/module.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/spi/spi.h>
22 #include <linux/string.h>
23 #include <linux/types.h>
24 #include <linux/unaligned.h>
25 #include <linux/units.h>
26
27 #include <linux/iio/iio.h>
28 #include <linux/iio/buffer.h>
29 #include <linux/iio/sysfs.h>
30 #include <linux/iio/trigger.h>
31 #include <linux/iio/triggered_buffer.h>
32 #include <linux/iio/trigger_consumer.h>
33
34 #define AD7779_SPI_READ_CMD BIT(7)
35
36 #define AD7779_DISABLE_SD BIT(7)
37
38 #define AD7779_REG_CH_DISABLE 0x08
39 #define AD7779_REG_CH_SYNC_OFFSET(ch) (0x09 + (ch))
40 #define AD7779_REG_CH_CONFIG(ch) (0x00 + (ch))
41 #define AD7779_REG_GENERAL_USER_CONFIG_1 0x11
42 #define AD7779_REG_GENERAL_USER_CONFIG_2 0x12
43 #define AD7779_REG_GENERAL_USER_CONFIG_3 0x13
44 #define AD7779_REG_DOUT_FORMAT 0x14
45 #define AD7779_REG_ADC_MUX_CONFIG 0x15
46 #define AD7779_REG_GPIO_CONFIG 0x17
47 #define AD7779_REG_BUFFER_CONFIG_1 0x19
48 #define AD7779_REG_GLOBAL_MUX_CONFIG 0x16
49 #define AD7779_REG_BUFFER_CONFIG_2 0x1A
50 #define AD7779_REG_GPIO_DATA 0x18
51 #define AD7779_REG_CH_OFFSET_UPPER_BYTE(ch) (0x1C + (ch) * 6)
52 #define AD7779_REG_CH_OFFSET_LOWER_BYTE(ch) (0x1E + (ch) * 6)
53 #define AD7779_REG_CH_GAIN_UPPER_BYTE(ch) (0x1F + (ch) * 6)
54 #define AD7779_REG_CH_OFFSET_MID_BYTE(ch) (0x1D + (ch) * 6)
55 #define AD7779_REG_CH_GAIN_MID_BYTE(ch) (0x20 + (ch) * 6)
56 #define AD7779_REG_CH_ERR_REG(ch) (0x4C + (ch))
57 #define AD7779_REG_CH0_1_SAT_ERR 0x54
58 #define AD7779_REG_CH_GAIN_LOWER_BYTE(ch) (0x21 + (ch) * 6)
59 #define AD7779_REG_CH2_3_SAT_ERR 0x55
60 #define AD7779_REG_CH4_5_SAT_ERR 0x56
61 #define AD7779_REG_CH6_7_SAT_ERR 0x57
62 #define AD7779_REG_CHX_ERR_REG_EN 0x58
63 #define AD7779_REG_GEN_ERR_REG_1 0x59
64 #define AD7779_REG_GEN_ERR_REG_1_EN 0x5A
65 #define AD7779_REG_GEN_ERR_REG_2 0x5B
66 #define AD7779_REG_GEN_ERR_REG_2_EN 0x5C
67 #define AD7779_REG_STATUS_REG_1 0x5D
68 #define AD7779_REG_STATUS_REG_2 0x5E
69 #define AD7779_REG_STATUS_REG_3 0x5F
70 #define AD7779_REG_SRC_N_MSB 0x60
71 #define AD7779_REG_SRC_N_LSB 0x61
72 #define AD7779_REG_SRC_IF_MSB 0x62
73 #define AD7779_REG_SRC_IF_LSB 0x63
74 #define AD7779_REG_SRC_UPDATE 0x64
75
76 #define AD7779_FILTER_MSK BIT(6)
77 #define AD7779_MOD_POWERMODE_MSK BIT(6)
78 #define AD7779_MOD_PDB_REFOUT_MSK BIT(4)
79 #define AD7779_MOD_SPI_EN_MSK BIT(4)
80 #define AD7779_USRMOD_INIT_MSK GENMASK(6, 4)
81
82 /* AD7779_REG_DOUT_FORMAT */
83 #define AD7779_DOUT_FORMAT_MSK GENMASK(7, 6)
84 #define AD7779_DOUT_HEADER_FORMAT BIT(5)
85 #define AD7779_DCLK_CLK_DIV_MSK GENMASK(3, 1)
86
87 #define AD7779_REFMUX_CTRL_MSK GENMASK(7, 6)
88 #define AD7779_SPI_CRC_EN_MSK BIT(0)
89
90 #define AD7779_MAXCLK_LOWPOWER (4096 * HZ_PER_KHZ)
91 #define AD7779_NUM_CHANNELS 8
92 #define AD7779_RESET_BUF_SIZE 8
93 #define AD7779_CHAN_DATA_SIZE 4
94
95 #define AD7779_LOWPOWER_DIV 512
96 #define AD7779_HIGHPOWER_DIV 2048
97
98 #define AD7779_SINC3_MAXFREQ (16 * HZ_PER_KHZ)
99 #define AD7779_SINC5_MAXFREQ (128 * HZ_PER_KHZ)
100
101 #define AD7779_DEFAULT_SAMPLING_FREQ (8 * HZ_PER_KHZ)
102 #define AD7779_DEFAULT_SAMPLING_2LINE (4 * HZ_PER_KHZ)
103 #define AD7779_DEFAULT_SAMPLING_1LINE (2 * HZ_PER_KHZ)
104
105 #define AD7779_SPIMODE_MAX_SAMP_FREQ (16 * HZ_PER_KHZ)
106
107 #define GAIN_REL 0x555555
108 #define AD7779_FREQ_MSB_MSK GENMASK(15, 8)
109 #define AD7779_FREQ_LSB_MSK GENMASK(7, 0)
110 #define AD7779_UPPER GENMASK(23, 16)
111 #define AD7779_MID GENMASK(15, 8)
112 #define AD7779_LOWER GENMASK(7, 0)
113
114 #define AD7779_REG_MSK GENMASK(6, 0)
115
116 #define AD7779_CRC8_POLY 0x07
117 DECLARE_CRC8_TABLE(ad7779_crc8_table);
118
119 enum ad7779_filter {
120 AD7779_SINC3,
121 AD7779_SINC5,
122 };
123
124 enum ad7779_variant {
125 ad7770,
126 ad7771,
127 ad7779,
128 };
129
130 enum ad7779_power_mode {
131 AD7779_LOW_POWER,
132 AD7779_HIGH_POWER,
133 };
134
135 struct ad7779_chip_info {
136 const char *name;
137 struct iio_chan_spec const *channels;
138 };
139
140 struct ad7779_state {
141 struct spi_device *spi;
142 const struct ad7779_chip_info *chip_info;
143 struct clk *mclk;
144 struct iio_trigger *trig;
145 struct completion completion;
146 unsigned int sampling_freq;
147 enum ad7779_filter filter_enabled;
148 /*
149 * DMA (thus cache coherency maintenance) requires the
150 * transfer buffers to live in their own cache lines.
151 */
152 struct {
153 u32 chans[8];
154 aligned_s64 timestamp;
155 } data __aligned(IIO_DMA_MINALIGN);
156 u32 spidata_tx[8];
157 u8 reg_rx_buf[3];
158 u8 reg_tx_buf[3];
159 u8 reset_buf[8];
160 };
161
162 static const char * const ad7779_filter_type[] = {
163 [AD7779_SINC3] = "sinc3",
164 [AD7779_SINC5] = "sinc5",
165 };
166
167 static const char * const ad7779_power_supplies[] = {
168 "avdd1", "avdd2", "avdd4",
169 };
170
ad7779_spi_read(struct ad7779_state * st,u8 reg,u8 * rbuf)171 static int ad7779_spi_read(struct ad7779_state *st, u8 reg, u8 *rbuf)
172 {
173 int ret;
174 u8 crc_buf[2];
175 u8 exp_crc;
176 struct spi_transfer t = {
177 .tx_buf = st->reg_tx_buf,
178 .rx_buf = st->reg_rx_buf,
179 };
180
181 st->reg_tx_buf[0] = AD7779_SPI_READ_CMD | FIELD_GET(AD7779_REG_MSK, reg);
182 st->reg_tx_buf[1] = 0;
183
184 if (reg == AD7779_REG_GEN_ERR_REG_1_EN) {
185 t.len = 2;
186 } else {
187 t.len = 3;
188 st->reg_tx_buf[2] = crc8(ad7779_crc8_table, st->reg_tx_buf,
189 t.len - 1, 0);
190 }
191
192 ret = spi_sync_transfer(st->spi, &t, 1);
193 if (ret)
194 return ret;
195
196 crc_buf[0] = AD7779_SPI_READ_CMD | FIELD_GET(AD7779_REG_MSK, reg);
197 crc_buf[1] = st->reg_rx_buf[1];
198 exp_crc = crc8(ad7779_crc8_table, crc_buf, ARRAY_SIZE(crc_buf), 0);
199 if (reg != AD7779_REG_GEN_ERR_REG_1_EN && exp_crc != st->reg_rx_buf[2]) {
200 dev_err(&st->spi->dev, "Bad CRC %x, expected %x",
201 st->reg_rx_buf[2], exp_crc);
202 return -EINVAL;
203 }
204 *rbuf = st->reg_rx_buf[1];
205
206 return 0;
207 }
208
ad7779_spi_write(struct ad7779_state * st,u8 reg,u8 val)209 static int ad7779_spi_write(struct ad7779_state *st, u8 reg, u8 val)
210 {
211 u8 length = 3;
212
213 st->reg_tx_buf[0] = FIELD_GET(AD7779_REG_MSK, reg);
214 st->reg_tx_buf[1] = val;
215 if (reg == AD7779_REG_GEN_ERR_REG_1_EN)
216 length = 2;
217 else
218 st->reg_tx_buf[2] = crc8(ad7779_crc8_table, st->reg_tx_buf,
219 length - 1, 0);
220
221 return spi_write(st->spi, st->reg_tx_buf, length);
222 }
223
ad7779_spi_write_mask(struct ad7779_state * st,u8 reg,u8 mask,u8 val)224 static int ad7779_spi_write_mask(struct ad7779_state *st, u8 reg, u8 mask,
225 u8 val)
226 {
227 int ret;
228 u8 regval, data;
229
230 ret = ad7779_spi_read(st, reg, &data);
231 if (ret)
232 return ret;
233
234 regval = (data & ~mask) | (val & mask);
235
236 if (regval == data)
237 return 0;
238
239 return ad7779_spi_write(st, reg, regval);
240 }
241
ad7779_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)242 static int ad7779_reg_access(struct iio_dev *indio_dev,
243 unsigned int reg,
244 unsigned int writeval,
245 unsigned int *readval)
246 {
247 struct ad7779_state *st = iio_priv(indio_dev);
248 u8 rval;
249 int ret;
250
251 if (readval) {
252 ret = ad7779_spi_read(st, reg, &rval);
253 *readval = rval;
254 return ret;
255 }
256
257 return ad7779_spi_write(st, reg, writeval);
258 }
259
ad7779_set_sampling_frequency(struct ad7779_state * st,unsigned int sampling_freq)260 static int ad7779_set_sampling_frequency(struct ad7779_state *st,
261 unsigned int sampling_freq)
262 {
263 int ret;
264 unsigned int dec;
265 unsigned int frac;
266 unsigned int div;
267 unsigned int decimal;
268 unsigned int freq_khz;
269
270 if (st->filter_enabled == AD7779_SINC3 &&
271 sampling_freq > AD7779_SINC3_MAXFREQ)
272 return -EINVAL;
273
274 if (st->filter_enabled == AD7779_SINC5 &&
275 sampling_freq > AD7779_SINC5_MAXFREQ)
276 return -EINVAL;
277
278 if (sampling_freq > AD7779_SPIMODE_MAX_SAMP_FREQ)
279 return -EINVAL;
280
281 div = AD7779_HIGHPOWER_DIV;
282
283 freq_khz = sampling_freq / HZ_PER_KHZ;
284 dec = div / freq_khz;
285 frac = div % freq_khz;
286
287 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_MSB,
288 FIELD_GET(AD7779_FREQ_MSB_MSK, dec));
289 if (ret)
290 return ret;
291 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_LSB,
292 FIELD_GET(AD7779_FREQ_LSB_MSK, dec));
293 if (ret)
294 return ret;
295
296 if (frac) {
297 /*
298 * In order to obtain the first three decimals of the decimation
299 * the initial number is multiplied with 10^3 prior to the
300 * division, then the original division result is subtracted and
301 * the number is divided by 10^3.
302 */
303 decimal = ((mult_frac(div, KILO, freq_khz) - dec * KILO) << 16)
304 / KILO;
305 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_MSB,
306 FIELD_GET(AD7779_FREQ_MSB_MSK, decimal));
307 if (ret)
308 return ret;
309 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_LSB,
310 FIELD_GET(AD7779_FREQ_LSB_MSK, decimal));
311 if (ret)
312 return ret;
313 } else {
314 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_MSB,
315 FIELD_GET(AD7779_FREQ_MSB_MSK, 0x0));
316 if (ret)
317 return ret;
318 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_LSB,
319 FIELD_GET(AD7779_FREQ_LSB_MSK, 0x0));
320 if (ret)
321 return ret;
322 }
323 ret = ad7779_spi_write(st, AD7779_REG_SRC_UPDATE, BIT(0));
324 if (ret)
325 return ret;
326
327 /* SRC update settling time */
328 fsleep(15);
329
330 ret = ad7779_spi_write(st, AD7779_REG_SRC_UPDATE, 0x0);
331 if (ret)
332 return ret;
333
334 /* SRC update settling time */
335 fsleep(15);
336
337 st->sampling_freq = sampling_freq;
338
339 return 0;
340 }
341
ad7779_get_filter(struct iio_dev * indio_dev,struct iio_chan_spec const * chan)342 static int ad7779_get_filter(struct iio_dev *indio_dev,
343 struct iio_chan_spec const *chan)
344 {
345 struct ad7779_state *st = iio_priv(indio_dev);
346 u8 temp;
347 int ret;
348
349 ret = ad7779_spi_read(st, AD7779_REG_GENERAL_USER_CONFIG_2, &temp);
350 if (ret)
351 return ret;
352
353 return FIELD_GET(AD7779_FILTER_MSK, temp);
354 }
355
ad7779_set_filter(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,unsigned int mode)356 static int ad7779_set_filter(struct iio_dev *indio_dev,
357 struct iio_chan_spec const *chan,
358 unsigned int mode)
359 {
360 struct ad7779_state *st = iio_priv(indio_dev);
361 int ret;
362
363 ret = ad7779_spi_write_mask(st,
364 AD7779_REG_GENERAL_USER_CONFIG_2,
365 AD7779_FILTER_MSK,
366 FIELD_PREP(AD7779_FILTER_MSK, mode));
367 if (ret)
368 return ret;
369
370 ret = ad7779_set_sampling_frequency(st, st->sampling_freq);
371 if (ret)
372 return ret;
373
374 st->filter_enabled = mode;
375
376 return 0;
377 }
378
ad7779_get_calibscale(struct ad7779_state * st,int channel)379 static int ad7779_get_calibscale(struct ad7779_state *st, int channel)
380 {
381 int ret;
382 u8 calibscale[3];
383
384 ret = ad7779_spi_read(st, AD7779_REG_CH_GAIN_LOWER_BYTE(channel),
385 &calibscale[0]);
386 if (ret)
387 return ret;
388
389 ret = ad7779_spi_read(st, AD7779_REG_CH_GAIN_MID_BYTE(channel),
390 &calibscale[1]);
391 if (ret)
392 return ret;
393
394 ret = ad7779_spi_read(st, AD7779_REG_CH_GAIN_UPPER_BYTE(channel),
395 &calibscale[2]);
396 if (ret)
397 return ret;
398
399 return get_unaligned_be24(calibscale);
400 }
401
ad7779_set_calibscale(struct ad7779_state * st,int channel,int val)402 static int ad7779_set_calibscale(struct ad7779_state *st, int channel, int val)
403 {
404 int ret;
405 unsigned int gain;
406 u8 gain_bytes[3];
407
408 /*
409 * The gain value is relative to 0x555555, which represents a gain of 1
410 */
411 gain = DIV_ROUND_CLOSEST_ULL((u64)val * 5592405LL, MEGA);
412 put_unaligned_be24(gain, gain_bytes);
413 ret = ad7779_spi_write(st, AD7779_REG_CH_GAIN_UPPER_BYTE(channel),
414 gain_bytes[0]);
415 if (ret)
416 return ret;
417
418 ret = ad7779_spi_write(st, AD7779_REG_CH_GAIN_MID_BYTE(channel),
419 gain_bytes[1]);
420 if (ret)
421 return ret;
422
423 return ad7779_spi_write(st, AD7779_REG_CH_GAIN_LOWER_BYTE(channel),
424 gain_bytes[2]);
425 }
426
ad7779_get_calibbias(struct ad7779_state * st,int channel)427 static int ad7779_get_calibbias(struct ad7779_state *st, int channel)
428 {
429 int ret;
430 u8 calibbias[3];
431
432 ret = ad7779_spi_read(st, AD7779_REG_CH_OFFSET_LOWER_BYTE(channel),
433 &calibbias[0]);
434 if (ret)
435 return ret;
436
437 ret = ad7779_spi_read(st, AD7779_REG_CH_OFFSET_MID_BYTE(channel),
438 &calibbias[1]);
439 if (ret)
440 return ret;
441
442 ret = ad7779_spi_read(st, AD7779_REG_CH_OFFSET_UPPER_BYTE(channel),
443 &calibbias[2]);
444 if (ret)
445 return ret;
446
447 return get_unaligned_be24(calibbias);
448 }
449
ad7779_set_calibbias(struct ad7779_state * st,int channel,int val)450 static int ad7779_set_calibbias(struct ad7779_state *st, int channel, int val)
451 {
452 int ret;
453 u8 calibbias[3];
454
455 put_unaligned_be24(val, calibbias);
456 ret = ad7779_spi_write(st, AD7779_REG_CH_OFFSET_UPPER_BYTE(channel),
457 calibbias[0]);
458 if (ret)
459 return ret;
460
461 ret = ad7779_spi_write(st, AD7779_REG_CH_OFFSET_MID_BYTE(channel),
462 calibbias[1]);
463 if (ret)
464 return ret;
465
466 return ad7779_spi_write(st, AD7779_REG_CH_OFFSET_LOWER_BYTE(channel),
467 calibbias[2]);
468 }
469
ad7779_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)470 static int ad7779_read_raw(struct iio_dev *indio_dev,
471 struct iio_chan_spec const *chan, int *val,
472 int *val2, long mask)
473 {
474 struct ad7779_state *st = iio_priv(indio_dev);
475 int ret;
476
477 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
478 switch (mask) {
479 case IIO_CHAN_INFO_CALIBSCALE:
480 ret = ad7779_get_calibscale(st, chan->channel);
481 if (ret < 0)
482 return ret;
483 *val = ret;
484 *val2 = GAIN_REL;
485 return IIO_VAL_FRACTIONAL;
486 case IIO_CHAN_INFO_CALIBBIAS:
487 ret = ad7779_get_calibbias(st, chan->channel);
488 if (ret < 0)
489 return ret;
490 *val = ret;
491 return IIO_VAL_INT;
492 case IIO_CHAN_INFO_SAMP_FREQ:
493 *val = st->sampling_freq;
494 if (*val < 0)
495 return -EINVAL;
496 return IIO_VAL_INT;
497 default:
498 return -EINVAL;
499 }
500 }
501 unreachable();
502 }
503
ad7779_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)504 static int ad7779_write_raw(struct iio_dev *indio_dev,
505 struct iio_chan_spec const *chan, int val, int val2,
506 long mask)
507 {
508 struct ad7779_state *st = iio_priv(indio_dev);
509
510 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
511 switch (mask) {
512 case IIO_CHAN_INFO_CALIBSCALE:
513 return ad7779_set_calibscale(st, chan->channel, val2);
514 case IIO_CHAN_INFO_CALIBBIAS:
515 return ad7779_set_calibbias(st, chan->channel, val);
516 case IIO_CHAN_INFO_SAMP_FREQ:
517 return ad7779_set_sampling_frequency(st, val);
518 default:
519 return -EINVAL;
520 }
521 }
522 unreachable();
523 }
524
ad7779_buffer_preenable(struct iio_dev * indio_dev)525 static int ad7779_buffer_preenable(struct iio_dev *indio_dev)
526 {
527 int ret;
528 struct ad7779_state *st = iio_priv(indio_dev);
529
530 ret = ad7779_spi_write_mask(st,
531 AD7779_REG_GENERAL_USER_CONFIG_3,
532 AD7779_MOD_SPI_EN_MSK,
533 FIELD_PREP(AD7779_MOD_SPI_EN_MSK, 1));
534 if (ret)
535 return ret;
536
537 /*
538 * DRDY output cannot be disabled at device level therefore we mask
539 * the irq at host end.
540 */
541 enable_irq(st->spi->irq);
542
543 return 0;
544 }
545
ad7779_buffer_postdisable(struct iio_dev * indio_dev)546 static int ad7779_buffer_postdisable(struct iio_dev *indio_dev)
547 {
548 struct ad7779_state *st = iio_priv(indio_dev);
549
550 disable_irq(st->spi->irq);
551
552 return ad7779_spi_write(st, AD7779_REG_GENERAL_USER_CONFIG_3,
553 AD7779_DISABLE_SD);
554 }
555
ad7779_trigger_handler(int irq,void * p)556 static irqreturn_t ad7779_trigger_handler(int irq, void *p)
557 {
558 struct iio_poll_func *pf = p;
559 struct iio_dev *indio_dev = pf->indio_dev;
560 struct ad7779_state *st = iio_priv(indio_dev);
561 int ret;
562 struct spi_transfer t = {
563 .rx_buf = st->data.chans,
564 .tx_buf = st->spidata_tx,
565 .len = AD7779_NUM_CHANNELS * AD7779_CHAN_DATA_SIZE,
566 };
567
568 st->spidata_tx[0] = AD7779_SPI_READ_CMD;
569 ret = spi_sync_transfer(st->spi, &t, 1);
570 if (ret) {
571 dev_err(&st->spi->dev, "SPI transfer error in IRQ handler");
572 goto exit_handler;
573 }
574
575 iio_push_to_buffers_with_timestamp(indio_dev, &st->data, pf->timestamp);
576
577 exit_handler:
578 iio_trigger_notify_done(indio_dev->trig);
579 return IRQ_HANDLED;
580 }
581
ad7779_reset(struct iio_dev * indio_dev,struct gpio_desc * reset_gpio)582 static int ad7779_reset(struct iio_dev *indio_dev, struct gpio_desc *reset_gpio)
583 {
584 struct ad7779_state *st = iio_priv(indio_dev);
585 int ret;
586 struct spi_transfer t = {
587 .tx_buf = st->reset_buf,
588 .len = 8,
589 };
590
591 if (reset_gpio) {
592 gpiod_set_value(reset_gpio, 1);
593 /* Delay for reset to occur is 225 microseconds */
594 fsleep(230);
595 ret = 0;
596 } else {
597 memset(st->reset_buf, 0xff, sizeof(st->reset_buf));
598 ret = spi_sync_transfer(st->spi, &t, 1);
599 if (ret)
600 return ret;
601 }
602
603 /* Delay for reset to occur is 225 microseconds */
604 fsleep(230);
605
606 return ret;
607 }
608
609 static const struct iio_info ad7779_info = {
610 .read_raw = ad7779_read_raw,
611 .write_raw = ad7779_write_raw,
612 .debugfs_reg_access = &ad7779_reg_access,
613 };
614
615 static const struct iio_enum ad7779_filter_enum = {
616 .items = ad7779_filter_type,
617 .num_items = ARRAY_SIZE(ad7779_filter_type),
618 .get = ad7779_get_filter,
619 .set = ad7779_set_filter,
620 };
621
622 static const struct iio_chan_spec_ext_info ad7779_ext_filter[] = {
623 IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad7779_filter_enum),
624 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL,
625 &ad7779_filter_enum),
626 { }
627 };
628
629 #define AD777x_CHAN_S(index, _ext_info) \
630 { \
631 .type = IIO_VOLTAGE, \
632 .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) | \
633 BIT(IIO_CHAN_INFO_CALIBBIAS), \
634 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
635 .address = (index), \
636 .indexed = 1, \
637 .channel = (index), \
638 .scan_index = (index), \
639 .ext_info = (_ext_info), \
640 .scan_type = { \
641 .sign = 's', \
642 .realbits = 24, \
643 .storagebits = 32, \
644 .endianness = IIO_BE, \
645 }, \
646 }
647
648 #define AD777x_CHAN_NO_FILTER_S(index) \
649 AD777x_CHAN_S(index, NULL)
650
651 #define AD777x_CHAN_FILTER_S(index) \
652 AD777x_CHAN_S(index, ad7779_ext_filter)
653 static const struct iio_chan_spec ad7779_channels[] = {
654 AD777x_CHAN_NO_FILTER_S(0),
655 AD777x_CHAN_NO_FILTER_S(1),
656 AD777x_CHAN_NO_FILTER_S(2),
657 AD777x_CHAN_NO_FILTER_S(3),
658 AD777x_CHAN_NO_FILTER_S(4),
659 AD777x_CHAN_NO_FILTER_S(5),
660 AD777x_CHAN_NO_FILTER_S(6),
661 AD777x_CHAN_NO_FILTER_S(7),
662 IIO_CHAN_SOFT_TIMESTAMP(8),
663 };
664
665 static const struct iio_chan_spec ad7779_channels_filter[] = {
666 AD777x_CHAN_FILTER_S(0),
667 AD777x_CHAN_FILTER_S(1),
668 AD777x_CHAN_FILTER_S(2),
669 AD777x_CHAN_FILTER_S(3),
670 AD777x_CHAN_FILTER_S(4),
671 AD777x_CHAN_FILTER_S(5),
672 AD777x_CHAN_FILTER_S(6),
673 AD777x_CHAN_FILTER_S(7),
674 IIO_CHAN_SOFT_TIMESTAMP(8),
675 };
676
677 static const struct iio_buffer_setup_ops ad7779_buffer_setup_ops = {
678 .preenable = ad7779_buffer_preenable,
679 .postdisable = ad7779_buffer_postdisable,
680 };
681
682 static const struct iio_trigger_ops ad7779_trigger_ops = {
683 .validate_device = iio_trigger_validate_own_device,
684 };
685
ad7779_conf(struct ad7779_state * st,struct gpio_desc * start_gpio)686 static int ad7779_conf(struct ad7779_state *st, struct gpio_desc *start_gpio)
687 {
688 int ret;
689
690 ret = ad7779_spi_write_mask(st, AD7779_REG_GEN_ERR_REG_1_EN,
691 AD7779_SPI_CRC_EN_MSK,
692 FIELD_PREP(AD7779_SPI_CRC_EN_MSK, 1));
693 if (ret)
694 return ret;
695
696 ret = ad7779_spi_write_mask(st, AD7779_REG_GENERAL_USER_CONFIG_1,
697 AD7779_USRMOD_INIT_MSK,
698 FIELD_PREP(AD7779_USRMOD_INIT_MSK, 5));
699 if (ret)
700 return ret;
701
702 ret = ad7779_spi_write_mask(st, AD7779_REG_DOUT_FORMAT,
703 AD7779_DCLK_CLK_DIV_MSK,
704 FIELD_PREP(AD7779_DCLK_CLK_DIV_MSK, 1));
705 if (ret)
706 return ret;
707
708 ret = ad7779_spi_write_mask(st, AD7779_REG_ADC_MUX_CONFIG,
709 AD7779_REFMUX_CTRL_MSK,
710 FIELD_PREP(AD7779_REFMUX_CTRL_MSK, 1));
711 if (ret)
712 return ret;
713
714 ret = ad7779_set_sampling_frequency(st, AD7779_DEFAULT_SAMPLING_FREQ);
715 if (ret)
716 return ret;
717
718 gpiod_set_value(start_gpio, 0);
719 /* Start setup time */
720 fsleep(15);
721 gpiod_set_value(start_gpio, 1);
722 /* Start setup time */
723 fsleep(15);
724 gpiod_set_value(start_gpio, 0);
725 /* Start setup time */
726 fsleep(15);
727
728 return 0;
729 }
730
ad7779_probe(struct spi_device * spi)731 static int ad7779_probe(struct spi_device *spi)
732 {
733 struct iio_dev *indio_dev;
734 struct ad7779_state *st;
735 struct gpio_desc *reset_gpio, *start_gpio;
736 struct device *dev = &spi->dev;
737 int ret = -EINVAL;
738
739 if (!spi->irq)
740 return dev_err_probe(dev, ret, "DRDY irq not present\n");
741
742 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
743 if (!indio_dev)
744 return -ENOMEM;
745
746 st = iio_priv(indio_dev);
747
748 ret = devm_regulator_bulk_get_enable(dev,
749 ARRAY_SIZE(ad7779_power_supplies),
750 ad7779_power_supplies);
751 if (ret)
752 return dev_err_probe(dev, ret,
753 "failed to get and enable supplies\n");
754
755 st->mclk = devm_clk_get_enabled(dev, "mclk");
756 if (IS_ERR(st->mclk))
757 return PTR_ERR(st->mclk);
758
759 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
760 if (IS_ERR(reset_gpio))
761 return PTR_ERR(reset_gpio);
762
763 start_gpio = devm_gpiod_get(dev, "start", GPIOD_OUT_HIGH);
764 if (IS_ERR(start_gpio))
765 return PTR_ERR(start_gpio);
766
767 crc8_populate_msb(ad7779_crc8_table, AD7779_CRC8_POLY);
768 st->spi = spi;
769
770 st->chip_info = spi_get_device_match_data(spi);
771 if (!st->chip_info)
772 return -ENODEV;
773
774 ret = ad7779_reset(indio_dev, reset_gpio);
775 if (ret)
776 return ret;
777
778 ret = ad7779_conf(st, start_gpio);
779 if (ret)
780 return ret;
781
782 indio_dev->name = st->chip_info->name;
783 indio_dev->info = &ad7779_info;
784 indio_dev->modes = INDIO_DIRECT_MODE;
785 indio_dev->channels = st->chip_info->channels;
786 indio_dev->num_channels = ARRAY_SIZE(ad7779_channels);
787
788 st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name,
789 iio_device_id(indio_dev));
790 if (!st->trig)
791 return -ENOMEM;
792
793 st->trig->ops = &ad7779_trigger_ops;
794
795 iio_trigger_set_drvdata(st->trig, st);
796
797 ret = devm_request_irq(dev, spi->irq, iio_trigger_generic_data_rdy_poll,
798 IRQF_ONESHOT | IRQF_NO_AUTOEN, indio_dev->name,
799 st->trig);
800 if (ret)
801 return dev_err_probe(dev, ret, "request IRQ %d failed\n",
802 st->spi->irq);
803
804 ret = devm_iio_trigger_register(dev, st->trig);
805 if (ret)
806 return ret;
807
808 indio_dev->trig = iio_trigger_get(st->trig);
809
810 init_completion(&st->completion);
811
812 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
813 &iio_pollfunc_store_time,
814 &ad7779_trigger_handler,
815 &ad7779_buffer_setup_ops);
816 if (ret)
817 return ret;
818
819 ret = ad7779_spi_write_mask(st, AD7779_REG_DOUT_FORMAT,
820 AD7779_DCLK_CLK_DIV_MSK,
821 FIELD_PREP(AD7779_DCLK_CLK_DIV_MSK, 7));
822 if (ret)
823 return ret;
824
825 return devm_iio_device_register(dev, indio_dev);
826 }
827
ad7779_suspend(struct device * dev)828 static int ad7779_suspend(struct device *dev)
829 {
830 struct iio_dev *indio_dev = dev_get_drvdata(dev);
831 struct ad7779_state *st = iio_priv(indio_dev);
832
833 return ad7779_spi_write_mask(st, AD7779_REG_GENERAL_USER_CONFIG_1,
834 AD7779_MOD_POWERMODE_MSK,
835 FIELD_PREP(AD7779_MOD_POWERMODE_MSK,
836 AD7779_LOW_POWER));
837 }
838
ad7779_resume(struct device * dev)839 static int ad7779_resume(struct device *dev)
840 {
841 struct iio_dev *indio_dev = dev_get_drvdata(dev);
842 struct ad7779_state *st = iio_priv(indio_dev);
843
844 return ad7779_spi_write_mask(st, AD7779_REG_GENERAL_USER_CONFIG_1,
845 AD7779_MOD_POWERMODE_MSK,
846 FIELD_PREP(AD7779_MOD_POWERMODE_MSK,
847 AD7779_HIGH_POWER));
848 }
849
850 static DEFINE_SIMPLE_DEV_PM_OPS(ad7779_pm_ops, ad7779_suspend, ad7779_resume);
851
852 static const struct ad7779_chip_info ad7770_chip_info = {
853 .name = "ad7770",
854 .channels = ad7779_channels,
855 };
856
857 static const struct ad7779_chip_info ad7771_chip_info = {
858 .name = "ad7771",
859 .channels = ad7779_channels_filter,
860 };
861
862 static const struct ad7779_chip_info ad7779_chip_info = {
863 .name = "ad7779",
864 .channels = ad7779_channels,
865 };
866
867 static const struct spi_device_id ad7779_id[] = {
868 {
869 .name = "ad7770",
870 .driver_data = (kernel_ulong_t)&ad7770_chip_info,
871 },
872 {
873 .name = "ad7771",
874 .driver_data = (kernel_ulong_t)&ad7771_chip_info,
875 },
876 {
877 .name = "ad7779",
878 .driver_data = (kernel_ulong_t)&ad7779_chip_info,
879 },
880 { }
881 };
882 MODULE_DEVICE_TABLE(spi, ad7779_id);
883
884 static const struct of_device_id ad7779_of_table[] = {
885 {
886 .compatible = "adi,ad7770",
887 .data = &ad7770_chip_info,
888 },
889 {
890 .compatible = "adi,ad7771",
891 .data = &ad7771_chip_info,
892 },
893 {
894 .compatible = "adi,ad7779",
895 .data = &ad7779_chip_info,
896 },
897 { }
898 };
899 MODULE_DEVICE_TABLE(of, ad7779_of_table);
900
901 static struct spi_driver ad7779_driver = {
902 .driver = {
903 .name = "ad7779",
904 .pm = pm_sleep_ptr(&ad7779_pm_ops),
905 .of_match_table = ad7779_of_table,
906 },
907 .probe = ad7779_probe,
908 .id_table = ad7779_id,
909 };
910 module_spi_driver(ad7779_driver);
911
912 MODULE_AUTHOR("Ramona Alexandra Nechita <[email protected]>");
913 MODULE_DESCRIPTION("Analog Devices AD7779 ADC");
914 MODULE_LICENSE("GPL");
915