1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018 Intel Corporation */
3
4 #include "igc_mac.h"
5 #include "igc_nvm.h"
6
7 /**
8 * igc_poll_eerd_eewr_done - Poll for EEPROM read/write completion
9 * @hw: pointer to the HW structure
10 * @ee_reg: EEPROM flag for polling
11 *
12 * Polls the EEPROM status bit for either read or write completion based
13 * upon the value of 'ee_reg'.
14 */
igc_poll_eerd_eewr_done(struct igc_hw * hw,int ee_reg)15 static s32 igc_poll_eerd_eewr_done(struct igc_hw *hw, int ee_reg)
16 {
17 s32 ret_val = -IGC_ERR_NVM;
18 u32 attempts = 100000;
19 u32 i, reg = 0;
20
21 for (i = 0; i < attempts; i++) {
22 if (ee_reg == IGC_NVM_POLL_READ)
23 reg = rd32(IGC_EERD);
24 else
25 reg = rd32(IGC_EEWR);
26
27 if (reg & IGC_NVM_RW_REG_DONE) {
28 ret_val = 0;
29 break;
30 }
31
32 udelay(5);
33 }
34
35 return ret_val;
36 }
37
38 /**
39 * igc_read_nvm_eerd - Reads EEPROM using EERD register
40 * @hw: pointer to the HW structure
41 * @offset: offset of word in the EEPROM to read
42 * @words: number of words to read
43 * @data: word read from the EEPROM
44 *
45 * Reads a 16 bit word from the EEPROM using the EERD register.
46 */
igc_read_nvm_eerd(struct igc_hw * hw,u16 offset,u16 words,u16 * data)47 s32 igc_read_nvm_eerd(struct igc_hw *hw, u16 offset, u16 words, u16 *data)
48 {
49 struct igc_nvm_info *nvm = &hw->nvm;
50 u32 i, eerd = 0;
51 s32 ret_val = 0;
52
53 /* A check for invalid values: offset too large, too many words,
54 * and not enough words.
55 */
56 if (offset >= nvm->word_size || (words > (nvm->word_size - offset)) ||
57 words == 0) {
58 hw_dbg("nvm parameter(s) out of bounds\n");
59 ret_val = -IGC_ERR_NVM;
60 goto out;
61 }
62
63 for (i = 0; i < words; i++) {
64 eerd = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) +
65 IGC_NVM_RW_REG_START;
66
67 wr32(IGC_EERD, eerd);
68 ret_val = igc_poll_eerd_eewr_done(hw, IGC_NVM_POLL_READ);
69 if (ret_val)
70 break;
71
72 data[i] = (rd32(IGC_EERD) >> IGC_NVM_RW_REG_DATA);
73 }
74
75 out:
76 return ret_val;
77 }
78
79 /**
80 * igc_read_mac_addr - Read device MAC address
81 * @hw: pointer to the HW structure
82 */
igc_read_mac_addr(struct igc_hw * hw)83 s32 igc_read_mac_addr(struct igc_hw *hw)
84 {
85 u32 rar_high;
86 u32 rar_low;
87 u16 i;
88
89 rar_high = rd32(IGC_RAH(0));
90 rar_low = rd32(IGC_RAL(0));
91
92 for (i = 0; i < IGC_RAL_MAC_ADDR_LEN; i++)
93 hw->mac.perm_addr[i] = (u8)(rar_low >> (i * 8));
94
95 for (i = 0; i < IGC_RAH_MAC_ADDR_LEN; i++)
96 hw->mac.perm_addr[i + 4] = (u8)(rar_high >> (i * 8));
97
98 for (i = 0; i < ETH_ALEN; i++)
99 hw->mac.addr[i] = hw->mac.perm_addr[i];
100
101 return 0;
102 }
103
104 /**
105 * igc_validate_nvm_checksum - Validate EEPROM checksum
106 * @hw: pointer to the HW structure
107 *
108 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
109 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
110 */
igc_validate_nvm_checksum(struct igc_hw * hw)111 s32 igc_validate_nvm_checksum(struct igc_hw *hw)
112 {
113 u16 checksum = 0;
114 u16 i, nvm_data;
115 s32 ret_val = 0;
116
117 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
118 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
119 if (ret_val) {
120 hw_dbg("NVM Read Error\n");
121 goto out;
122 }
123 checksum += nvm_data;
124 }
125
126 if (checksum != (u16)NVM_SUM) {
127 hw_dbg("NVM Checksum Invalid\n");
128 ret_val = -IGC_ERR_NVM;
129 goto out;
130 }
131
132 out:
133 return ret_val;
134 }
135
136 /**
137 * igc_update_nvm_checksum - Update EEPROM checksum
138 * @hw: pointer to the HW structure
139 *
140 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
141 * up to the checksum. Then calculates the EEPROM checksum and writes the
142 * value to the EEPROM.
143 */
igc_update_nvm_checksum(struct igc_hw * hw)144 s32 igc_update_nvm_checksum(struct igc_hw *hw)
145 {
146 u16 checksum = 0;
147 u16 i, nvm_data;
148 s32 ret_val;
149
150 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
151 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
152 if (ret_val) {
153 hw_dbg("NVM Read Error while updating checksum.\n");
154 goto out;
155 }
156 checksum += nvm_data;
157 }
158 checksum = (u16)NVM_SUM - checksum;
159 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
160 if (ret_val)
161 hw_dbg("NVM Write Error while updating checksum.\n");
162
163 out:
164 return ret_val;
165 }
166