1 // SPDX-License-Identifier: GPL-2.0
2 /* Intel DWMAC platform driver
3  *
4  * Copyright(C) 2020 Intel Corporation
5  */
6 
7 #include <linux/ethtool.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11 #include <linux/property.h>
12 #include <linux/stmmac.h>
13 
14 #include "dwmac4.h"
15 #include "stmmac.h"
16 #include "stmmac_platform.h"
17 
18 struct intel_dwmac {
19 	struct device *dev;
20 	struct clk *tx_clk;
21 	const struct intel_dwmac_data *data;
22 };
23 
24 struct intel_dwmac_data {
25 	void (*fix_mac_speed)(void *priv, unsigned int speed, unsigned int mode);
26 	unsigned long ptp_ref_clk_rate;
27 	unsigned long tx_clk_rate;
28 	bool tx_clk_en;
29 };
30 
kmb_eth_fix_mac_speed(void * priv,unsigned int speed,unsigned int mode)31 static void kmb_eth_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode)
32 {
33 	struct intel_dwmac *dwmac = priv;
34 	long rate;
35 	int ret;
36 
37 	rate = rgmii_clock(speed);
38 	if (rate < 0) {
39 		dev_err(dwmac->dev, "Invalid speed\n");
40 		return;
41 	}
42 
43 	ret = clk_set_rate(dwmac->tx_clk, rate);
44 	if (ret)
45 		dev_err(dwmac->dev, "Failed to configure tx clock rate\n");
46 }
47 
48 static const struct intel_dwmac_data kmb_data = {
49 	.fix_mac_speed = kmb_eth_fix_mac_speed,
50 	.ptp_ref_clk_rate = 200000000,
51 	.tx_clk_rate = 125000000,
52 	.tx_clk_en = true,
53 };
54 
55 static const struct of_device_id intel_eth_plat_match[] = {
56 	{ .compatible = "intel,keembay-dwmac", .data = &kmb_data },
57 	{ }
58 };
59 MODULE_DEVICE_TABLE(of, intel_eth_plat_match);
60 
intel_eth_plat_probe(struct platform_device * pdev)61 static int intel_eth_plat_probe(struct platform_device *pdev)
62 {
63 	struct plat_stmmacenet_data *plat_dat;
64 	struct stmmac_resources stmmac_res;
65 	struct intel_dwmac *dwmac;
66 	unsigned long rate;
67 	int ret;
68 
69 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
70 	if (ret)
71 		return ret;
72 
73 	plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
74 	if (IS_ERR(plat_dat)) {
75 		dev_err(&pdev->dev, "dt configuration failed\n");
76 		return PTR_ERR(plat_dat);
77 	}
78 
79 	dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
80 	if (!dwmac)
81 		return -ENOMEM;
82 
83 	dwmac->dev = &pdev->dev;
84 	dwmac->tx_clk = NULL;
85 
86 	/*
87 	 * This cannot return NULL at this point because the driver’s
88 	 * compatibility with the device has already been validated in
89 	 * platform_match().
90 	 */
91 	dwmac->data = device_get_match_data(&pdev->dev);
92 	if (dwmac->data->fix_mac_speed)
93 		plat_dat->fix_mac_speed = dwmac->data->fix_mac_speed;
94 
95 	/* Enable TX clock */
96 	if (dwmac->data->tx_clk_en) {
97 		dwmac->tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
98 		if (IS_ERR(dwmac->tx_clk))
99 			return PTR_ERR(dwmac->tx_clk);
100 
101 		ret = clk_prepare_enable(dwmac->tx_clk);
102 		if (ret) {
103 			dev_err(&pdev->dev,
104 				"Failed to enable tx_clk\n");
105 			return ret;
106 		}
107 
108 		/* Check and configure TX clock rate */
109 		rate = clk_get_rate(dwmac->tx_clk);
110 		if (dwmac->data->tx_clk_rate &&
111 		    rate != dwmac->data->tx_clk_rate) {
112 			rate = dwmac->data->tx_clk_rate;
113 			ret = clk_set_rate(dwmac->tx_clk, rate);
114 			if (ret) {
115 				dev_err(&pdev->dev,
116 					"Failed to set tx_clk\n");
117 				goto err_tx_clk_disable;
118 			}
119 		}
120 
121 		/* Check and configure PTP ref clock rate */
122 		rate = clk_get_rate(plat_dat->clk_ptp_ref);
123 		if (dwmac->data->ptp_ref_clk_rate &&
124 		    rate != dwmac->data->ptp_ref_clk_rate) {
125 			rate = dwmac->data->ptp_ref_clk_rate;
126 			ret = clk_set_rate(plat_dat->clk_ptp_ref, rate);
127 			if (ret) {
128 				dev_err(&pdev->dev,
129 					"Failed to set clk_ptp_ref\n");
130 				goto err_tx_clk_disable;
131 			}
132 		}
133 	}
134 
135 	plat_dat->bsp_priv = dwmac;
136 	plat_dat->eee_usecs_rate = plat_dat->clk_ptp_rate;
137 
138 	if (plat_dat->eee_usecs_rate > 0) {
139 		u32 tx_lpi_usec;
140 
141 		tx_lpi_usec = (plat_dat->eee_usecs_rate / 1000000) - 1;
142 		writel(tx_lpi_usec, stmmac_res.addr + GMAC_1US_TIC_COUNTER);
143 	}
144 
145 	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
146 	if (ret)
147 		goto err_tx_clk_disable;
148 
149 	return 0;
150 
151 err_tx_clk_disable:
152 	if (dwmac->data->tx_clk_en)
153 		clk_disable_unprepare(dwmac->tx_clk);
154 	return ret;
155 }
156 
intel_eth_plat_remove(struct platform_device * pdev)157 static void intel_eth_plat_remove(struct platform_device *pdev)
158 {
159 	struct intel_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev);
160 
161 	stmmac_pltfr_remove(pdev);
162 	if (dwmac->data->tx_clk_en)
163 		clk_disable_unprepare(dwmac->tx_clk);
164 }
165 
166 static struct platform_driver intel_eth_plat_driver = {
167 	.probe  = intel_eth_plat_probe,
168 	.remove = intel_eth_plat_remove,
169 	.driver = {
170 		.name		= "intel-eth-plat",
171 		.pm		= &stmmac_pltfr_pm_ops,
172 		.of_match_table = intel_eth_plat_match,
173 	},
174 };
175 module_platform_driver(intel_eth_plat_driver);
176 
177 MODULE_LICENSE("GPL v2");
178 MODULE_DESCRIPTION("Intel DWMAC platform driver");
179