1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018-2024 Intel Corporation
4 */
5 #include <linux/dmi.h>
6 #include "iwl-trans.h"
7 #include "iwl-fh.h"
8 #include "iwl-context-info-gen3.h"
9 #include "internal.h"
10 #include "iwl-prph.h"
11
12 static const struct dmi_system_id dmi_force_scu_active_approved_list[] = {
13 { .ident = "DELL",
14 .matches = {
15 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
16 },
17 },
18 { .ident = "DELL",
19 .matches = {
20 DMI_MATCH(DMI_SYS_VENDOR, "Alienware"),
21 },
22 },
23 /* keep last */
24 {}
25 };
26
iwl_is_force_scu_active_approved(void)27 static bool iwl_is_force_scu_active_approved(void)
28 {
29 return !!dmi_check_system(dmi_force_scu_active_approved_list);
30 }
31
32 static void
iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans * trans,struct iwl_prph_scratch_hwm_cfg * dbg_cfg,u32 * control_flags)33 iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans,
34 struct iwl_prph_scratch_hwm_cfg *dbg_cfg,
35 u32 *control_flags)
36 {
37 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
38 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
39 u32 dbg_flags = 0;
40
41 if (!iwl_trans_dbg_ini_valid(trans)) {
42 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
43
44 iwl_pcie_alloc_fw_monitor(trans, 0);
45
46 if (fw_mon->size) {
47 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
48
49 IWL_DEBUG_FW(trans,
50 "WRT: Applying DRAM buffer destination\n");
51
52 dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical);
53 dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size);
54 }
55
56 goto out;
57 }
58
59 fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id];
60
61 switch (le32_to_cpu(fw_mon_cfg->buf_location)) {
62 case IWL_FW_INI_LOCATION_SRAM_PATH:
63 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL;
64 IWL_DEBUG_FW(trans,
65 "WRT: Applying SMEM buffer destination\n");
66 break;
67
68 case IWL_FW_INI_LOCATION_NPK_PATH:
69 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF;
70 IWL_DEBUG_FW(trans,
71 "WRT: Applying NPK buffer destination\n");
72 break;
73
74 case IWL_FW_INI_LOCATION_DRAM_PATH:
75 if (trans->dbg.fw_mon_ini[alloc_id].num_frags) {
76 struct iwl_dram_data *frag =
77 &trans->dbg.fw_mon_ini[alloc_id].frags[0];
78 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
79 dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical);
80 dbg_cfg->hwm_size = cpu_to_le32(frag->size);
81 dbg_cfg->debug_token_config = cpu_to_le32(trans->dbg.ucode_preset);
82 IWL_DEBUG_FW(trans,
83 "WRT: Applying DRAM destination (debug_token_config=%u)\n",
84 dbg_cfg->debug_token_config);
85 IWL_DEBUG_FW(trans,
86 "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n",
87 alloc_id,
88 trans->dbg.fw_mon_ini[alloc_id].num_frags);
89 }
90 break;
91 default:
92 IWL_DEBUG_FW(trans, "WRT: Invalid buffer destination (%d)\n",
93 le32_to_cpu(fw_mon_cfg->buf_location));
94 }
95 out:
96 if (dbg_flags)
97 *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags;
98 }
99
iwl_pcie_ctxt_info_gen3_init(struct iwl_trans * trans,const struct fw_img * fw)100 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
101 const struct fw_img *fw)
102 {
103 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
104 struct iwl_context_info_gen3 *ctxt_info_gen3;
105 struct iwl_prph_scratch *prph_scratch;
106 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl;
107 struct iwl_prph_info *prph_info;
108 u32 control_flags = 0;
109 u32 control_flags_ext = 0;
110 int ret;
111 int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
112 trans->cfg->min_txq_size);
113
114 switch (trans_pcie->rx_buf_size) {
115 case IWL_AMSDU_DEF:
116 return -EINVAL;
117 case IWL_AMSDU_2K:
118 break;
119 case IWL_AMSDU_4K:
120 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
121 break;
122 case IWL_AMSDU_8K:
123 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
124 /* if firmware supports the ext size, tell it */
125 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K;
126 break;
127 case IWL_AMSDU_12K:
128 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
129 /* if firmware supports the ext size, tell it */
130 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K;
131 break;
132 }
133
134 if (trans->dsbr_urm_fw_dependent)
135 control_flags_ext |= IWL_PRPH_SCRATCH_EXT_URM_FW;
136
137 if (trans->dsbr_urm_permanent)
138 control_flags_ext |= IWL_PRPH_SCRATCH_EXT_URM_PERM;
139
140 /* Allocate prph scratch */
141 prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch),
142 &trans_pcie->prph_scratch_dma_addr,
143 GFP_KERNEL);
144 if (!prph_scratch)
145 return -ENOMEM;
146
147 prph_sc_ctrl = &prph_scratch->ctrl_cfg;
148
149 prph_sc_ctrl->version.version = 0;
150 prph_sc_ctrl->version.mac_id =
151 cpu_to_le16((u16)trans->hw_rev);
152 prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4);
153
154 control_flags |= IWL_PRPH_SCRATCH_MTR_MODE;
155 control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT;
156
157 if (trans->trans_cfg->imr_enabled)
158 control_flags |= IWL_PRPH_SCRATCH_IMR_DEBUG_EN;
159
160 if (CSR_HW_REV_TYPE(trans->hw_rev) == IWL_CFG_MAC_TYPE_GL &&
161 iwl_is_force_scu_active_approved()) {
162 control_flags |= IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE;
163 IWL_DEBUG_FW(trans,
164 "Context Info: Set SCU_FORCE_ACTIVE (0x%x) in control_flags\n",
165 IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE);
166 }
167
168 /* initialize RX default queue */
169 prph_sc_ctrl->rbd_cfg.free_rbd_addr =
170 cpu_to_le64(trans_pcie->rxq->bd_dma);
171
172 iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg,
173 &control_flags);
174 prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags);
175 prph_sc_ctrl->control.control_flags_ext = cpu_to_le32(control_flags_ext);
176
177 /* initialize the Step equalizer data */
178 prph_sc_ctrl->step_cfg.mbx_addr_0 = cpu_to_le32(trans->mbx_addr_0_step);
179 prph_sc_ctrl->step_cfg.mbx_addr_1 = cpu_to_le32(trans->mbx_addr_1_step);
180
181 /* allocate ucode sections in dram and set addresses */
182 ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram);
183 if (ret)
184 goto err_free_prph_scratch;
185
186
187 /* Allocate prph information
188 * currently we don't assign to the prph info anything, but it would get
189 * assigned later
190 *
191 * We also use the second half of this page to give the device some
192 * dummy TR/CR tail pointers - which shouldn't be necessary as we don't
193 * use this, but the hardware still reads/writes there and we can't let
194 * it go do that with a NULL pointer.
195 */
196 BUILD_BUG_ON(sizeof(*prph_info) > PAGE_SIZE / 2);
197 prph_info = dma_alloc_coherent(trans->dev, PAGE_SIZE,
198 &trans_pcie->prph_info_dma_addr,
199 GFP_KERNEL);
200 if (!prph_info) {
201 ret = -ENOMEM;
202 goto err_free_prph_scratch;
203 }
204
205 /* Allocate context info */
206 ctxt_info_gen3 = dma_alloc_coherent(trans->dev,
207 sizeof(*ctxt_info_gen3),
208 &trans_pcie->ctxt_info_dma_addr,
209 GFP_KERNEL);
210 if (!ctxt_info_gen3) {
211 ret = -ENOMEM;
212 goto err_free_prph_info;
213 }
214
215 ctxt_info_gen3->prph_info_base_addr =
216 cpu_to_le64(trans_pcie->prph_info_dma_addr);
217 ctxt_info_gen3->prph_scratch_base_addr =
218 cpu_to_le64(trans_pcie->prph_scratch_dma_addr);
219 ctxt_info_gen3->prph_scratch_size =
220 cpu_to_le32(sizeof(*prph_scratch));
221 ctxt_info_gen3->cr_head_idx_arr_base_addr =
222 cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
223 ctxt_info_gen3->tr_tail_idx_arr_base_addr =
224 cpu_to_le64(trans_pcie->prph_info_dma_addr + PAGE_SIZE / 2);
225 ctxt_info_gen3->cr_tail_idx_arr_base_addr =
226 cpu_to_le64(trans_pcie->prph_info_dma_addr + 3 * PAGE_SIZE / 4);
227 ctxt_info_gen3->mtr_base_addr =
228 cpu_to_le64(trans_pcie->txqs.txq[trans_pcie->txqs.cmd.q_id]->dma_addr);
229 ctxt_info_gen3->mcr_base_addr =
230 cpu_to_le64(trans_pcie->rxq->used_bd_dma);
231 ctxt_info_gen3->mtr_size =
232 cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size));
233 ctxt_info_gen3->mcr_size =
234 cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds));
235
236 trans_pcie->ctxt_info_gen3 = ctxt_info_gen3;
237 trans_pcie->prph_info = prph_info;
238 trans_pcie->prph_scratch = prph_scratch;
239
240 /* Allocate IML */
241 trans_pcie->iml = dma_alloc_coherent(trans->dev, trans->iml_len,
242 &trans_pcie->iml_dma_addr,
243 GFP_KERNEL);
244 if (!trans_pcie->iml) {
245 ret = -ENOMEM;
246 goto err_free_ctxt_info;
247 }
248
249 memcpy(trans_pcie->iml, trans->iml, trans->iml_len);
250
251 iwl_enable_fw_load_int_ctx_info(trans);
252
253 /* kick FW self load */
254 iwl_write64(trans, CSR_CTXT_INFO_ADDR,
255 trans_pcie->ctxt_info_dma_addr);
256 iwl_write64(trans, CSR_IML_DATA_ADDR,
257 trans_pcie->iml_dma_addr);
258 iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len);
259
260 iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,
261 CSR_AUTO_FUNC_BOOT_ENA);
262
263 return 0;
264
265 err_free_ctxt_info:
266 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
267 trans_pcie->ctxt_info_gen3,
268 trans_pcie->ctxt_info_dma_addr);
269 trans_pcie->ctxt_info_gen3 = NULL;
270 err_free_prph_info:
271 dma_free_coherent(trans->dev, PAGE_SIZE, prph_info,
272 trans_pcie->prph_info_dma_addr);
273
274 err_free_prph_scratch:
275 dma_free_coherent(trans->dev,
276 sizeof(*prph_scratch),
277 prph_scratch,
278 trans_pcie->prph_scratch_dma_addr);
279 return ret;
280
281 }
282
iwl_pcie_ctxt_info_gen3_free(struct iwl_trans * trans,bool alive)283 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive)
284 {
285 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
286
287 if (trans_pcie->iml) {
288 dma_free_coherent(trans->dev, trans->iml_len, trans_pcie->iml,
289 trans_pcie->iml_dma_addr);
290 trans_pcie->iml_dma_addr = 0;
291 trans_pcie->iml = NULL;
292 }
293
294 iwl_pcie_ctxt_info_free_fw_img(trans);
295
296 if (alive)
297 return;
298
299 if (!trans_pcie->ctxt_info_gen3)
300 return;
301
302 /* ctxt_info_gen3 and prph_scratch are still needed for PNVM load */
303 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
304 trans_pcie->ctxt_info_gen3,
305 trans_pcie->ctxt_info_dma_addr);
306 trans_pcie->ctxt_info_dma_addr = 0;
307 trans_pcie->ctxt_info_gen3 = NULL;
308
309 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch),
310 trans_pcie->prph_scratch,
311 trans_pcie->prph_scratch_dma_addr);
312 trans_pcie->prph_scratch_dma_addr = 0;
313 trans_pcie->prph_scratch = NULL;
314
315 /* this is needed for the entire lifetime */
316 dma_free_coherent(trans->dev, PAGE_SIZE, trans_pcie->prph_info,
317 trans_pcie->prph_info_dma_addr);
318 trans_pcie->prph_info_dma_addr = 0;
319 trans_pcie->prph_info = NULL;
320 }
321
iwl_pcie_load_payloads_continuously(struct iwl_trans * trans,const struct iwl_pnvm_image * pnvm_data,struct iwl_dram_data * dram)322 static int iwl_pcie_load_payloads_continuously(struct iwl_trans *trans,
323 const struct iwl_pnvm_image *pnvm_data,
324 struct iwl_dram_data *dram)
325 {
326 u32 len, len0, len1;
327
328 if (pnvm_data->n_chunks != UNFRAGMENTED_PNVM_PAYLOADS_NUMBER) {
329 IWL_DEBUG_FW(trans, "expected 2 payloads, got %d.\n",
330 pnvm_data->n_chunks);
331 return -EINVAL;
332 }
333
334 len0 = pnvm_data->chunks[0].len;
335 len1 = pnvm_data->chunks[1].len;
336 if (len1 > 0xFFFFFFFF - len0) {
337 IWL_DEBUG_FW(trans, "sizes of payloads overflow.\n");
338 return -EINVAL;
339 }
340 len = len0 + len1;
341
342 dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len,
343 &dram->physical);
344 if (!dram->block) {
345 IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA.\n");
346 return -ENOMEM;
347 }
348
349 dram->size = len;
350 memcpy(dram->block, pnvm_data->chunks[0].data, len0);
351 memcpy((u8 *)dram->block + len0, pnvm_data->chunks[1].data, len1);
352
353 return 0;
354 }
355
iwl_pcie_load_payloads_segments(struct iwl_trans * trans,struct iwl_dram_regions * dram_regions,const struct iwl_pnvm_image * pnvm_data)356 static int iwl_pcie_load_payloads_segments
357 (struct iwl_trans *trans,
358 struct iwl_dram_regions *dram_regions,
359 const struct iwl_pnvm_image *pnvm_data)
360 {
361 struct iwl_dram_data *cur_payload_dram = &dram_regions->drams[0];
362 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc;
363 struct iwl_prph_scrath_mem_desc_addr_array *addresses;
364 const void *data;
365 u32 len;
366 int i;
367
368 /* allocate and init DRAM descriptors array */
369 len = sizeof(struct iwl_prph_scrath_mem_desc_addr_array);
370 desc_dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent
371 (trans,
372 len,
373 &desc_dram->physical);
374 if (!desc_dram->block) {
375 IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA.\n");
376 return -ENOMEM;
377 }
378 desc_dram->size = len;
379 memset(desc_dram->block, 0, len);
380
381 /* allocate DRAM region for each payload */
382 dram_regions->n_regions = 0;
383 for (i = 0; i < pnvm_data->n_chunks; i++) {
384 len = pnvm_data->chunks[i].len;
385 data = pnvm_data->chunks[i].data;
386
387 if (iwl_pcie_ctxt_info_alloc_dma(trans,
388 data,
389 len,
390 cur_payload_dram)) {
391 iwl_trans_pcie_free_pnvm_dram_regions(dram_regions,
392 trans->dev);
393 return -ENOMEM;
394 }
395
396 dram_regions->n_regions++;
397 cur_payload_dram++;
398 }
399
400 /* fill desc with the DRAM payloads addresses */
401 addresses = desc_dram->block;
402 for (i = 0; i < pnvm_data->n_chunks; i++) {
403 addresses->mem_descs[i] =
404 cpu_to_le64(dram_regions->drams[i].physical);
405 }
406
407 return 0;
408
409 }
410
iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans * trans,const struct iwl_pnvm_image * pnvm_payloads,const struct iwl_ucode_capabilities * capa)411 int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans,
412 const struct iwl_pnvm_image *pnvm_payloads,
413 const struct iwl_ucode_capabilities *capa)
414 {
415 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
416 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
417 &trans_pcie->prph_scratch->ctrl_cfg;
418 struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data;
419 int ret = 0;
420
421 /* only allocate the DRAM if not allocated yet */
422 if (trans->pnvm_loaded)
423 return 0;
424
425 if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size))
426 return -EBUSY;
427
428 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
429 return 0;
430
431 if (!pnvm_payloads->n_chunks) {
432 IWL_DEBUG_FW(trans, "no payloads\n");
433 return -EINVAL;
434 }
435
436 /* save payloads in several DRAM sections */
437 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) {
438 ret = iwl_pcie_load_payloads_segments(trans,
439 dram_regions,
440 pnvm_payloads);
441 if (!ret)
442 trans->pnvm_loaded = true;
443 } else {
444 /* save only in one DRAM section */
445 ret = iwl_pcie_load_payloads_continuously
446 (trans,
447 pnvm_payloads,
448 &dram_regions->drams[0]);
449 if (!ret) {
450 dram_regions->n_regions = 1;
451 trans->pnvm_loaded = true;
452 }
453 }
454
455 return ret;
456 }
457
458 static inline size_t
iwl_dram_regions_size(const struct iwl_dram_regions * dram_regions)459 iwl_dram_regions_size(const struct iwl_dram_regions *dram_regions)
460 {
461 size_t total_size = 0;
462 int i;
463
464 for (i = 0; i < dram_regions->n_regions; i++)
465 total_size += dram_regions->drams[i].size;
466
467 return total_size;
468 }
469
iwl_pcie_set_pnvm_segments(struct iwl_trans * trans)470 static void iwl_pcie_set_pnvm_segments(struct iwl_trans *trans)
471 {
472 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
473 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
474 &trans_pcie->prph_scratch->ctrl_cfg;
475 struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data;
476
477 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr =
478 cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical);
479 prph_sc_ctrl->pnvm_cfg.pnvm_size =
480 cpu_to_le32(iwl_dram_regions_size(dram_regions));
481 }
482
iwl_pcie_set_continuous_pnvm(struct iwl_trans * trans)483 static void iwl_pcie_set_continuous_pnvm(struct iwl_trans *trans)
484 {
485 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
486 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
487 &trans_pcie->prph_scratch->ctrl_cfg;
488
489 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr =
490 cpu_to_le64(trans_pcie->pnvm_data.drams[0].physical);
491 prph_sc_ctrl->pnvm_cfg.pnvm_size =
492 cpu_to_le32(trans_pcie->pnvm_data.drams[0].size);
493 }
494
iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans * trans,const struct iwl_ucode_capabilities * capa)495 void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
496 const struct iwl_ucode_capabilities *capa)
497 {
498 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
499 return;
500
501 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG))
502 iwl_pcie_set_pnvm_segments(trans);
503 else
504 iwl_pcie_set_continuous_pnvm(trans);
505 }
506
iwl_trans_pcie_ctx_info_gen3_load_reduce_power(struct iwl_trans * trans,const struct iwl_pnvm_image * payloads,const struct iwl_ucode_capabilities * capa)507 int iwl_trans_pcie_ctx_info_gen3_load_reduce_power(struct iwl_trans *trans,
508 const struct iwl_pnvm_image *payloads,
509 const struct iwl_ucode_capabilities *capa)
510 {
511 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
512 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
513 &trans_pcie->prph_scratch->ctrl_cfg;
514 struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data;
515 int ret = 0;
516
517 /* only allocate the DRAM if not allocated yet */
518 if (trans->reduce_power_loaded)
519 return 0;
520
521 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
522 return 0;
523
524 if (WARN_ON(prph_sc_ctrl->reduce_power_cfg.size))
525 return -EBUSY;
526
527 if (!payloads->n_chunks) {
528 IWL_DEBUG_FW(trans, "no payloads\n");
529 return -EINVAL;
530 }
531
532 /* save payloads in several DRAM sections */
533 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) {
534 ret = iwl_pcie_load_payloads_segments(trans,
535 dram_regions,
536 payloads);
537 if (!ret)
538 trans->reduce_power_loaded = true;
539 } else {
540 /* save only in one DRAM section */
541 ret = iwl_pcie_load_payloads_continuously
542 (trans,
543 payloads,
544 &dram_regions->drams[0]);
545 if (!ret) {
546 dram_regions->n_regions = 1;
547 trans->reduce_power_loaded = true;
548 }
549 }
550
551 return ret;
552 }
553
iwl_pcie_set_reduce_power_segments(struct iwl_trans * trans)554 static void iwl_pcie_set_reduce_power_segments(struct iwl_trans *trans)
555 {
556 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
557 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
558 &trans_pcie->prph_scratch->ctrl_cfg;
559 struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data;
560
561 prph_sc_ctrl->reduce_power_cfg.base_addr =
562 cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical);
563 prph_sc_ctrl->reduce_power_cfg.size =
564 cpu_to_le32(iwl_dram_regions_size(dram_regions));
565 }
566
iwl_pcie_set_continuous_reduce_power(struct iwl_trans * trans)567 static void iwl_pcie_set_continuous_reduce_power(struct iwl_trans *trans)
568 {
569 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
570 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
571 &trans_pcie->prph_scratch->ctrl_cfg;
572
573 prph_sc_ctrl->reduce_power_cfg.base_addr =
574 cpu_to_le64(trans_pcie->reduced_tables_data.drams[0].physical);
575 prph_sc_ctrl->reduce_power_cfg.size =
576 cpu_to_le32(trans_pcie->reduced_tables_data.drams[0].size);
577 }
578
579 void
iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans * trans,const struct iwl_ucode_capabilities * capa)580 iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans,
581 const struct iwl_ucode_capabilities *capa)
582 {
583 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
584 return;
585
586 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG))
587 iwl_pcie_set_reduce_power_segments(trans);
588 else
589 iwl_pcie_set_continuous_reduce_power(trans);
590 }
591
592